It has been mathematically shown that the testing problem is NP complete. Numerous attempts have been made in creating and designing algorithms to successfully test a digital circuit for all faults in computational linear time. However, due to the complexity of the NP problem, all these attempts start becoming exponential with an increase in circuit size and complexity. Algorithms have been proposed where successful vectors have been used to search for more test vectors with similar properties. However, this leads to a bottleneck when trying to find hard to find stuck-at faults which have only one or two unique tests and their properties may not match other previously successful tests. We propose a new probability based algorithm where new test vectors are generated based on the input probability correlation of previously unsuccessful test vectors. By looking at the correlation between the primary inputs for previously generated test vectors, we use the probability information of 1's or 0's at a primary input with respect to other inputs to skew the search in the test vector space. We have shown test time improvements for a 10 input AND gate, c17 and c432 benchmark circuits. We have also shown improvements when comparing our algorithm with a random test generator and weighted-random test generator.
{"title":"A New Test Vector Search Algorithm for a Single Stuck-at Fault Using Probabilistic Correlation","authors":"M. Venkatasubramanian, V. Agrawal","doi":"10.1109/NATW.2014.20","DOIUrl":"https://doi.org/10.1109/NATW.2014.20","url":null,"abstract":"It has been mathematically shown that the testing problem is NP complete. Numerous attempts have been made in creating and designing algorithms to successfully test a digital circuit for all faults in computational linear time. However, due to the complexity of the NP problem, all these attempts start becoming exponential with an increase in circuit size and complexity. Algorithms have been proposed where successful vectors have been used to search for more test vectors with similar properties. However, this leads to a bottleneck when trying to find hard to find stuck-at faults which have only one or two unique tests and their properties may not match other previously successful tests. We propose a new probability based algorithm where new test vectors are generated based on the input probability correlation of previously unsuccessful test vectors. By looking at the correlation between the primary inputs for previously generated test vectors, we use the probability information of 1's or 0's at a primary input with respect to other inputs to skew the search in the test vector space. We have shown test time improvements for a 10 input AND gate, c17 and c432 benchmark circuits. We have also shown improvements when comparing our algorithm with a random test generator and weighted-random test generator.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115134389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses power system fault simulation/modeling aspects on protection and control performance, requirements and technical problems often occurred during relay testing and commissioning, analyzing testing conditions, protection schemes and solutions for power systems, discussing major factors to be address during fault simulations in order to have successful outcomes for relay testing and acceptance test for protection and control systems.
{"title":"Power System Fault Modeling/Simulation Protective Relay Testing and Simulation","authors":"G. Tang","doi":"10.1109/NATW.2014.16","DOIUrl":"https://doi.org/10.1109/NATW.2014.16","url":null,"abstract":"This paper discusses power system fault simulation/modeling aspects on protection and control performance, requirements and technical problems often occurred during relay testing and commissioning, analyzing testing conditions, protection schemes and solutions for power systems, discussing major factors to be address during fault simulations in order to have successful outcomes for relay testing and acceptance test for protection and control systems.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114778796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yukun Gao, Tengteng Zhang, Swati Chakraborty, D. Walker
Memory arrays cannot be as easily tested as other storage elements. They can be considered as non-scan cells. Memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these techniques have relatively poor coverage of the timing critical paths. We propose path delay test through memory arrays using pseudo functional test with K Longest Paths Per Gate (PKLPG). Long paths captured into a non-scan cell (including a memory cell) are propagated to a scan cell, and non-scan cells are initialized so that they can launch transitions onto long paths.
{"title":"Delay Test of Embedded Memories","authors":"Yukun Gao, Tengteng Zhang, Swati Chakraborty, D. Walker","doi":"10.1109/NATW.2014.22","DOIUrl":"https://doi.org/10.1109/NATW.2014.22","url":null,"abstract":"Memory arrays cannot be as easily tested as other storage elements. They can be considered as non-scan cells. Memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these techniques have relatively poor coverage of the timing critical paths. We propose path delay test through memory arrays using pseudo functional test with K Longest Paths Per Gate (PKLPG). Long paths captured into a non-scan cell (including a memory cell) are propagated to a scan cell, and non-scan cells are initialized so that they can launch transitions onto long paths.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133749702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Cell-aware faults have previously been proposed to more effectively detect defects within gates. At the same time, n-detect test sets that provide multiple detections of each stuck-at fault are often used to maximize the detection of unmodeled defects. However, n-detect test sets are often not particularly effective at fortuitously detecting all untargeted cell-aware faults. In this paper, we investigate the effectiveness of different types of n-detect ATPG test sets for efficiently detecting difficult cell-aware-type faults and explain why optimizing test sets for n- detect using stuck-at faults while still keeping pattern counts low can actually bias those test sets against the detection of some cell-aware type faults. We then investigate the addition of cell-aware top-off patterns for cell-aware-type faults that are shown to be functionally relevant through good state simulation, allowing such faults to be prioritized when testing resources are limited.
{"title":"When Optimized N-Detect Test Sets are Biased: An Investigation of Cell-Aware-Type Faults and N-Detect Stuck-At ATPG","authors":"Fanchen Zhang, Micah Thornton, Jennifer Dworak","doi":"10.1109/NATW.2014.15","DOIUrl":"https://doi.org/10.1109/NATW.2014.15","url":null,"abstract":"Cell-aware faults have previously been proposed to more effectively detect defects within gates. At the same time, n-detect test sets that provide multiple detections of each stuck-at fault are often used to maximize the detection of unmodeled defects. However, n-detect test sets are often not particularly effective at fortuitously detecting all untargeted cell-aware faults. In this paper, we investigate the effectiveness of different types of n-detect ATPG test sets for efficiently detecting difficult cell-aware-type faults and explain why optimizing test sets for n- detect using stuck-at faults while still keeping pattern counts low can actually bias those test sets against the detection of some cell-aware type faults. We then investigate the addition of cell-aware top-off patterns for cell-aware-type faults that are shown to be functionally relevant through good state simulation, allowing such faults to be prioritized when testing resources are limited.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115953426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, M. Tehranipoor
With the high costs associated with modern IC fabrication, most semiconductor companies have gone fabless, i.e., they outsource manufacturing of their designs to contract foundries. This horizontal business model has led to many well documented issues associated with untrusted foundries including IC overproduction and shipping improperly or insufficiently tested chips. Entering such chips in the supply chain can be catastrophic for critical applications. We propose a new Secure Split-Test to give control over testing back to the IP owner. Each chip is locked during test. The IP owner is the only entity who can interpret the locked test results and unlock passing chips. In this way, SST can prevent shipping overproduction and defective chips from reaching the supply chain. The proposed method considerably simplifies the communication required between the foundry and IP owner compared to the original version of the secure split test. The results demonstrate that our new technique is more secure than the original and with less communication barriers.
{"title":"CSST: An Efficient Secure Split-Test for Preventing IC Piracy","authors":"Md. Tauhidur Rahman, Domenic Forte, Quihang Shi, Gustavo K. Contreras, M. Tehranipoor","doi":"10.1109/NATW.2014.17","DOIUrl":"https://doi.org/10.1109/NATW.2014.17","url":null,"abstract":"With the high costs associated with modern IC fabrication, most semiconductor companies have gone fabless, i.e., they outsource manufacturing of their designs to contract foundries. This horizontal business model has led to many well documented issues associated with untrusted foundries including IC overproduction and shipping improperly or insufficiently tested chips. Entering such chips in the supply chain can be catastrophic for critical applications. We propose a new Secure Split-Test to give control over testing back to the IP owner. Each chip is locked during test. The IP owner is the only entity who can interpret the locked test results and unlock passing chips. In this way, SST can prevent shipping overproduction and defective chips from reaching the supply chain. The proposed method considerably simplifies the communication required between the foundry and IP owner compared to the original version of the secure split test. The results demonstrate that our new technique is more secure than the original and with less communication barriers.","PeriodicalId":283155,"journal":{"name":"2014 IEEE 23rd North Atlantic Test Workshop","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131008871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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