Pub Date : 2016-09-29DOI: 10.1109/ISPCS.2016.7579515
Felipe Torres-González, Javier Díaz, Emilio Marin-Lopez, R. Rodríguez-Gómez
Due to an increase of timing requirements in many actual and future applications, improvements are needed in current synchronization protocols. New scenarios as the Internet of Things or the next generation of 5G Mobile telecommunication networks, where a large number of devices must be interconnected, will stand in need of a better synchronization accuracy and a highly scalable protocol. White Rabbit (WR) is a multi-collaborative open project aiming at the distribution of timing with sub-nanosecond accuracy to thousand of nodes connected within an Ethernet network. It is built as an extension of the Precision Time Protocol (PTP). In order to improve the PTP's accuracy, WR incorporates some enhancements such as a precise link delay model, fine delay phase measurement and clock syntonization over the physical layer. In this paper we focus on the scalability analysis of the WR solution with networks of more than 15 hops connected in a daisy-chain configuration, using the WR Light Embedded Node (WR-LEN) which includes the White Rabbit PTP Core Dual Port. The study evaluates the scalability of the WR extensions to PTPv2 for the achievement of ultra-accurate time transfer in networks with linear topology. The contribution results are relevant for applications where the scalability of the timing solution is a fundamental ingredient for addressing novel applications and markets.
{"title":"Scalability analysis of the white-rabbit technology for cascade-chain networks","authors":"Felipe Torres-González, Javier Díaz, Emilio Marin-Lopez, R. Rodríguez-Gómez","doi":"10.1109/ISPCS.2016.7579515","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579515","url":null,"abstract":"Due to an increase of timing requirements in many actual and future applications, improvements are needed in current synchronization protocols. New scenarios as the Internet of Things or the next generation of 5G Mobile telecommunication networks, where a large number of devices must be interconnected, will stand in need of a better synchronization accuracy and a highly scalable protocol. White Rabbit (WR) is a multi-collaborative open project aiming at the distribution of timing with sub-nanosecond accuracy to thousand of nodes connected within an Ethernet network. It is built as an extension of the Precision Time Protocol (PTP). In order to improve the PTP's accuracy, WR incorporates some enhancements such as a precise link delay model, fine delay phase measurement and clock syntonization over the physical layer. In this paper we focus on the scalability analysis of the WR solution with networks of more than 15 hops connected in a daisy-chain configuration, using the WR Light Embedded Node (WR-LEN) which includes the White Rabbit PTP Core Dual Port. The study evaluates the scalability of the WR extensions to PTPv2 for the achievement of ultra-accurate time transfer in networks with linear topology. The contribution results are relevant for applications where the scalability of the timing solution is a fundamental ingredient for addressing novel applications and markets.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128590303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-29DOI: 10.1109/ISPCS.2016.7579514
M. Rizzi, M. Lipinski, T. Wlostowski, J. Serrano, G. Daniluk, P. Ferrari, S. Rinaldi
White Rabbit (WR) extends the Precision Time Protocol (PTP) to provide synchronisation with sub-nanosecond accuracy and sub-50 picoseconds precision. The protocol aspects of the WR extension are currently studied and integrated into the upcoming revision of PTP. In the context of this PTP revision, mechanisms are added to allow the control of the Layer 1 (L1) syntonisation by the PTP protocol. This article focuses on the frequency transfer characteristics of the L1 syntonisation in WR. We first explain the interaction between L1 syntonisation and PTP synchronisation in a WR device and describe the architecture of its Phase-Locked Loop (PLL). We then characterize the frequency transfer through a WR network in two ways: measuring the characteristics of the WR switch according to the Synchronous Ethernet (SyncE) metrics defined in ITU-T G.8262, and performing phase noise analysis. The results of the measurements allow us to propose improvements that might be useful for different types of WR applications. Metrology laboratories might be interested in the optimisations made to significantly reduce the phase noise. On the other hand, the telecom industry might be interested in the modifications that make the WR switch SyncE-compliant but deteriorate its performance. Notably, the latter was achieved merely by modifying the software that implements the WR PLL.
{"title":"White rabbit clock characteristics","authors":"M. Rizzi, M. Lipinski, T. Wlostowski, J. Serrano, G. Daniluk, P. Ferrari, S. Rinaldi","doi":"10.1109/ISPCS.2016.7579514","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579514","url":null,"abstract":"White Rabbit (WR) extends the Precision Time Protocol (PTP) to provide synchronisation with sub-nanosecond accuracy and sub-50 picoseconds precision. The protocol aspects of the WR extension are currently studied and integrated into the upcoming revision of PTP. In the context of this PTP revision, mechanisms are added to allow the control of the Layer 1 (L1) syntonisation by the PTP protocol. This article focuses on the frequency transfer characteristics of the L1 syntonisation in WR. We first explain the interaction between L1 syntonisation and PTP synchronisation in a WR device and describe the architecture of its Phase-Locked Loop (PLL). We then characterize the frequency transfer through a WR network in two ways: measuring the characteristics of the WR switch according to the Synchronous Ethernet (SyncE) metrics defined in ITU-T G.8262, and performing phase noise analysis. The results of the measurements allow us to propose improvements that might be useful for different types of WR applications. Metrology laboratories might be interested in the optimisations made to significantly reduce the phase noise. On the other hand, the telecom industry might be interested in the modifications that make the WR switch SyncE-compliant but deteriorate its performance. Notably, the latter was achieved merely by modifying the software that implements the WR PLL.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122077221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579517
Chandra Mallela, Yu Ying Choo, Vince Bridgers
The Intel-PSG division focused on FPGAs, has always delivered the hardware Intellectual Property (IP) cores that include both soft cores (synthesizable code) and hard cores (already routed and supplied with the FPGA), that can integrate well with firmware and application software in a system. The 1588 Precision Timing Protocol (1588-PTP) solution spans both software and hardware and the accuracy reported at a system level has more credibility than the accuracy reported at the hardware level. Hence, the Intel-PSG has chosen the route of open-source stack available with the Linux and built its 1588 RD (Reference Design) solution comprising its already established 1588 hardware IP. The system solution has achieved an accuracy of around 7ns in an Ordinary Clock system comprising one master clock and one slave clock. This article details the objectives of the 1588 RD solution, the technical process of achieving the objectives and key learnings in the whole exercise. Specifically, the article focuses on the key system level decisions viz., (a) choosing FIFO/DMA/TCAM (b) Timestamping all the packets vs timestamping only the PTP packets. The article further details the software and hardware architecture and their internal design details, the PTP packet flow and the procedure of arriving at the system level accuracy. Key learnings and scope for future work conclude the article.
{"title":"Building a 1588 system solution — Key learnings","authors":"Chandra Mallela, Yu Ying Choo, Vince Bridgers","doi":"10.1109/ISPCS.2016.7579517","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579517","url":null,"abstract":"The Intel-PSG division focused on FPGAs, has always delivered the hardware Intellectual Property (IP) cores that include both soft cores (synthesizable code) and hard cores (already routed and supplied with the FPGA), that can integrate well with firmware and application software in a system. The 1588 Precision Timing Protocol (1588-PTP) solution spans both software and hardware and the accuracy reported at a system level has more credibility than the accuracy reported at the hardware level. Hence, the Intel-PSG has chosen the route of open-source stack available with the Linux and built its 1588 RD (Reference Design) solution comprising its already established 1588 hardware IP. The system solution has achieved an accuracy of around 7ns in an Ordinary Clock system comprising one master clock and one slave clock. This article details the objectives of the 1588 RD solution, the technical process of achieving the objectives and key learnings in the whole exercise. Specifically, the article focuses on the key system level decisions viz., (a) choosing FIFO/DMA/TCAM (b) Timestamping all the packets vs timestamping only the PTP packets. The article further details the software and hardware architecture and their internal design details, the PTP packet flow and the procedure of arriving at the system level accuracy. Key learnings and scope for future work conclude the article.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"133 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133138058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579516
Wolfgang Wallner, Armin Wasicek, R. Grosu
IEEE 1588 specifies the Precision Time Protocol (PTP). The design space for PTP implementations is large, and system designers have to make trade-offs. A sophisticated and extensible simulation tool can assist PTP system designers when exploring the design space. This paper serves as an introduction to LibPTP, which is an OMNeT++-based simulation framework for PTP networks. LibPTP facilitates building PTP networks using Ordinary, Boundary, and Transparent clocks. For instance, it enables designers to study different configuration options, to compare delay mechanisms, or switch between clock servos. The paper gives an overview of the current feature set of LibPTP, and demonstrates LibPTP's capabilities through exemplary experiments. The demonstrations encompass analyzing the choice of synchronization intervals, the impact of path asymmetry, and daisy chaining of clocks.
IEEE 1588规定了PTP (Precision Time Protocol)协议。PTP实现的设计空间很大，系统设计师必须做出权衡。一个复杂且可扩展的仿真工具可以帮助PTP系统设计人员探索设计空间。LibPTP是一个基于omnet++的PTP网络仿真框架。LibPTP有助于使用普通、边界和透明时钟构建PTP网络。例如，它使设计人员能够研究不同的配置选项，比较延迟机制，或在时钟伺服器之间切换。本文概述了LibPTP的当前特性集，并通过示例实验演示了LibPTP的功能。演示包括分析同步间隔的选择、路径不对称的影响以及时钟的菊花链。
{"title":"A simulation framework for IEEE 1588","authors":"Wolfgang Wallner, Armin Wasicek, R. Grosu","doi":"10.1109/ISPCS.2016.7579516","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579516","url":null,"abstract":"IEEE 1588 specifies the Precision Time Protocol (PTP). The design space for PTP implementations is large, and system designers have to make trade-offs. A sophisticated and extensible simulation tool can assist PTP system designers when exploring the design space. This paper serves as an introduction to LibPTP, which is an OMNeT++-based simulation framework for PTP networks. LibPTP facilitates building PTP networks using Ordinary, Boundary, and Transparent clocks. For instance, it enables designers to study different configuration options, to compare delay mechanisms, or switch between clock servos. The paper gives an overview of the current feature set of LibPTP, and demonstrates LibPTP's capabilities through exemplary experiments. The demonstrations encompass analyzing the choice of synchronization intervals, the impact of path asymmetry, and daisy chaining of clocks.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128408885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579507
A. Puhm, A. Mahmood, Thomas Bigler, N. Kero
It is expected that there is only a single active path between an IEEE 1588 master and slave. This is based on the general operation scenario of an Ethernet network, which depends on a setup without network loops. In a redundant Ethernet system based on the Parallel Redundancy Protocol (PRP) or the High availability Seamless Redundancy protocol (HSR), this expectation is skewed. There are two simultaneously active paths between an IEEE 1588 master and slave clock in these systems. Selecting the better path for synchronization, by applying additional qualification criteria in the best master clock algorithm, e.g., the correction field, is a common solution for this problem. This paper proposes a solution to use both paths simultaneously for synchronization to provide a seamless switchover, if one path fails.
{"title":"Synchronizing an IEEE 1588 slave clock over both paths of a redundant Ethernet system","authors":"A. Puhm, A. Mahmood, Thomas Bigler, N. Kero","doi":"10.1109/ISPCS.2016.7579507","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579507","url":null,"abstract":"It is expected that there is only a single active path between an IEEE 1588 master and slave. This is based on the general operation scenario of an Ethernet network, which depends on a setup without network loops. In a redundant Ethernet system based on the Parallel Redundancy Protocol (PRP) or the High availability Seamless Redundancy protocol (HSR), this expectation is skewed. There are two simultaneously active paths between an IEEE 1588 master and slave clock in these systems. Selecting the better path for synchronization, by applying additional qualification criteria in the best master clock algorithm, e.g., the correction field, is a common solution for this problem. This paper proposes a solution to use both paths simultaneously for synchronization to provide a seamless switchover, if one path fails.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125694468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579502
K. O'Donoghue
Security has historically not been a top consideration for the developers of time synchronization protocols. However, in recent years rising awareness of the overall importance of security in general along with increasing examples of targeted vulnerability analysis and incidents exploiting the underlying weaknesses of existing solutions has increased the demand for standards based security mechanisms for network time synchronization protocols. This paper provides an overview of the general approach and discusses some key components being standardized as part of both the IEEE 1588 Precision Time Protocol (PTP) and the IETF Network Time Security (NTS) efforts. It also discusses the underlying motivation and requirements driving these efforts and identifies some next steps and possible avenues of further investigation.
{"title":"Emerging solutions for time protocol security","authors":"K. O'Donoghue","doi":"10.1109/ISPCS.2016.7579502","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579502","url":null,"abstract":"Security has historically not been a top consideration for the developers of time synchronization protocols. However, in recent years rising awareness of the overall importance of security in general along with increasing examples of targeted vulnerability analysis and incidents exploiting the underlying weaknesses of existing solutions has increased the demand for standards based security mechanisms for network time synchronization protocols. This paper provides an overview of the general approach and discusses some key components being standardized as part of both the IEEE 1588 Precision Time Protocol (PTP) and the IETF Network Time Security (NTS) efforts. It also discusses the underlying motivation and requirements driving these efforts and identifies some next steps and possible avenues of further investigation.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126717351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579499
S. Rinaldi, P. Ferrari, Matteo Loda
The growth of Smart Grids based on the IEC61850 standard makes the communication infrastructure a key factor of a successful application. Due to the distributed nature of the Smart Grid, the evaluation of the main performance indicators requires specialized distributed measurement system with dozens of measuring probes. Clearly, the scalability of the measurement system is tied to the cost of the single probe, and a tradeoff between cost and accuracy is needed. In this paper, the possibility of using low-cost probes for the estimation of the IEC61850 Transfer Time over Smart Grid communication infrastructure is investigated. The key feature to enable distributed measurement is the accuracy of the time synchronization that the probe (based on of-the-shelf microcomputer) can achieve. The paper presents an experimental evaluation of the measuring performance using some probe prototypes attached to an IEE1588 compliant infrastructure: the synchronization extended uncertainty is below 3 μs, and the IEC61850 Transfer Time measurement has an extended uncertainty below 15 μs.
{"title":"Synchronizing low-cost probes for IEC61850 transfer time estimation","authors":"S. Rinaldi, P. Ferrari, Matteo Loda","doi":"10.1109/ISPCS.2016.7579499","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579499","url":null,"abstract":"The growth of Smart Grids based on the IEC61850 standard makes the communication infrastructure a key factor of a successful application. Due to the distributed nature of the Smart Grid, the evaluation of the main performance indicators requires specialized distributed measurement system with dozens of measuring probes. Clearly, the scalability of the measurement system is tied to the cost of the single probe, and a tradeoff between cost and accuracy is needed. In this paper, the possibility of using low-cost probes for the estimation of the IEC61850 Transfer Time over Smart Grid communication infrastructure is investigated. The key feature to enable distributed measurement is the accuracy of the time synchronization that the probe (based on of-the-shelf microcomputer) can achieve. The paper presents an experimental evaluation of the measuring performance using some probe prototypes attached to an IEE1588 compliant infrastructure: the synchronization extended uncertainty is below 3 μs, and the IEC61850 Transfer Time measurement has an extended uncertainty below 15 μs.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121166371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579504
P. Iovanna, Stefano Ruffini, Mats Forsman, Tomas Thyni
Network synchronization is expected to be one of the key aspects in 5G. This article presents an application of the SDN (Software Defined Networking) and NFV (Network Function Virtualization) principles to the area of the network synchronization, enabling to offer synchronization as a service. The approach is based on defining a harmonization layer that allows orchestrating radio and heterogeneous transport domains.
{"title":"SDN-based architecture to support Synchronization in a 5G framework","authors":"P. Iovanna, Stefano Ruffini, Mats Forsman, Tomas Thyni","doi":"10.1109/ISPCS.2016.7579504","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579504","url":null,"abstract":"Network synchronization is expected to be one of the key aspects in 5G. This article presents an application of the SDN (Software Defined Networking) and NFV (Network Function Virtualization) principles to the area of the network synchronization, enabling to offer synchronization as a service. The approach is based on defining a harmonization layer that allows orchestrating radio and heterogeneous transport domains.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124107500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579509
Elena Lisova, E. Uhlemann, W. Steiner, J. Åkerberg, M. Bjorkman
Industrial applications usually have real-time requirements or high precision timing demands. For such applications, clock synchronization is one of the main assets that needs to be protected against malicious attacks. To provide sufficient accuracy for distributed time-critical applications, appropriate techniques for preventing or mitigating delay attacks that breach clock synchronization are needed. In this paper, we apply game theory to investigate possible strategies of an adversary, performing attacks targeting clock synchronization on the one hand and a network monitor, aiming to detect anomalies introduced by the adversary on the other. We investigate the interconnection of payoffs for both sides and propose the quarantine mode as a mitigation technique. Delay attacks with constant, linearly increasing, and randomly introduced delays are considered, and we show how the adversary strategy can be estimated by evaluating the detection coefficient, giving the network monitor the possibility to deploy appropriate protection techniques.
{"title":"Game theory applied to secure clock synchronization with IEEE 1588","authors":"Elena Lisova, E. Uhlemann, W. Steiner, J. Åkerberg, M. Bjorkman","doi":"10.1109/ISPCS.2016.7579509","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579509","url":null,"abstract":"Industrial applications usually have real-time requirements or high precision timing demands. For such applications, clock synchronization is one of the main assets that needs to be protected against malicious attacks. To provide sufficient accuracy for distributed time-critical applications, appropriate techniques for preventing or mitigating delay attacks that breach clock synchronization are needed. In this paper, we apply game theory to investigate possible strategies of an adversary, performing attacks targeting clock synchronization on the one hand and a network monitor, aiming to detect anomalies introduced by the adversary on the other. We investigate the interconnection of payoffs for both sides and propose the quarantine mode as a mitigation technique. Delay attacks with constant, linearly increasing, and randomly introduced delays are considered, and we show how the adversary strategy can be estimated by evaluating the detection coefficient, giving the network monitor the possibility to deploy appropriate protection techniques.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133788106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-09-01DOI: 10.1109/ISPCS.2016.7579518
I. Shkliarevskyi, Oleksandr Shkliarevskyi, Evgeniy Dyadenko, Youry Vountesmery
IEEE 1588-2008 protocol, or Precision Time Protocol (PTP) has found it's implementation in different applications for time and frequency distribution through both local and IP-networks. PTP profiles standardized by different international organizations just for adopting PTP to a field existing network are analyzed and compared each other to see a trend of their mutual compatibility providing. Conclusions have made that the PTP profiles divergence tendency still presents now in the Time and Frequency (T&F) world.
{"title":"IEEE 1588 protocol profiles' comparative analysis according to different applications and standards","authors":"I. Shkliarevskyi, Oleksandr Shkliarevskyi, Evgeniy Dyadenko, Youry Vountesmery","doi":"10.1109/ISPCS.2016.7579518","DOIUrl":"https://doi.org/10.1109/ISPCS.2016.7579518","url":null,"abstract":"IEEE 1588-2008 protocol, or Precision Time Protocol (PTP) has found it's implementation in different applications for time and frequency distribution through both local and IP-networks. PTP profiles standardized by different international organizations just for adopting PTP to a field existing network are analyzed and compared each other to see a trend of their mutual compatibility providing. Conclusions have made that the PTP profiles divergence tendency still presents now in the Time and Frequency (T&F) world.","PeriodicalId":284489,"journal":{"name":"2016 IEEE International Symposium on Precision Clock Synchronization for Measurement, Control, and Communication (ISPCS)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114781145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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