Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509389
D. Schweitzer, H. Pape, Liu Chen
The accurate and reproducible measurement of the junction-to-case thermal resistance Rth-JC of power semiconductor devices is far from trivial. In the recent time several new approaches to measure the Rth-JC have been suggested, among them transient measurements with different interface materials between the package and a heat-sink which allow identifying the Rth-IC in the structure function of the heat flow path. This paper shows that numerical effects during the calculation of the structure function as well as 3D heat spreading have a big influence on the structure function which makes it often difficult to determine the Rth-IC. Finite element simulations can provide a clue to identify this value in the structure function. The theoretical findings are applied to and demonstrated for actual measurements and the new approach is compared to the traditional method (involving a thermo-couple measurement of the case temperature) with respect to accuracy and reproducibility. Finally an alternative approach to determining the Rth-IC from transient dual- interface measurements, which is not based on structure functions, is presented.
{"title":"Transient Measurement of the Junction-To-Case Thermal Resistance Using Structure Functions: Chances and Limits","authors":"D. Schweitzer, H. Pape, Liu Chen","doi":"10.1109/STHERM.2008.4509389","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509389","url":null,"abstract":"The accurate and reproducible measurement of the junction-to-case thermal resistance Rth-JC of power semiconductor devices is far from trivial. In the recent time several new approaches to measure the Rth-JC have been suggested, among them transient measurements with different interface materials between the package and a heat-sink which allow identifying the Rth-IC in the structure function of the heat flow path. This paper shows that numerical effects during the calculation of the structure function as well as 3D heat spreading have a big influence on the structure function which makes it often difficult to determine the Rth-IC. Finite element simulations can provide a clue to identify this value in the structure function. The theoretical findings are applied to and demonstrated for actual measurements and the new approach is compared to the traditional method (involving a thermo-couple measurement of the case temperature) with respect to accuracy and reproducibility. Finally an alternative approach to determining the Rth-IC from transient dual- interface measurements, which is not based on structure functions, is presented.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129832251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509363
J. Tyacke, P. Tucker, P. Nithiarasu
Hybrid methods based on the Reynolds Averaged Navier Stokes (RANS) equations and the Large Eddy Simulation (LES) formulation are investigated to try and improve the accuracy of heat transfer and surface temperature predictions for electronics systems and components. Two relatively low Reynolds number flows are studied using hybrid RANS-LES, RANS-Implicit-LES (RANS-ILES) and non-linear LES models. Predictions using these methods are in good agreement with each other, even using different grid resolutions.
{"title":"Strategies for Modeling Turbulent Flows in Electronics","authors":"J. Tyacke, P. Tucker, P. Nithiarasu","doi":"10.1109/STHERM.2008.4509363","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509363","url":null,"abstract":"Hybrid methods based on the Reynolds Averaged Navier Stokes (RANS) equations and the Large Eddy Simulation (LES) formulation are investigated to try and improve the accuracy of heat transfer and surface temperature predictions for electronics systems and components. Two relatively low Reynolds number flows are studied using hybrid RANS-LES, RANS-Implicit-LES (RANS-ILES) and non-linear LES models. Predictions using these methods are in good agreement with each other, even using different grid resolutions.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114193610","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509361
C. Lasance, R. Aarts, Okke Ouweltjes
The paper discusses experimental results for a typical embodiment of synthetic jet cooling technology: an acoustic dipole cooler comprised of a standard loudspeaker in a housing provided with two pipes. A transient measurement set up is used to measure the average heat transfer coefficient based on cooling a 5*5 cm2 metal plate. Heat transfer and noise results are presented for a range of frequencies, pipe lengths and diameters. The results are compared with a standard 60*60 mm fan. It is concluded that, at least for the cases studied, the synthetic jet is superior on all fronts: heat transfer performance, noise level and dissipated power.
{"title":"Synthetic Jet Cooling Part II: Experimental Results of an Acoustic Dipole Cooler","authors":"C. Lasance, R. Aarts, Okke Ouweltjes","doi":"10.1109/STHERM.2008.4509361","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509361","url":null,"abstract":"The paper discusses experimental results for a typical embodiment of synthetic jet cooling technology: an acoustic dipole cooler comprised of a standard loudspeaker in a housing provided with two pipes. A transient measurement set up is used to measure the average heat transfer coefficient based on cooling a 5*5 cm2 metal plate. Heat transfer and noise results are presented for a range of frequencies, pipe lengths and diameters. The results are compared with a standard 60*60 mm fan. It is concluded that, at least for the cases studied, the synthetic jet is superior on all fronts: heat transfer performance, noise level and dissipated power.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129756570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509379
Y. Shabany
The exact analytical correlations to calculate radiation heat transfer rate from a diffuse and gray plate-fin heat sink are presented. These correlations involve a view factor that can be exactly calculated using a rather complex set of equations. A very simple approximate correlation for this view factor is proposed that results in radiation heat transfer rates that are accurate with a maximum error of about 11%.
{"title":"Radiation Heat Transfer from Plate-Fin Heat Sinks","authors":"Y. Shabany","doi":"10.1109/STHERM.2008.4509379","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509379","url":null,"abstract":"The exact analytical correlations to calculate radiation heat transfer rate from a diffuse and gray plate-fin heat sink are presented. These correlations involve a view factor that can be exactly calculated using a rather complex set of equations. A very simple approximate correlation for this view factor is proposed that results in radiation heat transfer rates that are accurate with a maximum error of about 11%.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122245943","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509375
G. Martin, E. Eggink
Thermal issues and problems of a product are emerging very early in the Product Creation Process (PCP). Innovation, Time to market and Cost are three important drivers of the consumer electronics market. While costs of changes exponentially increase during the product development cycle, the freedom to implement changes substantially diminishes. It is therefore important to identify very early in the PCP the thermal risks and associate to them possible cooling technologies or strategies. A Thermal Technology Roadmap (TTR) can lead to better strategic choices; it is a decision tool for long term investments in pre-development, it enables getting a common long term vision within the organization and it enables synergy between research centers and product development teams. This publication describes a methodology developed to create a Thermal Technology Roadmap (TTR) associating a product roadmap to emerging technologies. The resulting TTR identifies the most promising cooling technologies for the product range on short, middle and long terms according to defined criteria.
{"title":"Creation of a Thermal Technology Roadmap in a Consumer Electronics Product Environment","authors":"G. Martin, E. Eggink","doi":"10.1109/STHERM.2008.4509375","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509375","url":null,"abstract":"Thermal issues and problems of a product are emerging very early in the Product Creation Process (PCP). Innovation, Time to market and Cost are three important drivers of the consumer electronics market. While costs of changes exponentially increase during the product development cycle, the freedom to implement changes substantially diminishes. It is therefore important to identify very early in the PCP the thermal risks and associate to them possible cooling technologies or strategies. A Thermal Technology Roadmap (TTR) can lead to better strategic choices; it is a decision tool for long term investments in pre-development, it enables getting a common long term vision within the organization and it enables synergy between research centers and product development teams. This publication describes a methodology developed to create a Thermal Technology Roadmap (TTR) associating a product roadmap to emerging technologies. The resulting TTR identifies the most promising cooling technologies for the product range on short, middle and long terms according to defined criteria.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114280894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509382
R. Bonner, R. Wadell, G. Popov
Impingement cooling methods, such as spray cooling and jet impingement have demonstrated the capability of cooling high heat flux surfaces while maintaining a low thermal resistance. Most spray cooling and jet impingement experiments attempt to measure the average heat transfer coefficient, even though it is known that heat transfer coefficients are known to change as a function of distance from the impact zone. Secondly, most experiments are done on thick uniformly heated surfaces although most electronic devices are very thin (<0.2 mm) and generate heat very non- uniformly with very large peak heat fluxes (>1000 W/cm2) over very small areas (<0.25 mm2). In this study an accurate measurement of the uniformity of the spray cooling thermal solution was attained using an Intel supplied thermal test vehicle. The heater block is a thin silicon chip (<0.25 mm thick and 7 cm2 in surface area) delivering a uniform heat flux to 70 W/cm2. The platform also has the ability to power large peak heat fluxes (>1000 W/cm2) over small areas (<0.2 5 mm2). Experiments using jet impingement with flat spray nozzles angled to the surface were conducted with water, methanol, and HFE-7000. The axial heat transfer coefficient variation was measured under uniform heat loading. Finally, the measurements are compared to modified models from the literature with good agreement.
{"title":"Local Heat Transfer Coefficient Measurements of Flat Angled Sprays Using Thermal Test Vehicle","authors":"R. Bonner, R. Wadell, G. Popov","doi":"10.1109/STHERM.2008.4509382","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509382","url":null,"abstract":"Impingement cooling methods, such as spray cooling and jet impingement have demonstrated the capability of cooling high heat flux surfaces while maintaining a low thermal resistance. Most spray cooling and jet impingement experiments attempt to measure the average heat transfer coefficient, even though it is known that heat transfer coefficients are known to change as a function of distance from the impact zone. Secondly, most experiments are done on thick uniformly heated surfaces although most electronic devices are very thin (<0.2 mm) and generate heat very non- uniformly with very large peak heat fluxes (>1000 W/cm2) over very small areas (<0.25 mm2). In this study an accurate measurement of the uniformity of the spray cooling thermal solution was attained using an Intel supplied thermal test vehicle. The heater block is a thin silicon chip (<0.25 mm thick and 7 cm2 in surface area) delivering a uniform heat flux to 70 W/cm2. The platform also has the ability to power large peak heat fluxes (>1000 W/cm2) over small areas (<0.2 5 mm2). Experiments using jet impingement with flat spray nozzles angled to the surface were conducted with water, methanol, and HFE-7000. The axial heat transfer coefficient variation was measured under uniform heat loading. Finally, the measurements are compared to modified models from the literature with good agreement.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115487292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509365
Je-Hyoung Park, Xi Wang, A. Shakouri, S. Kang
The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI industry limiting both the performance and the reliability of packaged chips. Thus the surface temperature profile of VLSI ICs has become critical information in chip design flow. for fast computation of surface temperature profile, power blurring (PB) method has been developed. This method can be applied to simulations with high spatial resolution, which have been prohibitively expensive with conventional methods. Comparative case studies with different levels of resolution illustrate that not only localized small hot spots can be overlooked but even the average chip temperature can be underestimated, and hence the necessity of thermal simulation with high spatial resolution. Using our PB method, we obtained transistor level thermal map (5times5 mum2 grid) of a 5times5 mm2 chip with a computation time of 20 seconds.
{"title":"Fast Computation of Temperature Profiles of VLSI ICs with High Spatial Resolution","authors":"Je-Hyoung Park, Xi Wang, A. Shakouri, S. Kang","doi":"10.1109/STHERM.2008.4509365","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509365","url":null,"abstract":"The reality of high temperature non-uniformity has become a serious concern in the CMOS VLSI industry limiting both the performance and the reliability of packaged chips. Thus the surface temperature profile of VLSI ICs has become critical information in chip design flow. for fast computation of surface temperature profile, power blurring (PB) method has been developed. This method can be applied to simulations with high spatial resolution, which have been prohibitively expensive with conventional methods. Comparative case studies with different levels of resolution illustrate that not only localized small hot spots can be overlooked but even the average chip temperature can be underestimated, and hence the necessity of thermal simulation with high spatial resolution. Using our PB method, we obtained transistor level thermal map (5times5 mum2 grid) of a 5times5 mm2 chip with a computation time of 20 seconds.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127997215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509371
T. Karila, P. Palm
In traditional approach of electronics manufacturing, active and passive components are mounted on printed circuit board (PCB) utilizing surface mount technology (SMT). Due to the continuous miniaturization of electronic products, new innovative packaging technologies have been developed to meet future requirements. Integrated module board (1MB) technology offers solution for embedding active and passive components inside an organic substrate or PCB mother board. Development through three technology generations has enabled cost-effective manufacturing without drawbacks in terms of reliability, yield and system performance. The requirement of decreased product size along with constantly increasing power densities poses an issue of overheating. As embedded ICs are in question, the thermal management of the packages is typically even more challenging: gained benefit in size and weight produces fewer options for thermal management methods. However, despite of lost volume, 1MB technology also offers some degrees of freedom to manage the thermal load produced by ICs. This paper presents the summary of results about the initial thermal studies of the 1MB technology that is also presented in general terms. System-in-board (SiB) and system-in-package (SiP) types of packages have been manufactured and measured in standard natural convection environment and modeled with thermal simulation software. The results have provided fundamental information about the thermal behavior of the 1MB structure - e.g. main heat flow paths have been determined and the efficiency of various thermal enhancement methods has been evaluated.
{"title":"Thermal Characteristics of Integrated Module Board","authors":"T. Karila, P. Palm","doi":"10.1109/STHERM.2008.4509371","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509371","url":null,"abstract":"In traditional approach of electronics manufacturing, active and passive components are mounted on printed circuit board (PCB) utilizing surface mount technology (SMT). Due to the continuous miniaturization of electronic products, new innovative packaging technologies have been developed to meet future requirements. Integrated module board (1MB) technology offers solution for embedding active and passive components inside an organic substrate or PCB mother board. Development through three technology generations has enabled cost-effective manufacturing without drawbacks in terms of reliability, yield and system performance. The requirement of decreased product size along with constantly increasing power densities poses an issue of overheating. As embedded ICs are in question, the thermal management of the packages is typically even more challenging: gained benefit in size and weight produces fewer options for thermal management methods. However, despite of lost volume, 1MB technology also offers some degrees of freedom to manage the thermal load produced by ICs. This paper presents the summary of results about the initial thermal studies of the 1MB technology that is also presented in general terms. System-in-board (SiB) and system-in-package (SiP) types of packages have been manufactured and measured in standard natural convection environment and modeled with thermal simulation software. The results have provided fundamental information about the thermal behavior of the 1MB structure - e.g. main heat flow paths have been determined and the efficiency of various thermal enhancement methods has been evaluated.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133724866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509381
R. Walchli, R. Linderman, T. Brunschwiler, U. Kloter, H. Rothuizen, N. Bieri, D. Poulikakos, B. Michel
The radially oscillating flow hybrid cooling system, in the following referred to as RADIOS, provides a thin form factor cold plate with radial spreading of heat to a larger area. A small liquid volume (<10 ml) is hermetically sealed within the system and does not require external hose connections. Four membrane pumps running in a phase-delayed manner induce a constant-speed, oscillating direction fluid flow at the chip source that continuously shuttles heat to an extended periphery and returns cool liquid to the chip. In the peripheral branches, heat is transferred from the liquid to solid structures and finally dissipated to the air. A micro-scale copper mesh enables low-resistance heat transfer (solid-liquid and liquid- solid) in a thin form factor (< 2 mm). Narrow channels between the discrete heat exchanger areas optimize the spreading performance and reduce the fluid volume. Numerical modeling shows an effective conductivity of 20X and 50X over bulk copper for the spreader plates and the interconnecting tubes, respectively. The technology presented here promotes modular liquid cooling units for low-profile computing systems without incurring the risk of flooding associated with conventional liquid cooling circuits.
{"title":"Radially Oscillating Flow Hybrid Cooling System for Low Profile Electronics Applications","authors":"R. Walchli, R. Linderman, T. Brunschwiler, U. Kloter, H. Rothuizen, N. Bieri, D. Poulikakos, B. Michel","doi":"10.1109/STHERM.2008.4509381","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509381","url":null,"abstract":"The radially oscillating flow hybrid cooling system, in the following referred to as RADIOS, provides a thin form factor cold plate with radial spreading of heat to a larger area. A small liquid volume (<10 ml) is hermetically sealed within the system and does not require external hose connections. Four membrane pumps running in a phase-delayed manner induce a constant-speed, oscillating direction fluid flow at the chip source that continuously shuttles heat to an extended periphery and returns cool liquid to the chip. In the peripheral branches, heat is transferred from the liquid to solid structures and finally dissipated to the air. A micro-scale copper mesh enables low-resistance heat transfer (solid-liquid and liquid- solid) in a thin form factor (< 2 mm). Narrow channels between the discrete heat exchanger areas optimize the spreading performance and reduce the fluid volume. Numerical modeling shows an effective conductivity of 20X and 50X over bulk copper for the spreader plates and the interconnecting tubes, respectively. The technology presented here promotes modular liquid cooling units for low-profile computing systems without incurring the risk of flooding associated with conventional liquid cooling circuits.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129114191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-03-16DOI: 10.1109/STHERM.2008.4509367
B. Siegal, J. Galloway
Increasing device complexity, greater power densities, ever changing packages, and shorter time-to-market deadlines have combined to make thermal characterization efforts more frenzied than ever. A thermal test chip was designed to assist the thermal engineer in answering critical thermal packaging or material questions. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scaleable array size. This allows a single wafer to supply various array sizes to meet changing requirements. The key requirements for a thermal test chip are: (1) Maximum possible heating area relative to chip size (2) Uniform temperature profile across heating area (3) Low temperature coefficient for heating source (4) Temperature sensor in center of chip (5) Simple-to-use temperature sensor(s) (6) Multiple temperature sensors for a temperature profile across chip surface (7) Kelvin Connections (i.e., 4-wire connections) for improved measurement accuracy (8) Chip size that closely approximates the chip being simulated. This paper will describe a thermal test chip that meets these requirements in the simplest manner possible. Insight into future investigations will also be presented.
{"title":"Thermal Test Chip Design and Performance Considerations","authors":"B. Siegal, J. Galloway","doi":"10.1109/STHERM.2008.4509367","DOIUrl":"https://doi.org/10.1109/STHERM.2008.4509367","url":null,"abstract":"Increasing device complexity, greater power densities, ever changing packages, and shorter time-to-market deadlines have combined to make thermal characterization efforts more frenzied than ever. A thermal test chip was designed to assist the thermal engineer in answering critical thermal packaging or material questions. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scaleable array size. This allows a single wafer to supply various array sizes to meet changing requirements. The key requirements for a thermal test chip are: (1) Maximum possible heating area relative to chip size (2) Uniform temperature profile across heating area (3) Low temperature coefficient for heating source (4) Temperature sensor in center of chip (5) Simple-to-use temperature sensor(s) (6) Multiple temperature sensors for a temperature profile across chip surface (7) Kelvin Connections (i.e., 4-wire connections) for improved measurement accuracy (8) Chip size that closely approximates the chip being simulated. This paper will describe a thermal test chip that meets these requirements in the simplest manner possible. Insight into future investigations will also be presented.","PeriodicalId":285718,"journal":{"name":"2008 Twenty-fourth Annual IEEE Semiconductor Thermal Measurement and Management Symposium","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114678385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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