Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511708
Y. Chiew, J. Liong, F. Tan
The continuing package miniaturized on semiconductor industry had driven toward smaller feature sizes and higher density which will raise the hurdle of dicing. This has become a trend to increase the number of potential die per wafer (PDPW) by shrinking the saw street width to have a competitive product cost and strategically maintain the product margin that affected by yearly Average Selling Price (ASP) erosion. Producing a wafer is a fixed cost thus the more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow saw street, which are the cut lines for singulating the die. The narrower saw street width, the more dies per wafer and the more challenging the dicing. Generally, the width of the saw streets has been reduced from former industry standard of 85um to 60um and now to latest 50um. The dicing challenges and quality issue become more crucial with the requirement of wafer backside coating (WBC), smaller die size, thinner wafer with passivation stacks on the saw street and existing of process control monitor (PCM) areas which contains the massive test structures. Key dicing quality characteristics focused in this paper are including top side chipping, passivation peeling and die side wall damage. This is most severe issue in dicing process and has induced the quality risk of customer return due to not easy or impossible to screen out at final test for those minor chipped/cracked die. Qualitative analysis will be carried out and high power microscope will be used to check for chipping condition or other defects. This paper reports the challenges faced and the successful development of 50um narrow saw street with conductive and nonconductive wafer backside coating on various thickness of wafers with six sigma process capability dicing performance and passed all the reliability stress test requirements. A comprehensive study was performed in optimizing critical dicing parameter such as blade height, suitable dicing blade and dicing tape.
{"title":"Mechanical Dicing Challenges and Development on 50um Saw Street with Wafer Backside Coating (WBC)","authors":"Y. Chiew, J. Liong, F. Tan","doi":"10.1109/IEMT.2018.8511708","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511708","url":null,"abstract":"The continuing package miniaturized on semiconductor industry had driven toward smaller feature sizes and higher density which will raise the hurdle of dicing. This has become a trend to increase the number of potential die per wafer (PDPW) by shrinking the saw street width to have a competitive product cost and strategically maintain the product margin that affected by yearly Average Selling Price (ASP) erosion. Producing a wafer is a fixed cost thus the more die per wafer equates to lower cost per die. Each die is separated from its neighbors by narrow saw street, which are the cut lines for singulating the die. The narrower saw street width, the more dies per wafer and the more challenging the dicing. Generally, the width of the saw streets has been reduced from former industry standard of 85um to 60um and now to latest 50um. The dicing challenges and quality issue become more crucial with the requirement of wafer backside coating (WBC), smaller die size, thinner wafer with passivation stacks on the saw street and existing of process control monitor (PCM) areas which contains the massive test structures. Key dicing quality characteristics focused in this paper are including top side chipping, passivation peeling and die side wall damage. This is most severe issue in dicing process and has induced the quality risk of customer return due to not easy or impossible to screen out at final test for those minor chipped/cracked die. Qualitative analysis will be carried out and high power microscope will be used to check for chipping condition or other defects. This paper reports the challenges faced and the successful development of 50um narrow saw street with conductive and nonconductive wafer backside coating on various thickness of wafers with six sigma process capability dicing performance and passed all the reliability stress test requirements. A comprehensive study was performed in optimizing critical dicing parameter such as blade height, suitable dicing blade and dicing tape.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116945009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511790
Sim Jui Oon, K. S. Tan, T. Tou, S. Yap, C. Lau, Y. T. Chin
The demand for lightweight and high functionality devices is always a driving force in development of smaller, lighter and compact electronics circuit. Printed circuit board (PCB) is the most important structure that provides interconnection and supports the components; hence its flatness is always the main concern in SMT manufacturing. In order to ensure product reliability, the monitoring of thermally induced warpage of PCB during high temperature reflow is essential. PCB deformation occurs when there is mismatch of coefficients of thermal expansion between the materials. Thermally induced warpage in PCB can be obtained from the Shadow Moiré measurement, which is a non-contact full-field optical method integrated with a high temperature oven. In this study, a single-sided, small PCB (105 mm X 100 mm X 1.5 mm) and a large, multi-layer PCB (300 mm X 180 mm X 1.6 mm) are measured and analyzed. To reduce the temperature difference between the top and bottom of the PCBs, a heating profile is designed with the use of multiple thermocouples at various positions on the PCB. In addition, finite element analysis is carried out to determine the z-axis deformation of the PCBs. The finite-element simulation is setup to mimic the heating profile in the experiment. The results of simulation are compared to the experimental measurement.
对轻量化和高功能器件的需求一直是推动更小、更轻、更紧凑电子电路发展的动力。印刷电路板(PCB)是提供互连和支持组件的最重要的结构;因此，其平面度一直是SMT制造的主要关注点。为了保证产品的可靠性，对PCB在高温回流过程中的热致翘曲进行监测是十分必要的。当材料之间的热膨胀系数不匹配时，PCB板就会发生变形。阴影莫尔测量是一种与高温烘箱相结合的非接触式全场光学测量方法，可以获得PCB中的热致翘曲。在本研究中，测量和分析了单面小型PCB (105 mm X 100 mm X 1.5 mm)和大型多层PCB (300 mm X 180 mm X 1.6 mm)。为了减少PCB顶部和底部之间的温差，在PCB上的不同位置使用多个热电偶设计了加热剖面。此外，还进行了有限元分析，确定了pcb板的z轴变形。建立了模拟实验中加热剖面的有限元模拟。仿真结果与实验测量结果进行了比较。
{"title":"Warpage Studies of Printed Circuit Boards with Shadow Moiré and Simulations","authors":"Sim Jui Oon, K. S. Tan, T. Tou, S. Yap, C. Lau, Y. T. Chin","doi":"10.1109/IEMT.2018.8511790","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511790","url":null,"abstract":"The demand for lightweight and high functionality devices is always a driving force in development of smaller, lighter and compact electronics circuit. Printed circuit board (PCB) is the most important structure that provides interconnection and supports the components; hence its flatness is always the main concern in SMT manufacturing. In order to ensure product reliability, the monitoring of thermally induced warpage of PCB during high temperature reflow is essential. PCB deformation occurs when there is mismatch of coefficients of thermal expansion between the materials. Thermally induced warpage in PCB can be obtained from the Shadow Moiré measurement, which is a non-contact full-field optical method integrated with a high temperature oven. In this study, a single-sided, small PCB (105 mm X 100 mm X 1.5 mm) and a large, multi-layer PCB (300 mm X 180 mm X 1.6 mm) are measured and analyzed. To reduce the temperature difference between the top and bottom of the PCBs, a heating profile is designed with the use of multiple thermocouples at various positions on the PCB. In addition, finite element analysis is carried out to determine the z-axis deformation of the PCBs. The finite-element simulation is setup to mimic the heating profile in the experiment. The results of simulation are compared to the experimental measurement.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132792519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511766
E. Corpuz
In wire bonding process, one of the key factors to have a good bonding quality is the cleanliness of the bonding surfaces whether it is bonding pad (Die) or lead (leadframe). Foreign particles, contaminations, discolorations on bonding surfaces are common causes of non-sticking of ball bond. Improving material handling procedures, cleanroom procedures, additional line processes, improvement in process controls, process parameter optimizations, etc. are some of the preventions and improvement actions being carried out by semiconductor companies to minimize or eliminate such bonding surface conditions. In this paper, improvement of Non-Sticking On Pad (NSOP) caused by impurities or contaminations formed after ArH2 plasma cleaning process will be shown. It is detected in the impacted bonding pad surface a thick layer of “O” underneath the “C” layer when undergo depth profiling using X-ray Photoelectron Spectroscopy (XPS) surface analysis. Wirebond 1st bond parameter have been optimized to break through these “O” layer which is believed to be a film of hydroxyl (-OH) where one hydrogen atom combined to one oxygen atom formed after the ArH2 plasma cleaning process. The wirebond parameter (pre-US power) used in this non-sticking on bond pad improvement is not new in the wirebond equipment available today in the market. But with its function, ball bonding was able to break through the thick “O” layer and good bonding is achieved.
{"title":"Improving Non-Stick on Bond Pad Using High Pre-US (Ultrasonic) Power in Hydroxyl Coated Material","authors":"E. Corpuz","doi":"10.1109/IEMT.2018.8511766","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511766","url":null,"abstract":"In wire bonding process, one of the key factors to have a good bonding quality is the cleanliness of the bonding surfaces whether it is bonding pad (Die) or lead (leadframe). Foreign particles, contaminations, discolorations on bonding surfaces are common causes of non-sticking of ball bond. Improving material handling procedures, cleanroom procedures, additional line processes, improvement in process controls, process parameter optimizations, etc. are some of the preventions and improvement actions being carried out by semiconductor companies to minimize or eliminate such bonding surface conditions. In this paper, improvement of Non-Sticking On Pad (NSOP) caused by impurities or contaminations formed after ArH2 plasma cleaning process will be shown. It is detected in the impacted bonding pad surface a thick layer of “O” underneath the “C” layer when undergo depth profiling using X-ray Photoelectron Spectroscopy (XPS) surface analysis. Wirebond 1st bond parameter have been optimized to break through these “O” layer which is believed to be a film of hydroxyl (-OH) where one hydrogen atom combined to one oxygen atom formed after the ArH2 plasma cleaning process. The wirebond parameter (pre-US power) used in this non-sticking on bond pad improvement is not new in the wirebond equipment available today in the market. But with its function, ball bonding was able to break through the thick “O” layer and good bonding is achieved.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128553846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511627
G. J. Abarro, Rod J. Delos Santos, Darwin J. De Lazo, A. Denoyo, Manny S. Ramos
This study attempts to explore Batch-type Microwave (B-MW) plasma cleaning as a potential alternative to the conventional Strip-type Radiofrequency (S-RF) plasma; for application prior molding to improve adhesion along the mold-lead frame interface. Performance of B-MW was evaluated in terms of improvement in surface wettability, quantified via Contact Angle (CA) measurements. Mix of typical industrial plasma gases (Ar, H2 and O2) were assessed. Constant flow pattern was observed to significantly improve surface wettability and uniformity compared to its pulsed counterpart; and also affect the effect of other factors on the over-all cleaning performance of B-MW. Proceeding with constant flow pattern, surface wetting was found to improve with increasing power and cleaning time. The combination of O2and H2 plasma was found to be more effective compared to utilizing them separately. Both cleaning time and flow rate increased the amount of reactive species that come in contact with the contaminants. With optimized parameters, both techniques are effective in addressing delamination; but B-MW was confirmed to be a more efficient method than S-RF i.e. better uniformity, 12% more effective in and improving surface wettability and at least 28% higher throughput.
{"title":"Batch Microwave Plasma Cleaning for Robustification of Automotive Devices an Alternative to Strip-Type Radiofrequency Plasma","authors":"G. J. Abarro, Rod J. Delos Santos, Darwin J. De Lazo, A. Denoyo, Manny S. Ramos","doi":"10.1109/IEMT.2018.8511627","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511627","url":null,"abstract":"This study attempts to explore Batch-type Microwave (B-MW) plasma cleaning as a potential alternative to the conventional Strip-type Radiofrequency (S-RF) plasma; for application prior molding to improve adhesion along the mold-lead frame interface. Performance of B-MW was evaluated in terms of improvement in surface wettability, quantified via Contact Angle (CA) measurements. Mix of typical industrial plasma gases (Ar, H2 and O2) were assessed. Constant flow pattern was observed to significantly improve surface wettability and uniformity compared to its pulsed counterpart; and also affect the effect of other factors on the over-all cleaning performance of B-MW. Proceeding with constant flow pattern, surface wetting was found to improve with increasing power and cleaning time. The combination of O2and H2 plasma was found to be more effective compared to utilizing them separately. Both cleaning time and flow rate increased the amount of reactive species that come in contact with the contaminants. With optimized parameters, both techniques are effective in addressing delamination; but B-MW was confirmed to be a more efficient method than S-RF i.e. better uniformity, 12% more effective in and improving surface wettability and at least 28% higher throughput.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121718402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511686
W. K. Loh, R. Kulterman, Chih Chung Hsu, H. Fu
One of the challenges for developing an electronic package is to understand the dynamic warpage behavior of the package even before having the real physical sample. Hence, industry relies on the use of simulation tools, be it the finite element model and analytical equations, to refine the design options to obtain a high confidence warpage prediction. However, this is never consistently predictable because of the underlying assumptions where the actual assembly process is a lot more complex. In this paper, the comparison of assembly process steps and modeling method is discussed coupled with a demonstration of the use of Moldex3D to predict the mold flow pattern and warpage prediction by leveraging the mold cure kinetics, PVTC (Pressure Volume Temperature Cure) and viscoelasticity material properties of the mold. Effect of mesh detail, mold shrinkage percentage and glass transition temperature were considered to provide some general trend of these parameters impacting the package warpage prediction. The use of analytical equation in managing the material properties transition from uncured to cured mold was demonstrated. Even with existing modeling capabilities, there is no one common modeling method and capability to capture all the potential package assembly process interaction. Hence, this is the motivation for further development.
{"title":"Modeling of Molded Electronic Package Warpage Characteristic with Cure Induced Shrinkage and Viscoelasticity Properties","authors":"W. K. Loh, R. Kulterman, Chih Chung Hsu, H. Fu","doi":"10.1109/IEMT.2018.8511686","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511686","url":null,"abstract":"One of the challenges for developing an electronic package is to understand the dynamic warpage behavior of the package even before having the real physical sample. Hence, industry relies on the use of simulation tools, be it the finite element model and analytical equations, to refine the design options to obtain a high confidence warpage prediction. However, this is never consistently predictable because of the underlying assumptions where the actual assembly process is a lot more complex. In this paper, the comparison of assembly process steps and modeling method is discussed coupled with a demonstration of the use of Moldex3D to predict the mold flow pattern and warpage prediction by leveraging the mold cure kinetics, PVTC (Pressure Volume Temperature Cure) and viscoelasticity material properties of the mold. Effect of mesh detail, mold shrinkage percentage and glass transition temperature were considered to provide some general trend of these parameters impacting the package warpage prediction. The use of analytical equation in managing the material properties transition from uncured to cured mold was demonstrated. Even with existing modeling capabilities, there is no one common modeling method and capability to capture all the potential package assembly process interaction. Hence, this is the motivation for further development.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124174731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/iemt.2018.8511755
Navaretnasinggam Arivindran, Derus Rozazmi, T. Ming
RF Power packages have complex bonding diagram (BD) with high loop and long length of tuning wires which are very critical to achieve the resonance frequency of the device. The high loop and long length of tuning wires are very sensitive to wire sweep occurrence after molding process. Lately, the RF Power devices are becoming more complex with additional tuning wires and ground wires [1]. The height of tuning wires plays a critical role to ensure proper efficiency of the device at the same time prone to wire sweep at molding process. During initial startup of the RF Power devices, pre sway was implemented at wire bond (WB) process. The tuning wires are swayed 3° so that after molding the wires will be sweep by the mold compound flow into the package and eventually the wires will be become straight after molding [2]. However, the latest RF Power TO288 package has longer tuning wires up to 180mils and tuning wire height up to 60mils [1]. The pre sway at wire bond cannot be applied as wire bonders do not have the capability to perform pre-sway for such a long and high loop wires. Due to limitation at WB, mold process has to find strategies to minimize the wire sweep occurrence. This particular paper discusses how molding process have optimized their molding parameters to minimize the wire sweep occurrence. This paper will give a complete summary of wire sweep improvements done for RF Power TO288 package in terms of process optimization and mold gate location. The learnings of RF TO288 wire sweep study was implemented to upcoming RF packages.
射频电源封装具有复杂的键合图(BD)，具有高回路和长调谐线，这对于实现器件的谐振频率至关重要。调弦线圈高、长度长，对成型后的扫丝现象非常敏感。最近，RF功率器件变得越来越复杂，有额外的调谐线和地线[1]。调丝高度对保证设备的合理效率起着至关重要的作用，同时在成型过程中也容易产生扫丝现象。在射频功率器件的初始启动过程中，在线键(WB)过程中实现预摇摆。调弦摆动3°，使调弦成型后被模具复合气流扫入包内，最终调弦成型后变直[2]。然而，最新的RF Power TO288封装具有更长的调谐线，最高可达180mils，调谐线高度可达60mils[1]。对于如此长且高的环线，由于焊线机没有能力进行预摇，因此不能采用焊线预摇。由于在WB上的限制，模具工艺必须找到最小化钢丝扫线发生的策略。本文讨论了如何优化成型工艺参数，以减少钢丝扫线的发生。本文将在工艺优化和模口位置方面对RF Power TO288封装的线扫描改进进行完整的总结。在即将推出的RF封装中实现了对RF TO288线扫描的学习。
{"title":"Wire Sweep Improvement for Tuning Wires in RF Power TO288 Packages","authors":"Navaretnasinggam Arivindran, Derus Rozazmi, T. Ming","doi":"10.1109/iemt.2018.8511755","DOIUrl":"https://doi.org/10.1109/iemt.2018.8511755","url":null,"abstract":"RF Power packages have complex bonding diagram (BD) with high loop and long length of tuning wires which are very critical to achieve the resonance frequency of the device. The high loop and long length of tuning wires are very sensitive to wire sweep occurrence after molding process. Lately, the RF Power devices are becoming more complex with additional tuning wires and ground wires [1]. The height of tuning wires plays a critical role to ensure proper efficiency of the device at the same time prone to wire sweep at molding process. During initial startup of the RF Power devices, pre sway was implemented at wire bond (WB) process. The tuning wires are swayed 3° so that after molding the wires will be sweep by the mold compound flow into the package and eventually the wires will be become straight after molding [2]. However, the latest RF Power TO288 package has longer tuning wires up to 180mils and tuning wire height up to 60mils [1]. The pre sway at wire bond cannot be applied as wire bonders do not have the capability to perform pre-sway for such a long and high loop wires. Due to limitation at WB, mold process has to find strategies to minimize the wire sweep occurrence. This particular paper discusses how molding process have optimized their molding parameters to minimize the wire sweep occurrence. This paper will give a complete summary of wire sweep improvements done for RF Power TO288 package in terms of process optimization and mold gate location. The learnings of RF TO288 wire sweep study was implemented to upcoming RF packages.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115351658","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511787
M. Schindler
In a lot of MEMS-based devices, stress decoupling is of highest importance in order to avoid temperature-induced stress, i.e. on the membranes of pressure sensors or microphones. DELO's latest generation of MEMS die attach (DA) adhesives reaches Young's moduli lower than e.g. those of silicones at room temperature. The patented mCD chemistry also allows for an optional light pre-fixation of the dispensed adhesive in order to avoid unwanted spreading or bleeding during placement of the MEMS chip and/or the final heat curing step (b-stage process). In addition, DELO has developed new materials for ASIC die coating and ASIC encapsulation. Exposing the ASIC die to e.g. IR radiation leads to unwanted signal noise, especially in MEMS microphones. The bare ASIC die is exposed to the back volume ambience on all five sides. Hence, all five surfaces of the die need to be shielded (five face coating) against IR. DELO has developed materials with tailored dispensing and flow properties for this application. These adhesives are optimized for jet dispensing, still leaving the freedom to adjust the layer thickness to the needs of the application. The coating covers all five surfaces very well while minimizing the spread on the substrate, keeping the footprint small. This paper describes the new possibilities for MEMS packaging arising from MEMS DA adhesives based on DELO's patented mCD chemistry featuring a Young's modulus of < 1MPa at room temperature, which is lower than that of silicones. A further benefit of this class of adhesives is its screen- or stencil-printability for a fast and precise production process. Bondlines of about 50 µm are achievable, improving stress decoupling significantly.
{"title":"Novel Materials for MEMS Packaging: MEMS Die Attach and ASIC Die Coating and Encapsulation","authors":"M. Schindler","doi":"10.1109/IEMT.2018.8511787","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511787","url":null,"abstract":"In a lot of MEMS-based devices, stress decoupling is of highest importance in order to avoid temperature-induced stress, i.e. on the membranes of pressure sensors or microphones. DELO's latest generation of MEMS die attach (DA) adhesives reaches Young's moduli lower than e.g. those of silicones at room temperature. The patented mCD chemistry also allows for an optional light pre-fixation of the dispensed adhesive in order to avoid unwanted spreading or bleeding during placement of the MEMS chip and/or the final heat curing step (b-stage process). In addition, DELO has developed new materials for ASIC die coating and ASIC encapsulation. Exposing the ASIC die to e.g. IR radiation leads to unwanted signal noise, especially in MEMS microphones. The bare ASIC die is exposed to the back volume ambience on all five sides. Hence, all five surfaces of the die need to be shielded (five face coating) against IR. DELO has developed materials with tailored dispensing and flow properties for this application. These adhesives are optimized for jet dispensing, still leaving the freedom to adjust the layer thickness to the needs of the application. The coating covers all five surfaces very well while minimizing the spread on the substrate, keeping the footprint small. This paper describes the new possibilities for MEMS packaging arising from MEMS DA adhesives based on DELO's patented mCD chemistry featuring a Young's modulus of < 1MPa at room temperature, which is lower than that of silicones. A further benefit of this class of adhesives is its screen- or stencil-printability for a fast and precise production process. Bondlines of about 50 µm are achievable, improving stress decoupling significantly.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130948265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511674
Yung Hsiang Lee, I. Chin, W. K. Loh
Reliability defects associated with thermal humidity environments are not new to the electronics packaging industry, yet to this day it remains a key concern even for our latest technologies. Moisture absorbed into electronic packaging can impact package warpage, cause corrosion, underfill crack and interfacial delamination. Fundamental studies are needed to better understand the effect of moisture interaction with different package designs. This paper summarizes the lab experiments and Finite Element Analysis (FEA) that have been performed to study package moisture absorption-desorption, room temperature (RT) warpage and dynamic warpage, on packages post exposure to thermal humidity environment. This has yielded good fundamental learning and identified areas for future work.
{"title":"Electronic Packaging Moisture Interaction Study","authors":"Yung Hsiang Lee, I. Chin, W. K. Loh","doi":"10.1109/IEMT.2018.8511674","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511674","url":null,"abstract":"Reliability defects associated with thermal humidity environments are not new to the electronics packaging industry, yet to this day it remains a key concern even for our latest technologies. Moisture absorbed into electronic packaging can impact package warpage, cause corrosion, underfill crack and interfacial delamination. Fundamental studies are needed to better understand the effect of moisture interaction with different package designs. This paper summarizes the lab experiments and Finite Element Analysis (FEA) that have been performed to study package moisture absorption-desorption, room temperature (RT) warpage and dynamic warpage, on packages post exposure to thermal humidity environment. This has yielded good fundamental learning and identified areas for future work.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124245075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511783
Kunjapat Mugunan, L. Ying, C. C. Fei
Analysis of semiconductor packages with stacked dies poses a great challenge when assessing the die attach integrity of the different dies. With multiple interfaces already existing within the package it becomes even more difficult if the individual dies are bonded using different die attach material e.g. solder for the Base Chip and glue for the Top Chip. Typically the non-destructive test employed by most of the failure analysis labs to detect delamination for such kind of packages is by using Scanning Acoustic Microscopy in Transmission Mode (Thru-Scan). This non-invasive technique transmits ultrasound through the sample and reveals delamination at all interfaces in a single scan. However with this mode there is no way to determine which interface is delaminated. Furthermore the degree of spatial resolution for this mode is also rather poor. Verification of the Thru-Scan results is normally carried out by performing a mechanical cross-section across the delaminated region to identify the affected interface. The work presented in this paper focuses on an alternative non-destructive method using the Reflection Mode (C-SAM) to verify the delamination detected by the Transmission Mode Thru-Scan by progressively scanning from the bottom of the package across each of the interfaces within the package to identify the exact location of the defect. Various destructive tests were subsequently performed to validate this alternative method. The results show not only the effectiveness of this method in determining the correct interface that was affected but the Reflective Mode scanning also proves that it can reveal defects which are not able to be detected by the Transmission Mode Thru-Scan.
{"title":"Verification of Delamination Observed in SAM Transmission Mode (Thru-Scan) Using Reflection Mode (C-SAM Bottom Scan)","authors":"Kunjapat Mugunan, L. Ying, C. C. Fei","doi":"10.1109/IEMT.2018.8511783","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511783","url":null,"abstract":"Analysis of semiconductor packages with stacked dies poses a great challenge when assessing the die attach integrity of the different dies. With multiple interfaces already existing within the package it becomes even more difficult if the individual dies are bonded using different die attach material e.g. solder for the Base Chip and glue for the Top Chip. Typically the non-destructive test employed by most of the failure analysis labs to detect delamination for such kind of packages is by using Scanning Acoustic Microscopy in Transmission Mode (Thru-Scan). This non-invasive technique transmits ultrasound through the sample and reveals delamination at all interfaces in a single scan. However with this mode there is no way to determine which interface is delaminated. Furthermore the degree of spatial resolution for this mode is also rather poor. Verification of the Thru-Scan results is normally carried out by performing a mechanical cross-section across the delaminated region to identify the affected interface. The work presented in this paper focuses on an alternative non-destructive method using the Reflection Mode (C-SAM) to verify the delamination detected by the Transmission Mode Thru-Scan by progressively scanning from the bottom of the package across each of the interfaces within the package to identify the exact location of the defect. Various destructive tests were subsequently performed to validate this alternative method. The results show not only the effectiveness of this method in determining the correct interface that was affected but the Reflective Mode scanning also proves that it can reveal defects which are not able to be detected by the Transmission Mode Thru-Scan.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511673
L. Chia, L. B. Huat, C. M. Wan, Mohamad Som Siti Robiatun, Jessie Liong Shih Man
Development of mircoelectronic packages are always moving towards smaller and thinner. This is in conjunction of consumers need for mobile and wearable electronic gadgets. In order to achieve this, beside improvements in packaging technologies silicon die had to be smaller and thinner too. However thinner packages increase the challenges of package stress and thinner silicon chip becomes more susceptible to process related weakness especially at the front-end processes. Silicon die strength is an important parameter to ensure the packing reliability under stringent conditions. The strength of silicon wafer is heavily influenced by the die thickness and wafer the backside surface preparation prior to metal deposition. Stresses induced in the silicon die throughout the process of wafer processing, packaging and die assembly. Small flaws such as small micro cracks or uneveness can occur during backside processes causing the strength of the Silicon die to decrease and cause failure at early stage of packaging process or even reliability concern. This paper investigated the effect of die strength to the surface morphology using 3 point bending test and 3D Laser Measuring Microscope. The die strength was characterized using 3 point bending test while surface morphology was characterized using 3D Laser Measuring Microscope. The evaluation was performed with silicon die singulated from wafers of unevenness at wafer backside. The silicon die was then categorized into 4 different types by unevenness location, 1) unevenness through complete die in x-direction, 2) unevenness through complete die in y-direction 3) unevenness at the middle of die, 4) unevenness at the edge of die. Silicon die strength of 4 different type of location of unevenness was being measured using 3 point bending test. The result showed that the depth of unevenness was not the main factor of low die strength. Unevenness location at the die is the main factor of low die strength. Die strength with unevenness at the edge of die having the lowest strength.
{"title":"Characterization of Silicon Die Strength with Different Die Backside Unevenness Location","authors":"L. Chia, L. B. Huat, C. M. Wan, Mohamad Som Siti Robiatun, Jessie Liong Shih Man","doi":"10.1109/IEMT.2018.8511673","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511673","url":null,"abstract":"Development of mircoelectronic packages are always moving towards smaller and thinner. This is in conjunction of consumers need for mobile and wearable electronic gadgets. In order to achieve this, beside improvements in packaging technologies silicon die had to be smaller and thinner too. However thinner packages increase the challenges of package stress and thinner silicon chip becomes more susceptible to process related weakness especially at the front-end processes. Silicon die strength is an important parameter to ensure the packing reliability under stringent conditions. The strength of silicon wafer is heavily influenced by the die thickness and wafer the backside surface preparation prior to metal deposition. Stresses induced in the silicon die throughout the process of wafer processing, packaging and die assembly. Small flaws such as small micro cracks or uneveness can occur during backside processes causing the strength of the Silicon die to decrease and cause failure at early stage of packaging process or even reliability concern. This paper investigated the effect of die strength to the surface morphology using 3 point bending test and 3D Laser Measuring Microscope. The die strength was characterized using 3 point bending test while surface morphology was characterized using 3D Laser Measuring Microscope. The evaluation was performed with silicon die singulated from wafers of unevenness at wafer backside. The silicon die was then categorized into 4 different types by unevenness location, 1) unevenness through complete die in x-direction, 2) unevenness through complete die in y-direction 3) unevenness at the middle of die, 4) unevenness at the edge of die. Silicon die strength of 4 different type of location of unevenness was being measured using 3 point bending test. The result showed that the depth of unevenness was not the main factor of low die strength. Unevenness location at the die is the main factor of low die strength. Die strength with unevenness at the edge of die having the lowest strength.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122303721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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