Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511650
Jk Chong, Ernest Estiller, Mark Rosel, Ronald Malapitan, Silnore Sabando, Lan M. Vu, Hanh Phan
This paper elaborates the development of Polyethylene Terephthalate-S-Type Passive Sensor (PET-SPS) in ON Semiconductor Vietnam (OSV), which is a new product business expansion. The SPS is using the miniature die technology with multiple sensing feature and functionalities integrated into a single IC. It eliminates the need of stimulus detector and the need for microcontroller at the sensing node. The die in this case is attached onto the aluminum antenna covered with closed cell foam. The entire package is covered with PET with adhesive layer at the outer part in order to stick to designated car surfaces during moisture detection application. SPS package incorporates various designs of antenna made according to sensitivity requirement. Several foam with different properties had been studied initially and the result have shown that a closed cell foam with low moisture absorption provides much better dielectric constant (DK) and loss tangent (DF) which are being used as spacer or insulation. This paper further discusses the challenges it encountered during the development and mass production stage and outlines all the countermeasures being implemented that eventually led to the complete success of the project.
{"title":"DEVELOPMENT OF PET-SPS IN OSV","authors":"Jk Chong, Ernest Estiller, Mark Rosel, Ronald Malapitan, Silnore Sabando, Lan M. Vu, Hanh Phan","doi":"10.1109/IEMT.2018.8511650","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511650","url":null,"abstract":"This paper elaborates the development of Polyethylene Terephthalate-S-Type Passive Sensor (PET-SPS) in ON Semiconductor Vietnam (OSV), which is a new product business expansion. The SPS is using the miniature die technology with multiple sensing feature and functionalities integrated into a single IC. It eliminates the need of stimulus detector and the need for microcontroller at the sensing node. The die in this case is attached onto the aluminum antenna covered with closed cell foam. The entire package is covered with PET with adhesive layer at the outer part in order to stick to designated car surfaces during moisture detection application. SPS package incorporates various designs of antenna made according to sensitivity requirement. Several foam with different properties had been studied initially and the result have shown that a closed cell foam with low moisture absorption provides much better dielectric constant (DK) and loss tangent (DF) which are being used as spacer or insulation. This paper further discusses the challenges it encountered during the development and mass production stage and outlines all the countermeasures being implemented that eventually led to the complete success of the project.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127307799","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511730
Lim Khai Herng, Queck Cham Hee
Gen2 Taper is built by Infineon Technologies THA department which is used for taping the component into ammopack packing. Gen2 taper is running 100% volume of PG-SSO-2-53 in PSSO STS line. The topic was self-initiated by team looking at the poor performance of Gen2 Taper with OEE 52.5% (Target 75%) and Yield 96.43% (Target 97.60%). The poor yield performance is the main detractor that caused overall PSSO STS unable to achieve the TCR (Target Cost Roadmap) target. It had been a bottleneck process deciding the delivery quality to the customers. The initiative above has got very positive management buy-in as this would avoid poor delivery which upset the customers. Harvesting the project will directly contributed to NLoP (Next Level of Productivity) because of better delivery, better yield.
{"title":"New Benchmarked Standard in Yield and OEE Improvement - SENS PSSO STS Gen2 Taper Performance Improvement with Breakthrough Innovative Solutions","authors":"Lim Khai Herng, Queck Cham Hee","doi":"10.1109/IEMT.2018.8511730","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511730","url":null,"abstract":"Gen2 Taper is built by Infineon Technologies THA department which is used for taping the component into ammopack packing. Gen2 taper is running 100% volume of PG-SSO-2-53 in PSSO STS line. The topic was self-initiated by team looking at the poor performance of Gen2 Taper with OEE 52.5% (Target 75%) and Yield 96.43% (Target 97.60%). The poor yield performance is the main detractor that caused overall PSSO STS unable to achieve the TCR (Target Cost Roadmap) target. It had been a bottleneck process deciding the delivery quality to the customers. The initiative above has got very positive management buy-in as this would avoid poor delivery which upset the customers. Harvesting the project will directly contributed to NLoP (Next Level of Productivity) because of better delivery, better yield.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127994602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511784
Aldin-John Andam Tuazon, Leow Chin Kee
The extent of this paper covers thin package with thicker die. In a thin package design with thick frame, low loop height requirement is expected. This condition is set to avoid exposed wire after Mold process and damage wire after Laser Mark process for pin identification. In Wire Bond process the assessment of low loop formation is critical. Low loop formation is susceptible to stress at ball neck and is known to be the foremost cause of broken wire issue. Normal loop profiles on thick die insist of having stress on ball neck and broken wire issue due to limited clearance to form the wire loop. The modified M-Ioop wire formation is the innovative solution for thicker die to meet the package loop height requirement and criteria with no sign of stress at ball neck and zero reject of broken wire.
{"title":"Modified M-Loop Wire Formation: An Innovative Solution in Wire Bond Process to Relieve Stress on Ball Neck Causing Broken Wire","authors":"Aldin-John Andam Tuazon, Leow Chin Kee","doi":"10.1109/IEMT.2018.8511784","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511784","url":null,"abstract":"The extent of this paper covers thin package with thicker die. In a thin package design with thick frame, low loop height requirement is expected. This condition is set to avoid exposed wire after Mold process and damage wire after Laser Mark process for pin identification. In Wire Bond process the assessment of low loop formation is critical. Low loop formation is susceptible to stress at ball neck and is known to be the foremost cause of broken wire issue. Normal loop profiles on thick die insist of having stress on ball neck and broken wire issue due to limited clearance to form the wire loop. The modified M-Ioop wire formation is the innovative solution for thicker die to meet the package loop height requirement and criteria with no sign of stress at ball neck and zero reject of broken wire.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"104 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115477066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511659
Jose Palagud, Sw Wang
Palladium coated copper wire has been introduced in the semiconductor wirebond industry to addressed issues related to bare copper wire, mainly fast oxidation. The presence of the palladium coat provides protection to oxidation of bare copper wire core for a short period of time. This is very useful especially on bond stitch on ball (BSOB) wirebonding where a stitch bond is placed on top of bump ball. The relative hardness of the coated copper wire however possess significant challenge for large scale BSOB wirebonding. Conventional gold (4N Au) wirebonding is the best choice but with rising cost the alternative version is preferred by the industry. Silver (88, 92, 95%Ag) alloy wires offers cheaper cost solution but still remain to be proven for high reliability wirebonding. Alloying also of Ag wires results to an increase in the resistivity of the wire. This is unwanted especially on Mosfet devices where RDSon resistance is significantly controlled. Combining cost and reliability performance requirements, palladium coated copper wire is the still best choice.
{"title":"Thick Palladium Coated Copper (PCC) Wire BSOB Bonding on a Pre-Plated Frame Chip on Lead Package","authors":"Jose Palagud, Sw Wang","doi":"10.1109/IEMT.2018.8511659","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511659","url":null,"abstract":"Palladium coated copper wire has been introduced in the semiconductor wirebond industry to addressed issues related to bare copper wire, mainly fast oxidation. The presence of the palladium coat provides protection to oxidation of bare copper wire core for a short period of time. This is very useful especially on bond stitch on ball (BSOB) wirebonding where a stitch bond is placed on top of bump ball. The relative hardness of the coated copper wire however possess significant challenge for large scale BSOB wirebonding. Conventional gold (4N Au) wirebonding is the best choice but with rising cost the alternative version is preferred by the industry. Silver (88, 92, 95%Ag) alloy wires offers cheaper cost solution but still remain to be proven for high reliability wirebonding. Alloying also of Ag wires results to an increase in the resistivity of the wire. This is unwanted especially on Mosfet devices where RDSon resistance is significantly controlled. Combining cost and reliability performance requirements, palladium coated copper wire is the still best choice.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121536355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511779
C. Ong
Electroless Nickel Immersion Gold (ENIG) plating could offer superior durability and high corrosion resistance as well as providing excellent solderability. However, in plating chemistry field, poor intermetallic between 2 metals will lead to adhesion failure, and which would impact customer mounting application or even field failures. The main challenges to achieved robust manufacturing process is to understand adhesion failure mode between Nickel (Ni bump) to Nickel Phosphorous (Ni-P), based on several factors. A fundamental aspect underlying the coating process can be defined in bath technique, parameter and pre-process preparation. In this study, author investigating on previous series of improvement actions in adhesion failure. Based on lesson learn, all implemented action done with assumption that individual quality indices are independent to each other. But in real practise, the assumption may not be valid always. A Series of Block RSM were performed to verified current control in TSxP Galvanic Manufacturing line. Introduction of outlier parameter in the DOE is to increase the experiment window, and adhesion test act as output response (C=0). Then, developed mathematical model from RSM regression were used to validated and analysed the develop model with current production window (loading factor). From RSM analysis, “ZERO” adhesion failure event can be achieved via optimization of current production window (loading factor).
{"title":"Thin Small Leadless Package's (TSLP): Adhesion Failure Analysis After Electroless Nickel Immersion Gold (ENIG) Process","authors":"C. Ong","doi":"10.1109/IEMT.2018.8511779","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511779","url":null,"abstract":"Electroless Nickel Immersion Gold (ENIG) plating could offer superior durability and high corrosion resistance as well as providing excellent solderability. However, in plating chemistry field, poor intermetallic between 2 metals will lead to adhesion failure, and which would impact customer mounting application or even field failures. The main challenges to achieved robust manufacturing process is to understand adhesion failure mode between Nickel (Ni bump) to Nickel Phosphorous (Ni-P), based on several factors. A fundamental aspect underlying the coating process can be defined in bath technique, parameter and pre-process preparation. In this study, author investigating on previous series of improvement actions in adhesion failure. Based on lesson learn, all implemented action done with assumption that individual quality indices are independent to each other. But in real practise, the assumption may not be valid always. A Series of Block RSM were performed to verified current control in TSxP Galvanic Manufacturing line. Introduction of outlier parameter in the DOE is to increase the experiment window, and adhesion test act as output response (C=0). Then, developed mathematical model from RSM regression were used to validated and analysed the develop model with current production window (loading factor). From RSM analysis, “ZERO” adhesion failure event can be achieved via optimization of current production window (loading factor).","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129150934","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511698
N. A. Abdul-Kadir, N. Sahar, W. Chan, F. Harun
The development of information and communication technology has improved health tele-care by providing more sophisticated analysis software to support a realtime processing of ECG signals. Moreover, intense research has been devoted to the development of an affordable and reliable ECG for daily monitoring and outpatient usage. Meanwhile, the increase in manufacturing of small system module in medical diagnostic equipment for digital signal processing (DSP) applications can provide affordable ECGs with real-time processing which is suitable for monitoring and alert system. In this study, a wireless communication channel of ECG is developed using an ESP8266 WiFi module and an BMD101 Neurosky bio-signal system-on-a-chip (SoC) device. The SoC is designed with a powerful DSP structure which has a filter, amplifier, 16-bit analog-digital converter and an integrated 22.1MHz clock reference signal. The ECG circuit is equipped with single lead of two inputs of positive and negative. The size of the ECG circuit is as compact as 4.5 cm × 3 cm of length x width and it is a portable device. The performance shows the ECG device was able to capture the normal sinus rhythm of 60 beat-per-minute (bpm), 80 bpm, 100 bpm and 120 bpm from a patient simulator. The ECG circuit design also able to capture abnormal sinus rhythm such as atrial fibrillation, ventricular tachycardia, ventricular fibrillation.
{"title":"A Portable WiFi ECG","authors":"N. A. Abdul-Kadir, N. Sahar, W. Chan, F. Harun","doi":"10.1109/IEMT.2018.8511698","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511698","url":null,"abstract":"The development of information and communication technology has improved health tele-care by providing more sophisticated analysis software to support a realtime processing of ECG signals. Moreover, intense research has been devoted to the development of an affordable and reliable ECG for daily monitoring and outpatient usage. Meanwhile, the increase in manufacturing of small system module in medical diagnostic equipment for digital signal processing (DSP) applications can provide affordable ECGs with real-time processing which is suitable for monitoring and alert system. In this study, a wireless communication channel of ECG is developed using an ESP8266 WiFi module and an BMD101 Neurosky bio-signal system-on-a-chip (SoC) device. The SoC is designed with a powerful DSP structure which has a filter, amplifier, 16-bit analog-digital converter and an integrated 22.1MHz clock reference signal. The ECG circuit is equipped with single lead of two inputs of positive and negative. The size of the ECG circuit is as compact as 4.5 cm × 3 cm of length x width and it is a portable device. The performance shows the ECG device was able to capture the normal sinus rhythm of 60 beat-per-minute (bpm), 80 bpm, 100 bpm and 120 bpm from a patient simulator. The ECG circuit design also able to capture abnormal sinus rhythm such as atrial fibrillation, ventricular tachycardia, ventricular fibrillation.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128949547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511750
Jocson Emil Lamco, B. Kahar, W. C. Mun
Lifted wedge on lead has been the common defect mode (as in Figure 1) encountered in wire bonding process. There are numerous causes for lifted wedge in which many have more obvious causes and some are more eluded to be identified and resolved. This article elaborates on the root causes of lifted stitch, like characterization of a good clamping design and layout through multiple output responses such as bonder current curve traces, design layout simulation, bending test and the shorter foot wedge tool bond parameter through DOE. This solution proved able to eliminate the lifted wedge problem.
{"title":"75um Al Thin Wire Lifted Wedge Solutions on Hanging Centre Lead in DPak","authors":"Jocson Emil Lamco, B. Kahar, W. C. Mun","doi":"10.1109/IEMT.2018.8511750","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511750","url":null,"abstract":"Lifted wedge on lead has been the common defect mode (as in Figure 1) encountered in wire bonding process. There are numerous causes for lifted wedge in which many have more obvious causes and some are more eluded to be identified and resolved. This article elaborates on the root causes of lifted stitch, like characterization of a good clamping design and layout through multiple output responses such as bonder current curve traces, design layout simulation, bending test and the shorter foot wedge tool bond parameter through DOE. This solution proved able to eliminate the lifted wedge problem.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"2 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131639476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511749
Jeriel Figueroa, Jeramie Pendor, E. Ong, Swee Har Khor
Seremban QFN line has enjoyed continuous growth of production volume for Multi-die Driver/Controller MOSFET (DrMOS) package. Current production DrMOS device integrates a Driver/Controller, high-side MOSFET and low-side MOSFET into a 6 mm × 6 mm 40-pin QFN packaging. To be able to continue our fair share on the market though, new package and new case outline which comes into a 5 mm × 5 mm QFN32 project was recently developed for production. The new package consists of a FET die, Copper Clip and Controller die which are stacked to reduce the overall solution size. This paper elaborates specifically the wire bond challenges and corresponding improvements executed addressing the issues, hence making this package the reference for subsequent DrMOS with Stacked Controller Die on Copper Clip. To be able to define the allowable maximum loop height that can consistently meet the minimum stacked Controller die to Top Package clearance and marking depth requirements, package stack-up worst case analysis and loop height robustness study that can meet up to +6 sigma were evaluated. Since the Controller die is sitting on top of the FET die and Copper Clip, simulation on worst Controller die displacement scenario from different directions was also assessed to guarantee enough bonding wire to Copper Clip edge clearance. Reliability, bondability, wire bonding parameters characterization and cliff experiments were studied as well to ensure critical responses are well within pre-defined specification after implementation of new package design.
{"title":"Wire Bond Qualification Challenges and Development of First Stacked Die on Copper Clip for Multi-Die Controller MOSFET Package","authors":"Jeriel Figueroa, Jeramie Pendor, E. Ong, Swee Har Khor","doi":"10.1109/IEMT.2018.8511749","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511749","url":null,"abstract":"Seremban QFN line has enjoyed continuous growth of production volume for Multi-die Driver/Controller MOSFET (DrMOS) package. Current production DrMOS device integrates a Driver/Controller, high-side MOSFET and low-side MOSFET into a 6 mm × 6 mm 40-pin QFN packaging. To be able to continue our fair share on the market though, new package and new case outline which comes into a 5 mm × 5 mm QFN32 project was recently developed for production. The new package consists of a FET die, Copper Clip and Controller die which are stacked to reduce the overall solution size. This paper elaborates specifically the wire bond challenges and corresponding improvements executed addressing the issues, hence making this package the reference for subsequent DrMOS with Stacked Controller Die on Copper Clip. To be able to define the allowable maximum loop height that can consistently meet the minimum stacked Controller die to Top Package clearance and marking depth requirements, package stack-up worst case analysis and loop height robustness study that can meet up to +6 sigma were evaluated. Since the Controller die is sitting on top of the FET die and Copper Clip, simulation on worst Controller die displacement scenario from different directions was also assessed to guarantee enough bonding wire to Copper Clip edge clearance. Reliability, bondability, wire bonding parameters characterization and cliff experiments were studied as well to ensure critical responses are well within pre-defined specification after implementation of new package design.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127866044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511739
S. Subaramaniym, Guirit Lynn Simporios, Kuek Hsieh Ting, M. A. Rahman, Wong Jia Yi, C. S. Fang
To big package was developed with large and thin chip on Copper (Cu) die pad frame and Lead-free solder in chip by chip (CbC) die attach process. Die breakage during thick Aluminum (Al) wire bond process was encountered. Failure analysis observed high magnitude of void under the wire bond area and also porosity in between the chip backside metallization (BSM) and solder layer. Several studies and analysis were conducted to prove all the contributing factors. The investigation shows Sn element from solder wire, oxide from the Cu lead frame and solder wire tend to dissolve through the molten solder and contribute to a porous mixed layer in between the chip BSM and Copper Tin (CuSn) intermetallic compound (IMC). The porosity of the mixed layer and depletion of the chip backside metallization can be exaggerated when higher thermal budget is supplied towards the bonded units during the die bonding process either due to longer machine idling time or high bonding temperature as experienced by the chip. Besides, high presence of Tin Oxide (SnO) from the solder wire during solder dispensing and spanking process is causing poor wettability towards chip backside as well as on die pad surface. This resulted in high magnitude of solder voids formation. The chip strength became weak with the present of big voids and porosity and thus not able to withstand high force during thick Al wire bonding process resulting to broken die defect. Controlling the thermal budget in die attach process towards the material and increasing the solder volume became essential to eliminate the problem.
{"title":"Understanding Die Breakage During Heavy Al Wedge Bonding for Large/Thin Chip (39mm2/75µm) in J-Alloy-Cu System","authors":"S. Subaramaniym, Guirit Lynn Simporios, Kuek Hsieh Ting, M. A. Rahman, Wong Jia Yi, C. S. Fang","doi":"10.1109/IEMT.2018.8511739","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511739","url":null,"abstract":"To big package was developed with large and thin chip on Copper (Cu) die pad frame and Lead-free solder in chip by chip (CbC) die attach process. Die breakage during thick Aluminum (Al) wire bond process was encountered. Failure analysis observed high magnitude of void under the wire bond area and also porosity in between the chip backside metallization (BSM) and solder layer. Several studies and analysis were conducted to prove all the contributing factors. The investigation shows Sn element from solder wire, oxide from the Cu lead frame and solder wire tend to dissolve through the molten solder and contribute to a porous mixed layer in between the chip BSM and Copper Tin (CuSn) intermetallic compound (IMC). The porosity of the mixed layer and depletion of the chip backside metallization can be exaggerated when higher thermal budget is supplied towards the bonded units during the die bonding process either due to longer machine idling time or high bonding temperature as experienced by the chip. Besides, high presence of Tin Oxide (SnO) from the solder wire during solder dispensing and spanking process is causing poor wettability towards chip backside as well as on die pad surface. This resulted in high magnitude of solder voids formation. The chip strength became weak with the present of big voids and porosity and thus not able to withstand high force during thick Al wire bonding process resulting to broken die defect. Controlling the thermal budget in die attach process towards the material and increasing the solder volume became essential to eliminate the problem.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125814088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511681
K. Siow, S. T. Chua, Z. A. Samah
Sintered silver (Ag) is being used as a Pb-free die-attach material for selected high-temperature application. Reliable sintered Ag joint depends on sintering pressure, time, temperature, paste formulation, bonding area and environment to achieve the desired density and bonding to the substrates. Interfacial region determines the bonding strength as much as the densification of the sintered Ag joint. Air atmosphere sintering of micron-Ag paste oxidized the Cu substrate to prevent any inter-diffusion of Ag atoms which were observable under HR-TEM. Yet, these copper oxides acted as adhesive to produce higher die shear strength than those sintered in the forming gas (N2-5%H2). The N2-5%H2 environment assisted the densification and sintering of micron-Ag to the pristine Cu substrate; increasing the bonding quality and die-shear strength, compared to the total absence of bonding for the micron-Ag paste sintered in N2 environment. This result highlights the importance of using high resolution TEM to understand the strengthening mechanism of micron-Ag joints at Cu substrates in air and forming (N2-5%H2) gases environment.
{"title":"Interfacial TEM Analysis of Sintered Silver in Air and N2-5%H2 Gases Environment","authors":"K. Siow, S. T. Chua, Z. A. Samah","doi":"10.1109/IEMT.2018.8511681","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511681","url":null,"abstract":"Sintered silver (Ag) is being used as a Pb-free die-attach material for selected high-temperature application. Reliable sintered Ag joint depends on sintering pressure, time, temperature, paste formulation, bonding area and environment to achieve the desired density and bonding to the substrates. Interfacial region determines the bonding strength as much as the densification of the sintered Ag joint. Air atmosphere sintering of micron-Ag paste oxidized the Cu substrate to prevent any inter-diffusion of Ag atoms which were observable under HR-TEM. Yet, these copper oxides acted as adhesive to produce higher die shear strength than those sintered in the forming gas (N2-5%H2). The N2-5%H2 environment assisted the densification and sintering of micron-Ag to the pristine Cu substrate; increasing the bonding quality and die-shear strength, compared to the total absence of bonding for the micron-Ag paste sintered in N2 environment. This result highlights the importance of using high resolution TEM to understand the strengthening mechanism of micron-Ag joints at Cu substrates in air and forming (N2-5%H2) gases environment.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130165020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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