Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511749
Jeriel Figueroa, Jeramie Pendor, E. Ong, Swee Har Khor
Seremban QFN line has enjoyed continuous growth of production volume for Multi-die Driver/Controller MOSFET (DrMOS) package. Current production DrMOS device integrates a Driver/Controller, high-side MOSFET and low-side MOSFET into a 6 mm × 6 mm 40-pin QFN packaging. To be able to continue our fair share on the market though, new package and new case outline which comes into a 5 mm × 5 mm QFN32 project was recently developed for production. The new package consists of a FET die, Copper Clip and Controller die which are stacked to reduce the overall solution size. This paper elaborates specifically the wire bond challenges and corresponding improvements executed addressing the issues, hence making this package the reference for subsequent DrMOS with Stacked Controller Die on Copper Clip. To be able to define the allowable maximum loop height that can consistently meet the minimum stacked Controller die to Top Package clearance and marking depth requirements, package stack-up worst case analysis and loop height robustness study that can meet up to +6 sigma were evaluated. Since the Controller die is sitting on top of the FET die and Copper Clip, simulation on worst Controller die displacement scenario from different directions was also assessed to guarantee enough bonding wire to Copper Clip edge clearance. Reliability, bondability, wire bonding parameters characterization and cliff experiments were studied as well to ensure critical responses are well within pre-defined specification after implementation of new package design.
{"title":"Wire Bond Qualification Challenges and Development of First Stacked Die on Copper Clip for Multi-Die Controller MOSFET Package","authors":"Jeriel Figueroa, Jeramie Pendor, E. Ong, Swee Har Khor","doi":"10.1109/IEMT.2018.8511749","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511749","url":null,"abstract":"Seremban QFN line has enjoyed continuous growth of production volume for Multi-die Driver/Controller MOSFET (DrMOS) package. Current production DrMOS device integrates a Driver/Controller, high-side MOSFET and low-side MOSFET into a 6 mm × 6 mm 40-pin QFN packaging. To be able to continue our fair share on the market though, new package and new case outline which comes into a 5 mm × 5 mm QFN32 project was recently developed for production. The new package consists of a FET die, Copper Clip and Controller die which are stacked to reduce the overall solution size. This paper elaborates specifically the wire bond challenges and corresponding improvements executed addressing the issues, hence making this package the reference for subsequent DrMOS with Stacked Controller Die on Copper Clip. To be able to define the allowable maximum loop height that can consistently meet the minimum stacked Controller die to Top Package clearance and marking depth requirements, package stack-up worst case analysis and loop height robustness study that can meet up to +6 sigma were evaluated. Since the Controller die is sitting on top of the FET die and Copper Clip, simulation on worst Controller die displacement scenario from different directions was also assessed to guarantee enough bonding wire to Copper Clip edge clearance. Reliability, bondability, wire bonding parameters characterization and cliff experiments were studied as well to ensure critical responses are well within pre-defined specification after implementation of new package design.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127866044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511722
Pedro Almazan, Chellamuthu Naveendran, Chai Ying Lee
Formation of Pb (Lead) flakes after die attach reflow process is a common concern when soldering packages with high temperature and soldering material with high in Lead components. Pb flakes are visually manifested on the chip bonding pad after the post Reflow cleaning process, general term as “flux cleaning process”. Small Pb solder spheres can leave behind stains on bonding pad and could reduce wire-bonding yields, with the failure mode of non-stick-on-pad. This Pb flakes formation was investigated and the findings from this phenomenon will be discussed in this paper since very few studies found in current literature. Hypothesis for Pb flakes formation could be attributed during solder Reflow process. Rapid temperature excursions caused the flux component within the solder paste to rapidly expand. Some of the ingredients within the flux component will reach their boiling temperature, at which small solder spheres will experience “popcorn effect” and re-deposited themselves to the bond pad. Hence, this paper also described the feasibility studies of different flux cleaning methods on how to effectively remove this Pb flakes. Process/Equipment and Materials were considered on these studies to validate the applicable solutions for Pb flakes removal on bonding pad. Considerations are the following for the flux cleaning evaluations; Equipment: Spray-in-Air (Water-based chemical), Centrifugal type (both Water-based & Solvent-based chemicals) and Ultrasonic (both Water-based & Solvent-based chemicals). Due to implications or risks identified from these feasibility considerations, the current Ultrasonic process + new cleaning Chemistry with better results were selected to precede further evaluation, including Reliability assessment.
{"title":"Feasibility of Pb Flakes Reduction Post Reflow Cleaning Process","authors":"Pedro Almazan, Chellamuthu Naveendran, Chai Ying Lee","doi":"10.1109/IEMT.2018.8511722","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511722","url":null,"abstract":"Formation of Pb (Lead) flakes after die attach reflow process is a common concern when soldering packages with high temperature and soldering material with high in Lead components. Pb flakes are visually manifested on the chip bonding pad after the post Reflow cleaning process, general term as “flux cleaning process”. Small Pb solder spheres can leave behind stains on bonding pad and could reduce wire-bonding yields, with the failure mode of non-stick-on-pad. This Pb flakes formation was investigated and the findings from this phenomenon will be discussed in this paper since very few studies found in current literature. Hypothesis for Pb flakes formation could be attributed during solder Reflow process. Rapid temperature excursions caused the flux component within the solder paste to rapidly expand. Some of the ingredients within the flux component will reach their boiling temperature, at which small solder spheres will experience “popcorn effect” and re-deposited themselves to the bond pad. Hence, this paper also described the feasibility studies of different flux cleaning methods on how to effectively remove this Pb flakes. Process/Equipment and Materials were considered on these studies to validate the applicable solutions for Pb flakes removal on bonding pad. Considerations are the following for the flux cleaning evaluations; Equipment: Spray-in-Air (Water-based chemical), Centrifugal type (both Water-based & Solvent-based chemicals) and Ultrasonic (both Water-based & Solvent-based chemicals). Due to implications or risks identified from these feasibility considerations, the current Ultrasonic process + new cleaning Chemistry with better results were selected to precede further evaluation, including Reliability assessment.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131373423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511665
Chu Wei
A method towards low cost chip assembly is by increase unit density per Leadframe with Top gate molding solution. In top gate molding, leadframe not require to dedicated space for mold runner in transfer process. That space will replace with more units by lower unit column-to-column pitch distance. Typical challenge of top gate molding is wire sweep especially on unit at Leadframe outer row. EMC injected into units on Leadframe outer row experiencing unbalance mold flow that challenging the molding process development. CAE simulation tool used to predict mold flow behavior and improvement runner design to minimize mold flow unbalance at end of transfer filling process. DOE experiment was perform to optimize transfer time range between 7.8s to 10.5s. Wire loop height optimization was perform as continuous improvement to improve wire sweep in QFP top gate molding from 10.47% to 7%.
{"title":"Top Gate Molding and Wire Sweep Improvement in Full Plastic QFP Packages","authors":"Chu Wei","doi":"10.1109/IEMT.2018.8511665","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511665","url":null,"abstract":"A method towards low cost chip assembly is by increase unit density per Leadframe with Top gate molding solution. In top gate molding, leadframe not require to dedicated space for mold runner in transfer process. That space will replace with more units by lower unit column-to-column pitch distance. Typical challenge of top gate molding is wire sweep especially on unit at Leadframe outer row. EMC injected into units on Leadframe outer row experiencing unbalance mold flow that challenging the molding process development. CAE simulation tool used to predict mold flow behavior and improvement runner design to minimize mold flow unbalance at end of transfer filling process. DOE experiment was perform to optimize transfer time range between 7.8s to 10.5s. Wire loop height optimization was perform as continuous improvement to improve wire sweep in QFP top gate molding from 10.47% to 7%.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"172 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131610860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511745
Que Wei, Loo Shei Meng
Ag (Silver) wire is an emerging choice for packaging for its excellent mechanical properties and lower cost. The introduction of Ag alloy wire (~95% purity) in STMicroelectronics has been done to overcome the limitations of Cu (Copper) wire (hardness). A new development approach has been applied to ensure the highest manufacturing robustness. However, this also came with some challenges that were faced at the beginning to stabilize ramp up and manufacturing production. Design of Experiments was done using Robust Development approach: this had improved the process workability. One wire-bonding recipe is able to be used on multiple Front End technologies with this approach. This helped to simplify production management in the assembly lines. A strict quality control approach is used to minimize manufacturing variations and this has strong benefit in improving MTBA (Mean Time between Assist). FMEA (Failure Modes and Effects Analysis) methodology helped identify key risks for studies and analysis, while increasing the workability for wire bond process. Quick and long-term reliability were done on the weekly lots, to not only assess the production, but also protect our customer.
{"title":"Manufacturability of Ag Wire for Mass Production - Challenges and Robustness","authors":"Que Wei, Loo Shei Meng","doi":"10.1109/IEMT.2018.8511745","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511745","url":null,"abstract":"Ag (Silver) wire is an emerging choice for packaging for its excellent mechanical properties and lower cost. The introduction of Ag alloy wire (~95% purity) in STMicroelectronics has been done to overcome the limitations of Cu (Copper) wire (hardness). A new development approach has been applied to ensure the highest manufacturing robustness. However, this also came with some challenges that were faced at the beginning to stabilize ramp up and manufacturing production. Design of Experiments was done using Robust Development approach: this had improved the process workability. One wire-bonding recipe is able to be used on multiple Front End technologies with this approach. This helped to simplify production management in the assembly lines. A strict quality control approach is used to minimize manufacturing variations and this has strong benefit in improving MTBA (Mean Time between Assist). FMEA (Failure Modes and Effects Analysis) methodology helped identify key risks for studies and analysis, while increasing the workability for wire bond process. Quick and long-term reliability were done on the weekly lots, to not only assess the production, but also protect our customer.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132373223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511681
K. Siow, S. T. Chua, Z. A. Samah
Sintered silver (Ag) is being used as a Pb-free die-attach material for selected high-temperature application. Reliable sintered Ag joint depends on sintering pressure, time, temperature, paste formulation, bonding area and environment to achieve the desired density and bonding to the substrates. Interfacial region determines the bonding strength as much as the densification of the sintered Ag joint. Air atmosphere sintering of micron-Ag paste oxidized the Cu substrate to prevent any inter-diffusion of Ag atoms which were observable under HR-TEM. Yet, these copper oxides acted as adhesive to produce higher die shear strength than those sintered in the forming gas (N2-5%H2). The N2-5%H2 environment assisted the densification and sintering of micron-Ag to the pristine Cu substrate; increasing the bonding quality and die-shear strength, compared to the total absence of bonding for the micron-Ag paste sintered in N2 environment. This result highlights the importance of using high resolution TEM to understand the strengthening mechanism of micron-Ag joints at Cu substrates in air and forming (N2-5%H2) gases environment.
{"title":"Interfacial TEM Analysis of Sintered Silver in Air and N2-5%H2 Gases Environment","authors":"K. Siow, S. T. Chua, Z. A. Samah","doi":"10.1109/IEMT.2018.8511681","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511681","url":null,"abstract":"Sintered silver (Ag) is being used as a Pb-free die-attach material for selected high-temperature application. Reliable sintered Ag joint depends on sintering pressure, time, temperature, paste formulation, bonding area and environment to achieve the desired density and bonding to the substrates. Interfacial region determines the bonding strength as much as the densification of the sintered Ag joint. Air atmosphere sintering of micron-Ag paste oxidized the Cu substrate to prevent any inter-diffusion of Ag atoms which were observable under HR-TEM. Yet, these copper oxides acted as adhesive to produce higher die shear strength than those sintered in the forming gas (N2-5%H2). The N2-5%H2 environment assisted the densification and sintering of micron-Ag to the pristine Cu substrate; increasing the bonding quality and die-shear strength, compared to the total absence of bonding for the micron-Ag paste sintered in N2 environment. This result highlights the importance of using high resolution TEM to understand the strengthening mechanism of micron-Ag joints at Cu substrates in air and forming (N2-5%H2) gases environment.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130165020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511739
S. Subaramaniym, Guirit Lynn Simporios, Kuek Hsieh Ting, M. A. Rahman, Wong Jia Yi, C. S. Fang
To big package was developed with large and thin chip on Copper (Cu) die pad frame and Lead-free solder in chip by chip (CbC) die attach process. Die breakage during thick Aluminum (Al) wire bond process was encountered. Failure analysis observed high magnitude of void under the wire bond area and also porosity in between the chip backside metallization (BSM) and solder layer. Several studies and analysis were conducted to prove all the contributing factors. The investigation shows Sn element from solder wire, oxide from the Cu lead frame and solder wire tend to dissolve through the molten solder and contribute to a porous mixed layer in between the chip BSM and Copper Tin (CuSn) intermetallic compound (IMC). The porosity of the mixed layer and depletion of the chip backside metallization can be exaggerated when higher thermal budget is supplied towards the bonded units during the die bonding process either due to longer machine idling time or high bonding temperature as experienced by the chip. Besides, high presence of Tin Oxide (SnO) from the solder wire during solder dispensing and spanking process is causing poor wettability towards chip backside as well as on die pad surface. This resulted in high magnitude of solder voids formation. The chip strength became weak with the present of big voids and porosity and thus not able to withstand high force during thick Al wire bonding process resulting to broken die defect. Controlling the thermal budget in die attach process towards the material and increasing the solder volume became essential to eliminate the problem.
{"title":"Understanding Die Breakage During Heavy Al Wedge Bonding for Large/Thin Chip (39mm2/75µm) in J-Alloy-Cu System","authors":"S. Subaramaniym, Guirit Lynn Simporios, Kuek Hsieh Ting, M. A. Rahman, Wong Jia Yi, C. S. Fang","doi":"10.1109/IEMT.2018.8511739","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511739","url":null,"abstract":"To big package was developed with large and thin chip on Copper (Cu) die pad frame and Lead-free solder in chip by chip (CbC) die attach process. Die breakage during thick Aluminum (Al) wire bond process was encountered. Failure analysis observed high magnitude of void under the wire bond area and also porosity in between the chip backside metallization (BSM) and solder layer. Several studies and analysis were conducted to prove all the contributing factors. The investigation shows Sn element from solder wire, oxide from the Cu lead frame and solder wire tend to dissolve through the molten solder and contribute to a porous mixed layer in between the chip BSM and Copper Tin (CuSn) intermetallic compound (IMC). The porosity of the mixed layer and depletion of the chip backside metallization can be exaggerated when higher thermal budget is supplied towards the bonded units during the die bonding process either due to longer machine idling time or high bonding temperature as experienced by the chip. Besides, high presence of Tin Oxide (SnO) from the solder wire during solder dispensing and spanking process is causing poor wettability towards chip backside as well as on die pad surface. This resulted in high magnitude of solder voids formation. The chip strength became weak with the present of big voids and porosity and thus not able to withstand high force during thick Al wire bonding process resulting to broken die defect. Controlling the thermal budget in die attach process towards the material and increasing the solder volume became essential to eliminate the problem.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125814088","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511724
Wai Shan Liau, Tek Keong Gan
The common problem vespel collet; the eutectic die bonding process pick up tool; is a short lifespan. The collet tip dimension is similar to shrink chip (size<0.05mm2), which causes an aggressive rubbing effect during die pick and bond cycle. Debris is generated and then accumulated the surrounding of the collet tip surface gradually. Clogged vespel collet tip will result in die pickup issue and accummulated debris will also damage the protruded guard ring design on the chip surface. As such, the vespel collet is then controlled at few ten thousand touchdown. Extending vespel collet lifespan by optimizing die bonding process parameter, changing collet tip dimension and material are not feasible in this situation. The current vespel collet is the hardest material and the smallest tip dimension that can be used in the application. Removing the damaged vespel collet tip by the cleaning process would then be a solution from other perspective. Conventional method is to have manual collet cleaning process offline by human, which lead to high machine idling time and inconsistent collet cleaning quality. An innovative smart manufacturing concept known as “collet auto clean system” is established. It is a programmable fixture that mounted on the die bonding machine to clean vespel collet tip automatically at every predefine touchdown before reaching of the total vespel collet touch down setting. The challenges face are (1) vespel collet tip shape & dimension design to maintain the same tip shape and to withstand the turning force without any broken tip after cleaning, (2) polishing paper grading selection; cleaning parameters definition and cleaned collet tip in-line buyoff for an effective cleaning process. With the implementation of “collet auto clean system”, the vespel collet lifespan is then improved from few ten thousand to few hundred thousand touchdown. Few hundred million parts are delivered without comprising process stability and quality deviation. Vespel collet material consumption has improved from few hundreds pcs to few ten pcs yearly. Also, 3 % collet changing schedule downtime is gained from collet changing interval before every 3 hours to after every 1.2 days.
{"title":"‘Collet Auto Clean System’, A Smart Automatic Solution for Die Bonding Pick Up Tool Lifespan & Throughput Enhancement","authors":"Wai Shan Liau, Tek Keong Gan","doi":"10.1109/IEMT.2018.8511724","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511724","url":null,"abstract":"The common problem vespel collet; the eutectic die bonding process pick up tool; is a short lifespan. The collet tip dimension is similar to shrink chip (size<0.05mm2), which causes an aggressive rubbing effect during die pick and bond cycle. Debris is generated and then accumulated the surrounding of the collet tip surface gradually. Clogged vespel collet tip will result in die pickup issue and accummulated debris will also damage the protruded guard ring design on the chip surface. As such, the vespel collet is then controlled at few ten thousand touchdown. Extending vespel collet lifespan by optimizing die bonding process parameter, changing collet tip dimension and material are not feasible in this situation. The current vespel collet is the hardest material and the smallest tip dimension that can be used in the application. Removing the damaged vespel collet tip by the cleaning process would then be a solution from other perspective. Conventional method is to have manual collet cleaning process offline by human, which lead to high machine idling time and inconsistent collet cleaning quality. An innovative smart manufacturing concept known as “collet auto clean system” is established. It is a programmable fixture that mounted on the die bonding machine to clean vespel collet tip automatically at every predefine touchdown before reaching of the total vespel collet touch down setting. The challenges face are (1) vespel collet tip shape & dimension design to maintain the same tip shape and to withstand the turning force without any broken tip after cleaning, (2) polishing paper grading selection; cleaning parameters definition and cleaned collet tip in-line buyoff for an effective cleaning process. With the implementation of “collet auto clean system”, the vespel collet lifespan is then improved from few ten thousand to few hundred thousand touchdown. Few hundred million parts are delivered without comprising process stability and quality deviation. Vespel collet material consumption has improved from few hundreds pcs to few ten pcs yearly. Also, 3 % collet changing schedule downtime is gained from collet changing interval before every 3 hours to after every 1.2 days.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124374315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511658
C. Ong, W. Ng, Kian-Pin Queck
In Thin Small Non-Leaded Packages (TSNP) design, heat resistance tape (i.e. RT321 and RT321+CD1) were used as leadframe carrier throughout TSNP assembly manufacturing line. These carrier acts as package backbone during molding process and were removed during detape process as to expose Cu pad (2nd interconnection) before plating process. However, under un-optimized parameter condition in TSNP assembly manufacturing line, the heat resistance tape shows inconsistence performances and contribute high assembly yield losses. The current paper investigates the effect of heat resistance tape on torn tape and excess solder defect in detape and plating process respectively. Torn tape defect occurred during mechanical peeling (remove heat resistance tape as to expose Cu pad). Whereas, excess solder defect were detected after Sn plating process, excess solder defined as x and y pad dimension out of specification based on Infineon Technologies Process Control. The DOE's input factor of Detape (i.e. Temperature and Peeling Method), and Sn Plating (i.e. Current, Loading Method and Conveyor Speed) were established with the help of CEDA software. RT321+CD1 tape resulted to be best fit in TSNP manufacturing line compared to RT321 tape due to tape physical properties compatibility. However, at high detape temperature, low plating current and high conveyor speed, performances of RT321 tape are comparable with RT321+CD1.
{"title":"Effect of Leadframe Tape Material on Thin Small Non-Leaded Packages (TSNP) Manufacturing Line","authors":"C. Ong, W. Ng, Kian-Pin Queck","doi":"10.1109/IEMT.2018.8511658","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511658","url":null,"abstract":"In Thin Small Non-Leaded Packages (TSNP) design, heat resistance tape (i.e. RT321 and RT321+CD1) were used as leadframe carrier throughout TSNP assembly manufacturing line. These carrier acts as package backbone during molding process and were removed during detape process as to expose Cu pad (2nd interconnection) before plating process. However, under un-optimized parameter condition in TSNP assembly manufacturing line, the heat resistance tape shows inconsistence performances and contribute high assembly yield losses. The current paper investigates the effect of heat resistance tape on torn tape and excess solder defect in detape and plating process respectively. Torn tape defect occurred during mechanical peeling (remove heat resistance tape as to expose Cu pad). Whereas, excess solder defect were detected after Sn plating process, excess solder defined as x and y pad dimension out of specification based on Infineon Technologies Process Control. The DOE's input factor of Detape (i.e. Temperature and Peeling Method), and Sn Plating (i.e. Current, Loading Method and Conveyor Speed) were established with the help of CEDA software. RT321+CD1 tape resulted to be best fit in TSNP manufacturing line compared to RT321 tape due to tape physical properties compatibility. However, at high detape temperature, low plating current and high conveyor speed, performances of RT321 tape are comparable with RT321+CD1.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130716884","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511697
Younan Hua, Yue Shen, J. Goh, Y. Kee, Xiaomin Li
In wafer fab and assembly processes, non-stick on pad (NSOP) problem impacts seriously yields of the products as the electrical communication between the integrated circuit (IC) chips and other components taking place via the bondpad of the chip. NSOP (Non-Stick On pad) is a failure mode of the IC chip that occurs as a result of poor adhesion between the Aluminium (A1) bondpad and either the bond wire or solder contact. Such failures can be observed even for nanoscale chips such as the 65nm, 45nm, 40nm, and 28nm nodes and beyond. In order to eliminate NSOP problem to enhance the yield of products, process engineers from wafer fab and assembly house together with failure analysis engineers have to know what a good quality bondpad is and how to evaluate and qualify. On these common questions and concerns, in this paper, we will study and introduce Al bondpad qualification methodologies (OSAT and OSSD) and eliminate NSOP problem.
{"title":"Qualification of Microchip Al Bondpad and Elimination of NSOP","authors":"Younan Hua, Yue Shen, J. Goh, Y. Kee, Xiaomin Li","doi":"10.1109/IEMT.2018.8511697","DOIUrl":"https://doi.org/10.1109/IEMT.2018.8511697","url":null,"abstract":"In wafer fab and assembly processes, non-stick on pad (NSOP) problem impacts seriously yields of the products as the electrical communication between the integrated circuit (IC) chips and other components taking place via the bondpad of the chip. NSOP (Non-Stick On pad) is a failure mode of the IC chip that occurs as a result of poor adhesion between the Aluminium (A1) bondpad and either the bond wire or solder contact. Such failures can be observed even for nanoscale chips such as the 65nm, 45nm, 40nm, and 28nm nodes and beyond. In order to eliminate NSOP problem to enhance the yield of products, process engineers from wafer fab and assembly house together with failure analysis engineers have to know what a good quality bondpad is and how to evaluate and qualify. On these common questions and concerns, in this paper, we will study and introduce Al bondpad qualification methodologies (OSAT and OSSD) and eliminate NSOP problem.","PeriodicalId":292144,"journal":{"name":"2018 IEEE 38th International Electronics Manufacturing Technology Conference (IEMT)","volume":"23 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120910422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-01DOI: 10.1109/IEMT.2018.8511774
Liew Soon Lee, Ruel Aranda, Rasydan Tahir
As technology grows, semiconductor industry is developing towards thinner & smaller packages to meet market demand. Uneven package shrinkage during manufacturing of Molded Matrix Array Package affects the assembly yield and the yield of succeeding processes including test. Thin Small Leadless Package is no exception to this matter and has experienced a high yield loss above 6.58% at test process for one of its packages. This paper discusses and investigates in details some of the factors which might lead to the uneven volumetric shrinkage of the mold across the panel. There are two factors which are investigated thoroughly in this study, namely: the effect of leadframe design; and the effect of assembly processes (molding, post mold cure PMC and reflow process) towards molding compound material characteristics. Thermomechanical simulation is set up to give a better insight on the first factor, meanwhile the latter is addressed via material characterization as well as physical assessment under actual process conditions. After evaluating the results, it is determined that the leadframe geometry gives a more dominant impact on the uneven volumetric shrinkage of the molding compound issue as compared to the process conditions. This brings to a final recommendation to mitigate the shrinkage by balancing the metal content on the vent and gate area of the leadframe.
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