Pub Date : 1999-07-01DOI: 10.1109/PESC.1999.785604
Jin-Woo Ahn, Seok-Gyu Oh, Sung-Young Pyo, Cheul-U. Kim, Y. Hwang
The switched reluctance drive is known to provide good adjustable speed characteristics. However, higher torque ripple and lack of the precise speed control are drawbacks. These problems lie in the fact that SR drive is not operated with an MMF current specified for dwell angle and input voltage. To reduce torque ripple and to have precise speed control, the SR drive has to control the dwell angle and input voltage instantaneously. In the paper, a PLL (phase locked loop) technique is adopted to regulate the dwell angle and input voltage. A PLL control technique in conjunction with a dynamic dwell angle control scheme has good speed regulation characteristics. The DSP based control system is used to realize this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.
{"title":"Digital PLL technique for precise speed control of SR drive","authors":"Jin-Woo Ahn, Seok-Gyu Oh, Sung-Young Pyo, Cheul-U. Kim, Y. Hwang","doi":"10.1109/PESC.1999.785604","DOIUrl":"https://doi.org/10.1109/PESC.1999.785604","url":null,"abstract":"The switched reluctance drive is known to provide good adjustable speed characteristics. However, higher torque ripple and lack of the precise speed control are drawbacks. These problems lie in the fact that SR drive is not operated with an MMF current specified for dwell angle and input voltage. To reduce torque ripple and to have precise speed control, the SR drive has to control the dwell angle and input voltage instantaneously. In the paper, a PLL (phase locked loop) technique is adopted to regulate the dwell angle and input voltage. A PLL control technique in conjunction with a dynamic dwell angle control scheme has good speed regulation characteristics. The DSP based control system is used to realize this drive system. Test results show that the system has the ability to achieve good dynamic and precise speed control.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122917136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.789050
J.J. Jafar, B. G. Fernandes
A novel quasi-resonant DC-link (QRDCL) inverter for induction motor drives is proposed. Only one additional switching device is being used to create zero voltage instants in the DC-link to facilitate zero voltage switching of the inverter devices under all loading conditions. The voltage stress on the inverter devices is around (1.01-1.10)pu and any PWM technique can be used to control the output voltage of the inverter. In this paper, the principle of operation and the detailed analysis of the proposed QRDCL inverter are presented. Design criterion to achieve soft switching of the inverter devices is also given. Detailed PSPICE simulation studies are carried out to predict the performance of the inverter feeding an induction motor and these simulated results are verified experimentally.
{"title":"A novel quasi-resonant DC-link PWM inverter for induction motor drive","authors":"J.J. Jafar, B. G. Fernandes","doi":"10.1109/PESC.1999.789050","DOIUrl":"https://doi.org/10.1109/PESC.1999.789050","url":null,"abstract":"A novel quasi-resonant DC-link (QRDCL) inverter for induction motor drives is proposed. Only one additional switching device is being used to create zero voltage instants in the DC-link to facilitate zero voltage switching of the inverter devices under all loading conditions. The voltage stress on the inverter devices is around (1.01-1.10)pu and any PWM technique can be used to control the output voltage of the inverter. In this paper, the principle of operation and the detailed analysis of the proposed QRDCL inverter are presented. Design criterion to achieve soft switching of the inverter devices is also given. Detailed PSPICE simulation studies are carried out to predict the performance of the inverter feeding an induction motor and these simulated results are verified experimentally.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127109994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.789002
J. D. Oliveira, V. J. Farias, L. C. Freitas, J. Vieira
This paper presents a soft switching PWM AC/AC full-bridge circuit that will be employed at the development of a serial regulator to contribute supplying 20% of total load power when vi(t)=180 V and consuming 10% of the power supplied to load when vi(t)=240 V. It does not contribute anything when vi(t)=220 V. Principle of operation, theoretical analysis, and design procedure are provided. The soft switching PWM AC/AC full bridge regulator has been validated by simulation results.
{"title":"A serial regulator using a soft switching PWM AC/AC full bridge-converter","authors":"J. D. Oliveira, V. J. Farias, L. C. Freitas, J. Vieira","doi":"10.1109/PESC.1999.789002","DOIUrl":"https://doi.org/10.1109/PESC.1999.789002","url":null,"abstract":"This paper presents a soft switching PWM AC/AC full-bridge circuit that will be employed at the development of a serial regulator to contribute supplying 20% of total load power when vi(t)=180 V and consuming 10% of the power supplied to load when vi(t)=240 V. It does not contribute anything when vi(t)=220 V. Principle of operation, theoretical analysis, and design procedure are provided. The soft switching PWM AC/AC full bridge regulator has been validated by simulation results.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123262349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.785603
Ming Lin, Tian‐Hua Liu
This paper presents a systematic robust controller design for a synchronous reluctance drive system. Based on a simplified model of the system, a robust position controller has been derived. A digital signal processor, TMS-320-C30, is used to implement the control algorithm. Furthermore, all the current, velocity, and position control loops are executed by the digital signal processor. The system, as a result, is very flexible. Although the hardware circuit of the system is very simple, the synchronous reluctance drive system can accurately control a one-axis table. In addition, the system also has good transient response, load disturbance response, and tracking ability. Several experimental results validate the theoretical analysis.
{"title":"Robust controller design for a synchronous reluctance drive","authors":"Ming Lin, Tian‐Hua Liu","doi":"10.1109/PESC.1999.785603","DOIUrl":"https://doi.org/10.1109/PESC.1999.785603","url":null,"abstract":"This paper presents a systematic robust controller design for a synchronous reluctance drive system. Based on a simplified model of the system, a robust position controller has been derived. A digital signal processor, TMS-320-C30, is used to implement the control algorithm. Furthermore, all the current, velocity, and position control loops are executed by the digital signal processor. The system, as a result, is very flexible. Although the hardware circuit of the system is very simple, the synchronous reluctance drive system can accurately control a one-axis table. In addition, the system also has good transient response, load disturbance response, and tracking ability. Several experimental results validate the theoretical analysis.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114948186","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.785666
Jian Sun, D. Mitchell, D. E. Jenkins
This paper describes improved averaged models for PWM converters operating either in the discontinuous conduction mode (DCM) or with constant on- or off-time control. For DCM operation, an intrinsic delay is identified to exist between a perturbation in the on-time of the switch and the resulting perturbation in the off-time. For constant on- or off-time control, an analytical model is derived for the modulator that shows interesting phase lead and nonlinear, frequency dependent characteristics. Inclusion of these effects results in new averaged models, which are accurate up to one-third of the switching frequency, and corrects for the large discrepancy exhibited by previous models.
{"title":"Delay effects in averaged modeling of PWM converters","authors":"Jian Sun, D. Mitchell, D. E. Jenkins","doi":"10.1109/PESC.1999.785666","DOIUrl":"https://doi.org/10.1109/PESC.1999.785666","url":null,"abstract":"This paper describes improved averaged models for PWM converters operating either in the discontinuous conduction mode (DCM) or with constant on- or off-time control. For DCM operation, an intrinsic delay is identified to exist between a perturbation in the on-time of the switch and the resulting perturbation in the off-time. For constant on- or off-time control, an analytical model is derived for the modulator that shows interesting phase lead and nonlinear, frequency dependent characteristics. Inclusion of these effects results in new averaged models, which are accurate up to one-third of the switching frequency, and corrects for the large discrepancy exhibited by previous models.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123943499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.785650
J. Alonso, A. Calleja, J. Ribas, E. López, M. Rico, J. Sebastián, J. Arau, M. Ponce
This paper investigates the characteristics and features of a novel high input power factor electronic ballast based on the input current shaper (ICS) arrangement. The ICS is implemented between main rectifier and bulk capacitor in order to increase the conduction angle of the main rectifier diodes up to a minimum value to obtain low current harmonics injected to the mains. In this paper, the ICS is implemented using a flyback converter operating in discontinuous conduction mode, and the ballast features both good efficiency and dimming capability. Experimental results from a 40 W fluorescent lamp prototype are presented to evaluate the proposed solution.
{"title":"Investigation of a novel high-power-factor electronic ballast based on the input current shaper","authors":"J. Alonso, A. Calleja, J. Ribas, E. López, M. Rico, J. Sebastián, J. Arau, M. Ponce","doi":"10.1109/PESC.1999.785650","DOIUrl":"https://doi.org/10.1109/PESC.1999.785650","url":null,"abstract":"This paper investigates the characteristics and features of a novel high input power factor electronic ballast based on the input current shaper (ICS) arrangement. The ICS is implemented between main rectifier and bulk capacitor in order to increase the conduction angle of the main rectifier diodes up to a minimum value to obtain low current harmonics injected to the mains. In this paper, the ICS is implemented using a flyback converter operating in discontinuous conduction mode, and the ballast features both good efficiency and dimming capability. Experimental results from a 40 W fluorescent lamp prototype are presented to evaluate the proposed solution.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"415 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115983278","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.785644
Dongsheng Zhou, D. Rouaud
Three-level neutral point clamp topology has attracted applications in medium-voltage high-power drive systems. Since the topology utilizes the neutral point voltage to achieve half bus voltage withstand of power devices and three-level output voltage delivery, it is critical to balance the neutral point voltage in occasions of disturbed or even continuous unbalance load conditions. This paper proposes a couple of balancing techniques based on space vector modulation principle and experimentally compares their effectiveness against the existing method.
{"title":"Experimental comparisons of space vector neutral point balancing strategies for three-level topology","authors":"Dongsheng Zhou, D. Rouaud","doi":"10.1109/PESC.1999.785644","DOIUrl":"https://doi.org/10.1109/PESC.1999.785644","url":null,"abstract":"Three-level neutral point clamp topology has attracted applications in medium-voltage high-power drive systems. Since the topology utilizes the neutral point voltage to achieve half bus voltage withstand of power devices and three-level output voltage delivery, it is critical to balance the neutral point voltage in occasions of disturbed or even continuous unbalance load conditions. This paper proposes a couple of balancing techniques based on space vector modulation principle and experimentally compares their effectiveness against the existing method.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134297215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.789022
J. Kikuchi, M. Manjrekar, T. Lipo
The potential of the half-controlled three-phase pulse-width modulated (PWM) boost rectifier is investigated based on theoretical analysis, simulations and experiments. The main advantages of this rectifier are: (1) a simpler and economical system compared to a full controlled PWM rectifier (reduced controlled switch count, single power supply for gate drives, and shoot-through free leg structure); and (2) better performance compared to a diode rectifier (actively controllable DC link voltage and lower input current total harmonic distortion (THD)). In particular, it is shown in this paper that the input current THD of this rectifier can be reduced by intentionally introducing a lagging power factor current command. Several issues for further performance improvement are pointed out for future work.
{"title":"Performance improvement of half controlled three phase PWM boost rectifier","authors":"J. Kikuchi, M. Manjrekar, T. Lipo","doi":"10.1109/PESC.1999.789022","DOIUrl":"https://doi.org/10.1109/PESC.1999.789022","url":null,"abstract":"The potential of the half-controlled three-phase pulse-width modulated (PWM) boost rectifier is investigated based on theoretical analysis, simulations and experiments. The main advantages of this rectifier are: (1) a simpler and economical system compared to a full controlled PWM rectifier (reduced controlled switch count, single power supply for gate drives, and shoot-through free leg structure); and (2) better performance compared to a diode rectifier (actively controllable DC link voltage and lower input current total harmonic distortion (THD)). In particular, it is shown in this paper that the input current THD of this rectifier can be reduced by intentionally introducing a lagging power factor current command. Several issues for further performance improvement are pointed out for future work.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133565980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.785601
M. Heldwein, A. F. D. Souza, Ivo Barbi
This paper presents a simple control technique applied to three-phase rectifier units with high power factor and equilibrated currents in the input. The rectifier unit is composed of three single-phase modules without neutral connection and independent power factor pre-regulation stages. In order to obtain equal power processing in each phase, the output current of each single-phase module needs only to be equal, once the output voltage is common to all of them. The same current in each module is ensured by the current mode control technique. Theoretical analysis of the control technique, along with experimental results are provided in this paper.
{"title":"A simple control strategy applied to three-phase rectifier units for telecommunication applications using single-phase rectifier modules","authors":"M. Heldwein, A. F. D. Souza, Ivo Barbi","doi":"10.1109/PESC.1999.785601","DOIUrl":"https://doi.org/10.1109/PESC.1999.785601","url":null,"abstract":"This paper presents a simple control technique applied to three-phase rectifier units with high power factor and equilibrated currents in the input. The rectifier unit is composed of three single-phase modules without neutral connection and independent power factor pre-regulation stages. In order to obtain equal power processing in each phase, the output current of each single-phase module needs only to be equal, once the output voltage is common to all of them. The same current in each module is ensured by the current mode control technique. Theoretical analysis of the control technique, along with experimental results are provided in this paper.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115199430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1999-06-27DOI: 10.1109/PESC.1999.789021
J. Pomilio, G. Spiazzi
The paper deals with line-frequency commutated rectifiers, providing compliance with IEC 1000-3-2 standards with a reduced overall reactive component size as compared to conventional rectifiers with passive L-C filters. Based on a previously presented high quality rectifier, different topological modifications are studied with the attempt to reduce the magnetic component volume and/or to improve rectifier performances. The low switching frequency accounts for reduction of losses and of electromagnetic noise emission as compared to high switching frequency rectifiers. Moreover, the switches operation results in a boost action, which compensates for the filter inductor voltage drop, thus providing output voltage stabilization against load variations.
{"title":"A low-inductance line-frequency commutated rectifier complying with IEC 1000-3-2 standards","authors":"J. Pomilio, G. Spiazzi","doi":"10.1109/PESC.1999.789021","DOIUrl":"https://doi.org/10.1109/PESC.1999.789021","url":null,"abstract":"The paper deals with line-frequency commutated rectifiers, providing compliance with IEC 1000-3-2 standards with a reduced overall reactive component size as compared to conventional rectifiers with passive L-C filters. Based on a previously presented high quality rectifier, different topological modifications are studied with the attempt to reduce the magnetic component volume and/or to improve rectifier performances. The low switching frequency accounts for reduction of losses and of electromagnetic noise emission as compared to high switching frequency rectifiers. Moreover, the switches operation results in a boost action, which compensates for the filter inductor voltage drop, thus providing output voltage stabilization against load variations.","PeriodicalId":292317,"journal":{"name":"30th Annual IEEE Power Electronics Specialists Conference. Record. (Cat. No.99CH36321)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124176023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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