Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924556
S. Han, Young-Hee Choi, Heung See Kim
This paper describes a 3.3 V low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source at LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6 MHz and a power dissipation of 1 mW with a single power supply of 3.3 V for a double poly four metal standard CMOS 0.35 /spl square/ n-well technology.
{"title":"A 4 digit CMOS quaternary to analog converter with current switch and neuron MOS down-literal circuit","authors":"S. Han, Young-Hee Choi, Heung See Kim","doi":"10.1109/ISMVL.2001.924556","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924556","url":null,"abstract":"This paper describes a 3.3 V low power 4 digit CMOS quaternary to analog converter (QAC) designed with a neuron MOS down literal circuit block and cascode current mirror source block. The neuron MOS down literal architecture allows the designed QAC to accept not only 4 level voltage inputs, but also a high speed sampling rate quaternary voltage source at LSB. Fast settling time and low power consumption of the QAC are achieved by utilizing the proposed architecture. The simulation results of the designed 4 digit QAC show a sampling rate of 6 MHz and a power dissipation of 1 mW with a single power supply of 3.3 V for a double poly four metal standard CMOS 0.35 /spl square/ n-well technology.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114490582","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924567
A. Al-Rabadi, M. Perkowski
The idea of S/D trees for binary logic is a general concept that found its main application in ESOP minimization and the generation of new diagrams and canonical forms. S/D trees demonstrated their power by generating forms that include a minimum Galois-Field-Sum-of-Products (GFSOP) circuits for binary and ternary radices. Galois field of quaternary radix has some interesting properties. An extension of the S/D trees to GF(4) is presented here. A general formula to calculate the number of inclusive forms (IFs) per variable order for an arbitrary Galois field radix and arbitrary number of variables is derived. A new fast method to count the number of IFs for an arbitrary Galois field radix and functions of two variables is introduced; the IF/sub n,2/ Triangles. This research is useful to create an efficient GFSOP minimizer for reversible logic.
{"title":"Multiple-valued Galois field S/D trees for GFSOP minimization and their complexity","authors":"A. Al-Rabadi, M. Perkowski","doi":"10.1109/ISMVL.2001.924567","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924567","url":null,"abstract":"The idea of S/D trees for binary logic is a general concept that found its main application in ESOP minimization and the generation of new diagrams and canonical forms. S/D trees demonstrated their power by generating forms that include a minimum Galois-Field-Sum-of-Products (GFSOP) circuits for binary and ternary radices. Galois field of quaternary radix has some interesting properties. An extension of the S/D trees to GF(4) is presented here. A general formula to calculate the number of inclusive forms (IFs) per variable order for an arbitrary Galois field radix and arbitrary number of variables is derived. A new fast method to count the number of IFs for an arbitrary Galois field radix and functions of two variables is introduced; the IF/sub n,2/ Triangles. This research is useful to create an efficient GFSOP minimizer for reversible logic.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123290645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924568
T. Hanyu, M. Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran
This paper presents a compact multiple-valued mask-programmable logic array (MPLA) based on a MIN/TSUM (MINimum/Truncated-SUM) two-level synthesis. A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MIN plane. Since a threshold literal can be designed by using a single floating-gate MOS transistor, a compact MIN plane can be implemented in the proposed MPLA. Any arbitrary universal-literal circuits can be realized by programming the threshold voltage of the corresponding floating-gate MOS transistor and selecting an appropriate LVC as an input variable. The performance of the proposed MPLA is evaluated under a 0.8 /spl mu/m CMOS design. It is demonstrated that its performance is superior to that of conventional PLA's.
{"title":"Multiple-valued mask-programmable logic array using one-transistor universal-literal circuits","authors":"T. Hanyu, M. Kameyama, Katsuhiko Shimabukuro, Chotei Zukeran","doi":"10.1109/ISMVL.2001.924568","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924568","url":null,"abstract":"This paper presents a compact multiple-valued mask-programmable logic array (MPLA) based on a MIN/TSUM (MINimum/Truncated-SUM) two-level synthesis. A universal literal in the MIN plane is decomposed into a threshold literal and a logic-value conversion (LVC) that is shared in the same column of the MIN plane. Since a threshold literal can be designed by using a single floating-gate MOS transistor, a compact MIN plane can be implemented in the proposed MPLA. Any arbitrary universal-literal circuits can be realized by programming the threshold voltage of the corresponding floating-gate MOS transistor and selecting an appropriate LVC as an input variable. The performance of the proposed MPLA is evaluated under a 0.8 /spl mu/m CMOS design. It is demonstrated that its performance is superior to that of conventional PLA's.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131300962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924555
I. Dhaou, E. Dubrova, H. Tenhunen
This paper investigates the use of quaternary current mode signaling to minimize the power dissipation associated with inter-module communication. We formulate a condition specifying when the insertion of the encode-decoder pair between the two modules results in a reduction of the overall power consumption of the system. An algorithm LIBCOM is developed which utilizes this condition to insert the encoder-decoder pair between the two modules only if it is advantageous. The HSPICE results obtained for 0.35 /spl mu/m CMOS process show that LIBCOM can reduce the power consumption by 15%. As technology scales down, the power saved by our algorithm can be several orders of magnitude higher.
{"title":"Power efficient inter-module communication for digit-serial DSP architectures in deep-submicron technology","authors":"I. Dhaou, E. Dubrova, H. Tenhunen","doi":"10.1109/ISMVL.2001.924555","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924555","url":null,"abstract":"This paper investigates the use of quaternary current mode signaling to minimize the power dissipation associated with inter-module communication. We formulate a condition specifying when the insertion of the encode-decoder pair between the two modules results in a reduction of the overall power consumption of the system. An algorithm LIBCOM is developed which utilizes this condition to insert the encoder-decoder pair between the two modules only if it is advantageous. The HSPICE results obtained for 0.35 /spl mu/m CMOS process show that LIBCOM can reduce the power consumption by 15%. As technology scales down, the power saved by our algorithm can be several orders of magnitude higher.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127270128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924558
F. Esteva, L. Godo
In this paper we summarize recent results, both logical and algebraic, about [0,1]-valued logical systems having a t-norm and its residuum as truth functions for conjunction and implication. We describe their axiomatic systems and their algebraic varieties, and we stress that the most general variety generated by residuated structures in [0, 1] defined by (left-continuous) t-norms is the variety of pre-linear residuated lattices.
{"title":"On complete residuated many-valued logics with t-norm conjunction","authors":"F. Esteva, L. Godo","doi":"10.1109/ISMVL.2001.924558","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924558","url":null,"abstract":"In this paper we summarize recent results, both logical and algebraic, about [0,1]-valued logical systems having a t-norm and its residuum as truth functions for conjunction and implication. We describe their axiomatic systems and their algebraic varieties, and we stress that the most general variety generated by residuated structures in [0, 1] defined by (left-continuous) t-norms is the variety of pre-linear residuated lattices.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124100941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924580
M. Hiratsuka, T. Aoki, T. Higuchi
This paper proposes an experimental model of artificial reaction-diffusion systems, which provides a foundation for constructing future massively parallel molecular computers. The key idea is to control redox-active molecules in solution, by an array of integrated microelectrodes and to realize artificially programmable reaction-diffusion dynamics in a very small amount of solution.
{"title":"A model of reaction-diffusion cellular automata for massively parallel molecular computing","authors":"M. Hiratsuka, T. Aoki, T. Higuchi","doi":"10.1109/ISMVL.2001.924580","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924580","url":null,"abstract":"This paper proposes an experimental model of artificial reaction-diffusion systems, which provides a foundation for constructing future massively parallel molecular computers. The key idea is to control redox-active molecules in solution, by an array of integrated microelectrodes and to realize artificially programmable reaction-diffusion dynamics in a very small amount of solution.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"84 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130385672","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924589
R. Stankovic, M. Stankovic, C. Moraga
In spectral interpretation, decision diagrams (DDs) are defined in terms of some spectral transforms. For a given DD, the related transform is determined by an analysis of expansion rules used in the nodes and the related labels of edges. The converse task, design of a DD in terms of a given spectral transform often requires decomposition of basic functions in spectral transform to determine the corresponding expansion rules and labels at the edges. We point out that this problem relates to the assignment of nodes in Pseudo-Kronecker DDs(PKDDs). Due to that, we generalize the definition of Haar spectral transform DDs (HSTDDs) to multiple-valued (MV) functions. Conversely, from such defined HSTDDs, we derive various Haar transforms for MV functions.
{"title":"Design of Haar wavelet transforms and Haar spectral transform decision diagrams for multiple-valued functions","authors":"R. Stankovic, M. Stankovic, C. Moraga","doi":"10.1109/ISMVL.2001.924589","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924589","url":null,"abstract":"In spectral interpretation, decision diagrams (DDs) are defined in terms of some spectral transforms. For a given DD, the related transform is determined by an analysis of expansion rules used in the nodes and the related labels of edges. The converse task, design of a DD in terms of a given spectral transform often requires decomposition of basic functions in spectral transform to determine the corresponding expansion rules and labels at the edges. We point out that this problem relates to the assignment of nodes in Pseudo-Kronecker DDs(PKDDs). Due to that, we generalize the definition of Haar spectral transform DDs (HSTDDs) to multiple-valued (MV) functions. Conversely, from such defined HSTDDs, we derive various Haar transforms for MV functions.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114731105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924585
Hajime Machida, M. Miyakawa, I. Rosenberg
An endoprimal clone is defined via a set of unary operations. It was known before that the endoprimal clone for the set O/sub 4//sup (1)/ of all unary operations on, a k-element set is the least clone J/sub k/ and that the endoprimal clone for the symmetric group S/sub k/ strictly includes J/sub k/. In this paper we consider monoids of unary operations and clones corresponding to such monoids. We define a descending sequence {N/sub i/}/sub i=1//sup k=1/ of monoids lying between O/sub k//sup (1)/ and S/sub k/, and show that the endoprimal clone for N/sub k-1/ is distinct from J/sub k/. Finally we present a characterization of the endoprimal clone for S/sub k/.
{"title":"Relations between clones and full monoids","authors":"Hajime Machida, M. Miyakawa, I. Rosenberg","doi":"10.1109/ISMVL.2001.924585","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924585","url":null,"abstract":"An endoprimal clone is defined via a set of unary operations. It was known before that the endoprimal clone for the set O/sub 4//sup (1)/ of all unary operations on, a k-element set is the least clone J/sub k/ and that the endoprimal clone for the symmetric group S/sub k/ strictly includes J/sub k/. In this paper we consider monoids of unary operations and clones corresponding to such monoids. We define a descending sequence {N/sub i/}/sub i=1//sup k=1/ of monoids lying between O/sub k//sup (1)/ and S/sub k/, and show that the endoprimal clone for N/sub k-1/ is distinct from J/sub k/. Finally we present a characterization of the endoprimal clone for S/sub k/.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126290957","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924564
Viorica Sofronie-Stokkermans
This paper gives a unified presentation of various non-classical logics. We show that a general representation theorem (which has as particular instances the representation theorems as algebras of sets for Boolean algebras, distributive lattices and semilattices) allows to establish a relationship between algebraic models and Kripke-style models, and illustrate the ideas on several examples. Based on this, we present a method for automated theorem proving by resolution for such logics. Other representation theorems, as algebras of sets or as algebras of relations, as well as relational models are also mentioned.
{"title":"Representation theorems and the semantics of (semi)lattice-based logics","authors":"Viorica Sofronie-Stokkermans","doi":"10.1109/ISMVL.2001.924564","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924564","url":null,"abstract":"This paper gives a unified presentation of various non-classical logics. We show that a general representation theorem (which has as particular instances the representation theorems as algebras of sets for Boolean algebras, distributive lattices and semilattices) allows to establish a relationship between algebraic models and Kripke-style models, and illustrate the ideas on several examples. Based on this, we present a method for automated theorem proving by resolution for such logics. Other representation theorems, as algebras of sets or as algebras of relations, as well as relational models are also mentioned.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131105509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924591
Tomoyuki Araki, M. Mukaidono, F. Yamamoto
The authors attempts to translate the vagueness of fuzzy set theory and fuzzy logic to the ambiguity of fuzzy measure by considering the fact that the Sugeno integral in fuzzy measure theory can be represented in fuzzy switching functions with constants in fuzzy logic. Then, we attempt to apply the facts clarified in fuzzy logic to fuzzy measure. We propose two new concepts: "Extended fuzzy measure" and "Kleene-Sugeno integral".
{"title":"On a Kleenean extension of fuzzy measure","authors":"Tomoyuki Araki, M. Mukaidono, F. Yamamoto","doi":"10.1109/ISMVL.2001.924591","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924591","url":null,"abstract":"The authors attempts to translate the vagueness of fuzzy set theory and fuzzy logic to the ambiguity of fuzzy measure by considering the fact that the Sugeno integral in fuzzy measure theory can be represented in fuzzy switching functions with constants in fuzzy logic. Then, we attempt to apply the facts clarified in fuzzy logic to fuzzy measure. We propose two new concepts: \"Extended fuzzy measure\" and \"Kleene-Sugeno integral\".","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"324 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133357559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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