Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924548
J. Brzozowski, Z. Ésik, Y. Iland
Hazards pulses are undesirable short pulses caused by stray delays in digital circuits. Such pulses not only may cause errors in the circuit operation, but also consume energy, and add to the computation time. It is therefore very important to detect hazards in circuit designs. Two-valued Boolean algebra, which is commonly used for the analysis and synthesis of digital circuits, cannot detect hazard conditions directly. To overcome this limitation several multi-valued algebras have been proposed for hazard detection. This paper surveys these algebras, and studies their mathematical properties. Also, some recent results unifying most of the multi-valued algebras presented in the literature are described. Our attention in this paper is restricted to the study of static and dynamic hazards in gate circuits.
{"title":"Algebras for hazard detection","authors":"J. Brzozowski, Z. Ésik, Y. Iland","doi":"10.1109/ISMVL.2001.924548","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924548","url":null,"abstract":"Hazards pulses are undesirable short pulses caused by stray delays in digital circuits. Such pulses not only may cause errors in the circuit operation, but also consume energy, and add to the computation time. It is therefore very important to detect hazards in circuit designs. Two-valued Boolean algebra, which is commonly used for the analysis and synthesis of digital circuits, cannot detect hazard conditions directly. To overcome this limitation several multi-valued algebras have been proposed for hazard detection. This paper surveys these algebras, and studies their mathematical properties. Also, some recent results unifying most of the multi-valued algebras presented in the literature are described. Our attention in this paper is restricted to the study of static and dynamic hazards in gate circuits.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133553982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924576
R. Béjar, Reiner Hähnle, F. Manyà
In this paper we first define a reduction /spl delta/ that transforms an instance /spl Gamma/ of Regular-SAT into a satisfiability equivalent instance /spl Gamma//sup /spl delta// of SAT. The reduction /spl delta/ has interesting properties: (i) the size of /spl Gamma//sup /spl delta// is linear in the size of /spl Gamma/, (ii) /spl delta/ transforms regular Horn formulas into Horn formulas, and (iii) /spl delta/ transforms regular 2-CNF formulas into 2-CNF formulas. Second, we describe a new satisfiability algorithm that determines the satisfiability of a regular 2-CNF formula /spl Gamma/ in time O(|/spl Gamma/|log|/spl Gamma/|); this algorithm is inspired by the reduction /spl delta/. Third, we introduce the concept of renamable-Horn regular CNF formula and define another reduction /spl delta/' that transforms a renamable-Horn instance /spl Gamma/ of Regular-SAT into a renamable-Horn instance /spl Gamma//sup /spl delta/'/ of SAT. We use this reduction to show that both membership and satisfiability of renamable-Horn regular CNF formulas can be decided in time O(|/spl Gamma/|log|/spl Gamma/|).
{"title":"A modular reduction of regular logic to classical logic","authors":"R. Béjar, Reiner Hähnle, F. Manyà","doi":"10.1109/ISMVL.2001.924576","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924576","url":null,"abstract":"In this paper we first define a reduction /spl delta/ that transforms an instance /spl Gamma/ of Regular-SAT into a satisfiability equivalent instance /spl Gamma//sup /spl delta// of SAT. The reduction /spl delta/ has interesting properties: (i) the size of /spl Gamma//sup /spl delta// is linear in the size of /spl Gamma/, (ii) /spl delta/ transforms regular Horn formulas into Horn formulas, and (iii) /spl delta/ transforms regular 2-CNF formulas into 2-CNF formulas. Second, we describe a new satisfiability algorithm that determines the satisfiability of a regular 2-CNF formula /spl Gamma/ in time O(|/spl Gamma/|log|/spl Gamma/|); this algorithm is inspired by the reduction /spl delta/. Third, we introduce the concept of renamable-Horn regular CNF formula and define another reduction /spl delta/' that transforms a renamable-Horn instance /spl Gamma/ of Regular-SAT into a renamable-Horn instance /spl Gamma//sup /spl delta/'/ of SAT. We use this reduction to show that both membership and satisfiability of renamable-Horn regular CNF formulas can be decided in time O(|/spl Gamma/|log|/spl Gamma/|).","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130453188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924551
M. Inaba, K. Tanno, O. Ishizuka
In this paper, realization of three fundamental functions, NOT, negated MAX and negated MIN functions, in the voltage-mode quaternary logic is presented. First, the high-performance NOT circuits with the down literal circuits are composed. The proposed NOT circuits have the quantified effect to realize high noise margins in the voltage-mode quaternary logic circuits. Next, we propose the voltage comparator with the NOT circuit, and, as applications of the voltage comparator, NMAX and NMIN circuits are designed. They can realize the negated MAX and the negated MIN functions, respectively. The advantages of these proposed circuits are fabrication with a conventional CMOS process, high noise margins of more than 0.46[V] and low power consumption with peak of less than 350[/spl mu/W] under 3.0[V] of the supply voltage in verification using HSPICE simulations.
{"title":"Realization of NMAX and NMIN functions with multi-valued voltage comparators","authors":"M. Inaba, K. Tanno, O. Ishizuka","doi":"10.1109/ISMVL.2001.924551","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924551","url":null,"abstract":"In this paper, realization of three fundamental functions, NOT, negated MAX and negated MIN functions, in the voltage-mode quaternary logic is presented. First, the high-performance NOT circuits with the down literal circuits are composed. The proposed NOT circuits have the quantified effect to realize high noise margins in the voltage-mode quaternary logic circuits. Next, we propose the voltage comparator with the NOT circuit, and, as applications of the voltage comparator, NMAX and NMIN circuits are designed. They can realize the negated MAX and the negated MIN functions, respectively. The advantages of these proposed circuits are fabrication with a conventional CMOS process, high noise margins of more than 0.46[V] and low power consumption with peak of less than 350[/spl mu/W] under 3.0[V] of the supply voltage in verification using HSPICE simulations.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121336479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924575
A. Lewandowska, P. Dziurzański, S. Yanushkevich, V. Shmerko
We propose an approach to exact detection of symmetries in multiple-valued logic (MVL) functions based on two-stage strategy. First, we reduce the search space by using information measures and then apply an exact method to find symmetry. The efficiency of the approach is evaluated by experimental study.
{"title":"Two-stage exact detection of symmetries","authors":"A. Lewandowska, P. Dziurzański, S. Yanushkevich, V. Shmerko","doi":"10.1109/ISMVL.2001.924575","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924575","url":null,"abstract":"We propose an approach to exact detection of symmetries in multiple-valued logic (MVL) functions based on two-stage strategy. First, we reduce the search space by using information measures and then apply an exact method to find symmetry. The efficiency of the approach is evaluated by experimental study.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117092274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924587
Frank Schmiedle, Wolfgang Günther, R. Drechsler
Multi-valued decision diagrams (MDDs) are a generalization of binary decision diagrams (BDDs). They are suitable for several applications in synthesis and verification of integrated circuits since often, functions with multi-valued input variables can be represented efficiently by MDDs. Their sizes counted in number of nodes vary from linear to exponential dependent on the variable ordering used. Therefore sifting, i.e. dynamic variable re-ordering, has to be applied frequently while an MDD is built in order to keep the number of nodes needed during the process small. Often most of the runtime for MDD construction is spent for sifting. We present a new method that speeds up MDD construction and also reduces memory consumption. It is based on the selection of re-ordering heuristics dependent on the history of the construction process. Success of previous re-ordering steps as well as the frequency of sifting calls in the past are used to determine a variation of sifting that is applied next. Experimental results are given to demonstrate that runtimes and memory consumption can be reduced by 30% on average when the proposed selection methods are used during MDD construction.
{"title":"Selection of efficient re-ordering heuristics for MDD construction","authors":"Frank Schmiedle, Wolfgang Günther, R. Drechsler","doi":"10.1109/ISMVL.2001.924587","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924587","url":null,"abstract":"Multi-valued decision diagrams (MDDs) are a generalization of binary decision diagrams (BDDs). They are suitable for several applications in synthesis and verification of integrated circuits since often, functions with multi-valued input variables can be represented efficiently by MDDs. Their sizes counted in number of nodes vary from linear to exponential dependent on the variable ordering used. Therefore sifting, i.e. dynamic variable re-ordering, has to be applied frequently while an MDD is built in order to keep the number of nodes needed during the process small. Often most of the runtime for MDD construction is spent for sifting. We present a new method that speeds up MDD construction and also reduces memory consumption. It is based on the selection of re-ordering heuristics dependent on the history of the construction process. Success of previous re-ordering steps as well as the frequency of sifting calls in the past are used to determine a variation of sifting that is applied next. Experimental results are given to demonstrate that runtimes and memory consumption can be reduced by 30% on average when the proposed selection methods are used during MDD construction.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115349712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924566
Z. Stachniak
This paper surveys some polarity-based knowledge representational and automated reasoning techniques in the domain of many-valued logics.
本文研究了多值逻辑领域中基于极性的知识表示和自动推理技术。
{"title":"Exploiting polarity in multiple-valued inference systems","authors":"Z. Stachniak","doi":"10.1109/ISMVL.2001.924566","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924566","url":null,"abstract":"This paper surveys some polarity-based knowledge representational and automated reasoning techniques in the domain of many-valued logics.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131380270","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924553
M. Karpovsky, R. Stankovic, C. Moraga
This paper presents a tutorial review of spectral methods in switching and multiple-valued logic theory and the design of digital system in the last decade. The paper continues review work in this area done by the authors in 1981 and 1991.
{"title":"Spectral techniques in binary and multiple-valued switching theory. A review of results in the decade 1991-2000","authors":"M. Karpovsky, R. Stankovic, C. Moraga","doi":"10.1109/ISMVL.2001.924553","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924553","url":null,"abstract":"This paper presents a tutorial review of spectral methods in switching and multiple-valued logic theory and the design of digital system in the last decade. The paper continues review work in this area done by the authors in 1981 and 1991.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122893710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924579
T. Hanyu
A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass-transistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.
{"title":"Challenge of a multiple-valued technology in recent deep-submicron VLSI","authors":"T. Hanyu","doi":"10.1109/ISMVL.2001.924579","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924579","url":null,"abstract":"A logic-in-memory VLSI architecture based on multiple-valued floating-gate MOS pass-transistor logic is proposed to solve a communication bottleneck between modules in the recent deep-submicron VLSI. Moreover, a multiple-valued current-mode circuit based on dual-rail differential logic is also proposed as a candidate suitable for self-checking and asynchronous VLSI systems. Finally, the advantage of the above multiple-valued circuit technologies is shown by using design examples.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124398253","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924596
S. Aguzzoli, D. Mundici
The logic /spl exist/L of continuous piecewise linear functions with rational coefficients has enough expressive power to formalize Weierstrass approximation theorem. Thus, up to any prescribed error; every continuous (control) function can be approximated by a formula of /spl exist/L. As shown in this paper, /spl exist/L is just infinite-valued Lukasiewicz propositional logic with one quantified propositional variable. We evaluate the computational complexity of the decision problem for /spl exist/L. Enough background material is provided for all readers wishing to acquire a deeper understanding of the rapidly growing literature on Lukasiewicz propositional logic and its applications.
{"title":"Weierstrass approximations by Lukasiewicz formulas with one quantified variable","authors":"S. Aguzzoli, D. Mundici","doi":"10.1109/ISMVL.2001.924596","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924596","url":null,"abstract":"The logic /spl exist/L of continuous piecewise linear functions with rational coefficients has enough expressive power to formalize Weierstrass approximation theorem. Thus, up to any prescribed error; every continuous (control) function can be approximated by a formula of /spl exist/L. As shown in this paper, /spl exist/L is just infinite-valued Lukasiewicz propositional logic with one quantified propositional variable. We evaluate the computational complexity of the decision problem for /spl exist/L. Enough background material is provided for all readers wishing to acquire a deeper understanding of the rapidly growing literature on Lukasiewicz propositional logic and its applications.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116804451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924550
T. Ike, T. Hanyu, M. Kameyama
A new current mirror with a biasing current source is proposed for high-performance arithmetic VLSI systems. The delay for the current mirror is inversely proportional to the input current. The use of a biasing current source makes the input current of the current mirror increased, which results in smaller switching delay. As a typical example of the proposed dual-rail multiple-valued current mode (MVCM) circuit, a radix-2 signed-digit full adder is designed by using a 0.35-/spl mu/m CMOS technology. Its performance is superior to that of corresponding MVCM circuits without biasing current sources.
{"title":"Dual-rail multiple-valued current-mode VLSI with biasing current sources","authors":"T. Ike, T. Hanyu, M. Kameyama","doi":"10.1109/ISMVL.2001.924550","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924550","url":null,"abstract":"A new current mirror with a biasing current source is proposed for high-performance arithmetic VLSI systems. The delay for the current mirror is inversely proportional to the input current. The use of a biasing current source makes the input current of the current mirror increased, which results in smaller switching delay. As a typical example of the proposed dual-rail multiple-valued current mode (MVCM) circuit, a radix-2 signed-digit full adder is designed by using a 0.35-/spl mu/m CMOS technology. Its performance is superior to that of corresponding MVCM circuits without biasing current sources.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115699187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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