Pub Date : 2015-08-01DOI: 10.7763/IJCTE.2015.V7.977
T. Sasamal, Ashutosh Kumar Singh, A. Mohan
Reversible logic is one of the basis of future computing system that promises zero energy dissipation. It has applications in various fields such as Low power VLSI, Fault tolerant designs, quantum computing, nanotechnology, DN A computing, optical computing, cryptography and informatics. To make reversible logic circuits reliable, they must incorporate fault tolerance attribute. In this paper, we propose a new parity preserving reversible logic gate. We have proposed two optimized design of a self checking two rail checker circuit based on proposed parity preserving reversible logic gate in terms of number of gates and critical path delay. The proposed design achieves less critical delay and gates compared to the existing designs available in literature. Index Terms—Critical delay, fault tolerant, parity- preserving reversible gates, two rail checker.
{"title":"Design of Two-Rail Checker Using a New Parity Preserving Reversible Logic Gate","authors":"T. Sasamal, Ashutosh Kumar Singh, A. Mohan","doi":"10.7763/IJCTE.2015.V7.977","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.977","url":null,"abstract":"Reversible logic is one of the basis of future computing system that promises zero energy dissipation. It has applications in various fields such as Low power VLSI, Fault tolerant designs, quantum computing, nanotechnology, DN A computing, optical computing, cryptography and informatics. To make reversible logic circuits reliable, they must incorporate fault tolerance attribute. In this paper, we propose a new parity preserving reversible logic gate. We have proposed two optimized design of a self checking two rail checker circuit based on proposed parity preserving reversible logic gate in terms of number of gates and critical path delay. The proposed design achieves less critical delay and gates compared to the existing designs available in literature. Index Terms—Critical delay, fault tolerant, parity- preserving reversible gates, two rail checker.","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116447517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.7763/IJCTE.2015.V7.980
Edgar Serna M., Alexei Serna A.
Abstract—It is accepted widely that the work performed by the engineers fundamentally consists in detecting, identifying and solving problems, but most of the educational systems and related subjects seem to ignore the need of educating students for the development of logical reasoning in order they can properly perform this function. This article reviews the concepts of logic, abstraction, problem solving and logical reasoning, which are described and analyzed like a functional need for engineering and its professional application, by considering the requirements of today's Information and Knowledge Society, and making a relation fitted to the educational processes of current and future engineers.
{"title":"Knowledge in Engineering: A View from the Logical Reasoning","authors":"Edgar Serna M., Alexei Serna A.","doi":"10.7763/IJCTE.2015.V7.980","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.980","url":null,"abstract":" Abstract—It is accepted widely that the work performed by the engineers fundamentally consists in detecting, identifying and solving problems, but most of the educational systems and related subjects seem to ignore the need of educating students for the development of logical reasoning in order they can properly perform this function. This article reviews the concepts of logic, abstraction, problem solving and logical reasoning, which are described and analyzed like a functional need for engineering and its professional application, by considering the requirements of today's Information and Knowledge Society, and making a relation fitted to the educational processes of current and future engineers.","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126251374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-08-01DOI: 10.7763/IJCTE.2015.V7.978
Oranuch Pantho, M. Tiantong
Currently, e-learning systems are becoming more popular. This is because e-learning systems provide learners freedom to study with unlimited time and at any location. But, most of the e-learning systems present the same learning content without regard to different learning styles of learners. Many learners have to adapt to different learning styles such as learning content from images which is not specifically targeted at their needs. Meanwhile, other learners may have aptitude in reading or from listening, etc. Therefore, learning and teaching processes are important issues that teachers need to adjust their teaching according to individual learners. If each learner obtains content that aligns with their own learning style, it will lead to more achievement. The purpose of this research is to synthesize the learning model of adaptive e-learning and e-mentoring system in order to recommend learners and analyze the VARK learning style (VARK is an acronym for visual, aural, read/write, and kinesthetic) by using data mining methodology. The synthesized model consists of four modules which are 1) esaB eluR KRAV eludoM2) VARK Learner Module 3) Content Module and 4) Learning Module.
{"title":"Conceptual Framework of a Synthesized Adaptive e-Learning and e-Mentoring System Using VARK Learning Styles with Data Mining Methodology","authors":"Oranuch Pantho, M. Tiantong","doi":"10.7763/IJCTE.2015.V7.978","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.978","url":null,"abstract":"Currently, e-learning systems are becoming more popular. This is because e-learning systems provide learners freedom to study with unlimited time and at any location. But, most of the e-learning systems present the same learning content without regard to different learning styles of learners. Many learners have to adapt to different learning styles such as learning content from images which is not specifically targeted at their needs. Meanwhile, other learners may have aptitude in reading or from listening, etc. Therefore, learning and teaching processes are important issues that teachers need to adjust their teaching according to individual learners. If each learner obtains content that aligns with their own learning style, it will lead to more achievement. The purpose of this research is to synthesize the learning model of adaptive e-learning and e-mentoring system in order to recommend learners and analyze the VARK learning style (VARK is an acronym for visual, aural, read/write, and kinesthetic) by using data mining methodology. The synthesized model consists of four modules which are 1) esaB eluR KRAV eludoM2) VARK Learner Module 3) Content Module and 4) Learning Module.","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132241170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-07-01DOI: 10.7763/IJCTE.2015.V7.948
K. Kulathilake, L. Ranathunga, G. Constantine, N. A. Abdullah
Abstract—The Coronary Cineangiogram (CCA) is an invasive medical image modality which is used to determine the stenosis in the Coronary Arteries. The global motion occurring due to the heart beat makes great disturbance to obtain the visual alignment among the vessel structure shown in the CCA frames. Therefore, the recorded vessel structure's position in CCA varies within the frame sequence. This paper describes a hierarchical region based template matching technique to reconstruct the CCA by reducing the global motion artifacts. This proposed motion reduction technique is efficient and it reconstructs the CCA by reducing the background motion as desired. Experimental results of this method have shown its' ability to maintain the visual alignment of the internal blood flow among the frames.
{"title":"Hierarchical Region Based Template Matching Technique for Global Motion Reduction of Coronary Cineangiograms","authors":"K. Kulathilake, L. Ranathunga, G. Constantine, N. A. Abdullah","doi":"10.7763/IJCTE.2015.V7.948","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.948","url":null,"abstract":" Abstract—The Coronary Cineangiogram (CCA) is an invasive medical image modality which is used to determine the stenosis in the Coronary Arteries. The global motion occurring due to the heart beat makes great disturbance to obtain the visual alignment among the vessel structure shown in the CCA frames. Therefore, the recorded vessel structure's position in CCA varies within the frame sequence. This paper describes a hierarchical region based template matching technique to reconstruct the CCA by reducing the global motion artifacts. This proposed motion reduction technique is efficient and it reconstructs the CCA by reducing the background motion as desired. Experimental results of this method have shown its' ability to maintain the visual alignment of the internal blood flow among the frames.","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126758995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-01DOI: 10.7763/IJCTE.2015.V7.951
N. Raj, Ashutosh Kumar Singh, Anil Kumar, Gupta
{"title":"Low Power Circuit Design Techniques: A Survey","authors":"N. Raj, Ashutosh Kumar Singh, Anil Kumar, Gupta","doi":"10.7763/IJCTE.2015.V7.951","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.951","url":null,"abstract":"","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121626602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-01DOI: 10.7763/IJCTE.2015.V7.952
L. F. Rahman, M. Reaz, M. Marufuzzaman
A non-overlapping clock (NOC) generator circuit is designed for the successful operation of high voltage generator (HVG) implementation in low-power applications like radio frequency identification (RFID) tag EEPROM. The NOC generator has been implemented in 0.18 μm CMOS process. The designed NOC can generate two stable anti-phase clock signals as output, which is used in charge pump (CP) circuit with low power dissipation. The NOC generator required lower power dissipation with 359.87 nW under power supply voltage (VDD) 1.8 V. Moreover, this designed NOC generator produced faster clock signals with 0.972 μS as the settling time.
{"title":"Design of a Non-Overlapping Clock Generator for RFID Transponder EEPROM","authors":"L. F. Rahman, M. Reaz, M. Marufuzzaman","doi":"10.7763/IJCTE.2015.V7.952","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.952","url":null,"abstract":"A non-overlapping clock (NOC) generator circuit is designed for the successful operation of high voltage generator (HVG) implementation in low-power applications like radio frequency identification (RFID) tag EEPROM. The NOC generator has been implemented in 0.18 μm CMOS process. The designed NOC can generate two stable anti-phase clock signals as output, which is used in charge pump (CP) circuit with low power dissipation. The NOC generator required lower power dissipation with 359.87 nW under power supply voltage (VDD) 1.8 V. Moreover, this designed NOC generator produced faster clock signals with 0.972 μS as the settling time.","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123353347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-01DOI: 10.7763/IJCTE.2015.V7.959
N. Laloo, M. Z. A. A. Aungnoo, M. S. Sunhaloo
{"title":"Adapting Distance Based Clustering Concept to a Heterogeneous Network","authors":"N. Laloo, M. Z. A. A. Aungnoo, M. S. Sunhaloo","doi":"10.7763/IJCTE.2015.V7.959","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.959","url":null,"abstract":"","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121002191","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-01DOI: 10.7763/IJCTE.2015.V7.955
Ali Hassan, S. Lambert-Lacroix, F. Pasqualini
—In this paper, we propose a real-time fault detection system for the semiconductor domain, which aims to detect abnormal wafers from a recent history of electrical measurements. It is based on a dynamic model which uses our filter method as feature selection approach, and one-class support vector machines algorithm for classification task. The dynamicity of the model is ensured by updating the database through a temporal moving window. Two scenarios for updating the moving window are proposed. In order to prove the efficiency of our system, we compare it to an alternative detection system based on the Hotelling's T 2 test. Experiments are conducted on two real-world semiconductor datasets. Results show that our system outperforms the alternative system, and can provide an efficient way for real-time fault detection.
在本文中，我们提出了一个半导体领域的实时故障检测系统，旨在从最近的电气测量历史中检测异常晶圆。它是基于一个动态模型，使用我们的滤波方法作为特征选择方法，用一类支持向量机算法进行分类任务。通过实时移动窗口更新数据库，保证了模型的动态性。提出了两种更新移动窗口的方案。为了证明系统的有效性，我们将其与基于Hotelling’s T 2检验的替代检测系统进行了比较。实验在两个真实的半导体数据集上进行。结果表明，该系统优于备选系统，可以为实时故障检测提供有效的方法。
{"title":"Real-Time Fault Detection in Semiconductor Using One-Class Support Vector Machines","authors":"Ali Hassan, S. Lambert-Lacroix, F. Pasqualini","doi":"10.7763/IJCTE.2015.V7.955","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.955","url":null,"abstract":"—In this paper, we propose a real-time fault detection system for the semiconductor domain, which aims to detect abnormal wafers from a recent history of electrical measurements. It is based on a dynamic model which uses our filter method as feature selection approach, and one-class support vector machines algorithm for classification task. The dynamicity of the model is ensured by updating the database through a temporal moving window. Two scenarios for updating the moving window are proposed. In order to prove the efficiency of our system, we compare it to an alternative detection system based on the Hotelling's T 2 test. Experiments are conducted on two real-world semiconductor datasets. Results show that our system outperforms the alternative system, and can provide an efficient way for real-time fault detection.","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115385784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-01DOI: 10.7763/IJCTE.2015.V7.965
A. Alenezi, Muhammad Salim Javed Gandapur, A. Javed, M. Demba
The Ministry of Higher Education invests a significant sum of amounts in projects of the higher learning institutions but the success rate is still limited. Majority project continues to fail in achieving their objectives even with a good resource of project management and ultimately get scrapped. The main goal of this study is identification of project failure factors by an examination of higher learning institutional projects. The data were collected from projects of higher learning institutions of Saudi Arabia by conducting interview and distribution of structured questionnaire among project managers. The result showed that procedure for processing of project approval and release of funds has an unfavorable impact on the development project such as poor control, delayed project implementation, and checking system etc. In the same way, when projects are designed to poorly be short of the major characteristics of planning such as objectivity, feasibility, appraisal and detail cost forecasting. Therefore the project deficient a quality management system and bring about the main reasons for project failure. The solution requires a method to evaluate and identify the various significant factors that causes project failure and their mutual association. The validation of the conceptual solution has led to the conclusion that a systematic and holistic approach would improve the overall success rates of project and a project manager would be notified of problems during all phases of project life cycle.
{"title":"Significant Failure Factor of Higher Learning Institution Projects","authors":"A. Alenezi, Muhammad Salim Javed Gandapur, A. Javed, M. Demba","doi":"10.7763/IJCTE.2015.V7.965","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.965","url":null,"abstract":"The Ministry of Higher Education invests a significant sum of amounts in projects of the higher learning institutions but the success rate is still limited. Majority project continues to fail in achieving their objectives even with a good resource of project management and ultimately get scrapped. The main goal of this study is identification of project failure factors by an examination of higher learning institutional projects. The data were collected from projects of higher learning institutions of Saudi Arabia by conducting interview and distribution of structured questionnaire among project managers. The result showed that procedure for processing of project approval and release of funds has an unfavorable impact on the development project such as poor control, delayed project implementation, and checking system etc. In the same way, when projects are designed to poorly be short of the major characteristics of planning such as objectivity, feasibility, appraisal and detail cost forecasting. Therefore the project deficient a quality management system and bring about the main reasons for project failure. The solution requires a method to evaluate and identify the various significant factors that causes project failure and their mutual association. The validation of the conceptual solution has led to the conclusion that a systematic and holistic approach would improve the overall success rates of project and a project manager would be notified of problems during all phases of project life cycle.","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127290042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-01DOI: 10.7763/IJCTE.2015.V7.964
Afzaal H. Seyal, Yeo Sy Mey, Mardiyah Hj Matusin, Hjh Norzainah Hj Siau, A. A. Rahman
{"title":"Understanding Students Learning Style and Their Performance in Computer Programming Course: Evidence from Bruneian Technical Institution of Higher Learning","authors":"Afzaal H. Seyal, Yeo Sy Mey, Mardiyah Hj Matusin, Hjh Norzainah Hj Siau, A. A. Rahman","doi":"10.7763/IJCTE.2015.V7.964","DOIUrl":"https://doi.org/10.7763/IJCTE.2015.V7.964","url":null,"abstract":"","PeriodicalId":306280,"journal":{"name":"International Journal of Computer Theory and Engineering","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125972676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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