Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203867
A. Pouydebasque, B. Dumont, F. Wacquant, A. Halimaoui, C. Laviron, D. Lenoble, R. El-Farhane, B. Duriez, F. Arnaud, V. Carron, C. Rossato, S. Pokrant, F. Salvetti, A. Dray, F. Boeuf, T. Skotnicki
This paper demonstrates that, for NMOS, the use of LSA and smart junction engineering enable to improve dramatically short channel effects (-65% in DIBL at L/sub g/=45 nm due to lower X/sub j/ and DL) and I/sub on//I/sub off/ performance (+7% I/sub on/ at I/sub off/=100 nA//spl mu/m due to steeper sub-threshold slope and reduced poly-depletion) compared to spike annealed N-MOSFETs. These results show the potential advantage of ultra-high temperature and non diffusive annealing such as LSA that may be necessary for the 45 nm technology and below.
{"title":"NMOS-junction integration study with ultra-high temperature non-diffusive laser annealing for the 45 nm node and below","authors":"A. Pouydebasque, B. Dumont, F. Wacquant, A. Halimaoui, C. Laviron, D. Lenoble, R. El-Farhane, B. Duriez, F. Arnaud, V. Carron, C. Rossato, S. Pokrant, F. Salvetti, A. Dray, F. Boeuf, T. Skotnicki","doi":"10.1109/IWJT.2005.203867","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203867","url":null,"abstract":"This paper demonstrates that, for NMOS, the use of LSA and smart junction engineering enable to improve dramatically short channel effects (-65% in DIBL at L/sub g/=45 nm due to lower X/sub j/ and DL) and I/sub on//I/sub off/ performance (+7% I/sub on/ at I/sub off/=100 nA//spl mu/m due to steeper sub-threshold slope and reduced poly-depletion) compared to spike annealed N-MOSFETs. These results show the potential advantage of ultra-high temperature and non diffusive annealing such as LSA that may be necessary for the 45 nm technology and below.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131349291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203866
N. Sugii, J. Morioka, Y. Ishidoya, K. Koyama, T. Inada
In this paper the properties of ion-implanted strained-silicon/SiGe heterostructures are investigated. The strained-silicon layers were completely re-crystallized by rapid-thermal annealing at 900/spl deg/C or higher. Arsenic diffusivity was identical in strained and unstrained silicon but was higher than both of these in SiGe. Boron diffusivity in SiGe was lower than that in silicon. Electron mobility was greater by about 20-30% in strained silicon than in silicon and lower by about 20-30% in Si/sub 0.7/Ge/sub 0.3/ than in silicon. Hole mobility was greater by about 30-40% in strained silicon than in silicon and lower by about 5-8% in Si/sub 0.7/Ge/sub 0.3/ than in silicon. Parasitic resistance in the source/drain region can be decreased if the region consists mostly of strained silicon.
{"title":"Properties of ion-implanted strained-Si/SiGe heterostructures","authors":"N. Sugii, J. Morioka, Y. Ishidoya, K. Koyama, T. Inada","doi":"10.1109/IWJT.2005.203866","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203866","url":null,"abstract":"In this paper the properties of ion-implanted strained-silicon/SiGe heterostructures are investigated. The strained-silicon layers were completely re-crystallized by rapid-thermal annealing at 900/spl deg/C or higher. Arsenic diffusivity was identical in strained and unstrained silicon but was higher than both of these in SiGe. Boron diffusivity in SiGe was lower than that in silicon. Electron mobility was greater by about 20-30% in strained silicon than in silicon and lower by about 20-30% in Si/sub 0.7/Ge/sub 0.3/ than in silicon. Hole mobility was greater by about 30-40% in strained silicon than in silicon and lower by about 5-8% in Si/sub 0.7/Ge/sub 0.3/ than in silicon. Parasitic resistance in the source/drain region can be decreased if the region consists mostly of strained silicon.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114634517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203879
J. Nxumalo, C. Wintgens, R. Haythornthwaite, V. Ho
This article presents the results of a 2D carrier profile analysis of a finished 90 nm MPU with strained silicon by scanning capacitance microscopy (SCM). First, we show that the carrier concentration measurement dynamic range of SCM spans 10/sup 14/-10/sup 20/ cm/sup -3/. Then we present results that demonstrate p-n junction delineation on PMOS transistor with embedded SiGe in the source/drain regions. A big difference of carrier concentration in SiGe with respect to the surrounding silicon tends to indicate that in-situ boron doping was employed during SiGe S/D growth. We also report observed anomalous lateral "overgrowth" of SiGe over field oxide that may compromise manufacturing yield.
{"title":"2D carrier mapping in Si/sub 1-x/Ge/sub x/ source/drain regions of PMOSFETs used in a production device by scanning capacitance microscopy","authors":"J. Nxumalo, C. Wintgens, R. Haythornthwaite, V. Ho","doi":"10.1109/IWJT.2005.203879","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203879","url":null,"abstract":"This article presents the results of a 2D carrier profile analysis of a finished 90 nm MPU with strained silicon by scanning capacitance microscopy (SCM). First, we show that the carrier concentration measurement dynamic range of SCM spans 10/sup 14/-10/sup 20/ cm/sup -3/. Then we present results that demonstrate p-n junction delineation on PMOS transistor with embedded SiGe in the source/drain regions. A big difference of carrier concentration in SiGe with respect to the surrounding silicon tends to indicate that in-situ boron doping was employed during SiGe S/D growth. We also report observed anomalous lateral \"overgrowth\" of SiGe over field oxide that may compromise manufacturing yield.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"11 16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123693468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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