Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203886
I. Aiba, Y. Sasaki, K. Okashita, H. Tamura, Y. Fukagawa, K. Tsutsui, H. Ito, K. Kakushima, B. Mizuno, H. Iwai
Plasma doping is one of the candidates of the impurity doping processes to form shallow junction. Although the PD is a highly efficient doping process, it would be useful to establish a proper wet cleaning method that follows the PD processes so that the PD can be used in the conventional semiconductor fabrication flow. The effects of the photo-resist masks are examined in conjunction with the PD processes including the retained dose after the removal of the photo-resist using the ashing.
{"title":"Feasibility study of plasma doping on Si substrates with photo-resist patterns","authors":"I. Aiba, Y. Sasaki, K. Okashita, H. Tamura, Y. Fukagawa, K. Tsutsui, H. Ito, K. Kakushima, B. Mizuno, H. Iwai","doi":"10.1109/IWJT.2005.203886","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203886","url":null,"abstract":"Plasma doping is one of the candidates of the impurity doping processes to form shallow junction. Although the PD is a highly efficient doping process, it would be useful to establish a proper wet cleaning method that follows the PD processes so that the PD can be used in the conventional semiconductor fabrication flow. The effects of the photo-resist masks are examined in conjunction with the PD processes including the retained dose after the removal of the photo-resist using the ashing.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127436950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203889
G. Ru, Yu-Long Jiang, X. Qu, Bingzong Li
The effects of oxygen in metal, Ti capping and heating ramp rate on Ni-silicide formation and Ni-silicide/Si interface have been studied. The oxygen in Ni film results in high resistivity of Ni-silicide film, poor thermal stability, and poor electrical interface. Ti-capped silicidation can scavenge oxygen onto the silicide surface and results in comparable low resistivity, high thermal stability Ni-silicide film as that formed by oxygen-free deposition. The temperature-dependent current-voltage measurement of the Ni-silicide Schottky barrier diodes (SBD) with and without Ti capping reveals that both contacts have strip-like inhomogeneity and the inhomogeneity is larger for the SBD without Ti capping. Different heating ramp rate in Ni-silicidation has almost no effect on Ni-silicide film itself. But the electrical quality of Ni-silicide/Si interface is significantly influenced by the ramp rate. High ramp-rate (24/spl deg/C) heating gives rise to a poor Ni-silicide/Si interface, compared to low ramp-rate (12/spl deg/C) heating.
{"title":"Ti-capping and heating ramp-rate effects on Ni-silicide film and interface","authors":"G. Ru, Yu-Long Jiang, X. Qu, Bingzong Li","doi":"10.1109/IWJT.2005.203889","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203889","url":null,"abstract":"The effects of oxygen in metal, Ti capping and heating ramp rate on Ni-silicide formation and Ni-silicide/Si interface have been studied. The oxygen in Ni film results in high resistivity of Ni-silicide film, poor thermal stability, and poor electrical interface. Ti-capped silicidation can scavenge oxygen onto the silicide surface and results in comparable low resistivity, high thermal stability Ni-silicide film as that formed by oxygen-free deposition. The temperature-dependent current-voltage measurement of the Ni-silicide Schottky barrier diodes (SBD) with and without Ti capping reveals that both contacts have strip-like inhomogeneity and the inhomogeneity is larger for the SBD without Ti capping. Different heating ramp rate in Ni-silicidation has almost no effect on Ni-silicide film itself. But the electrical quality of Ni-silicide/Si interface is significantly influenced by the ramp rate. High ramp-rate (24/spl deg/C) heating gives rise to a poor Ni-silicide/Si interface, compared to low ramp-rate (12/spl deg/C) heating.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132883936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203875
K. Hosawa, K. Matsumoto, K. Shibahara
In this paper, the As and Sb dopant profiles in Ge introduced by ion implantation was evaluated. Profiles for medium dose implantation without amorphizing did not have severe discrepancy between simulated profiles. High dose implantation gave rise to unexpected deep penetration of the dopant. This probably originates from oxidation of the surface amorphized layer.
本文对离子注入法在 Ge 中引入的砷和锑掺杂剖面进行了评估。中等剂量植入而未发生非晶化的剖面与模拟剖面没有严重差异。高剂量植入会导致掺杂剂意外的深度渗透。这可能源于表面非晶化层的氧化。
{"title":"Anomalous doping profile in heavily doped Ge","authors":"K. Hosawa, K. Matsumoto, K. Shibahara","doi":"10.1109/IWJT.2005.203875","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203875","url":null,"abstract":"In this paper, the As and Sb dopant profiles in Ge introduced by ion implantation was evaluated. Profiles for medium dose implantation without amorphizing did not have severe discrepancy between simulated profiles. High dose implantation gave rise to unexpected deep penetration of the dopant. This probably originates from oxidation of the surface amorphized layer.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203887
K. Tsutsui, K. Majima, Y. Fukagawa, Y. Sasaki, K. Okashita, H. Tamura, K. Kakushima, H. Ito, B. Mizuno, H. Iwai
In this work, the shallow B doped layers formed by plasma doping and activation process using spike-RTA or flash lamp annealing (FLA) were characterized by Hall measurement, and carrier mobility and activation rate in these layers are evaluated in conjunction with doping method and activation process.
{"title":"Analysis of conductivity in ultra-shallow p/sup +/ layers formed by plasma doping","authors":"K. Tsutsui, K. Majima, Y. Fukagawa, Y. Sasaki, K. Okashita, H. Tamura, K. Kakushima, H. Ito, B. Mizuno, H. Iwai","doi":"10.1109/IWJT.2005.203887","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203887","url":null,"abstract":"In this work, the shallow B doped layers formed by plasma doping and activation process using spike-RTA or flash lamp annealing (FLA) were characterized by Hall measurement, and carrier mobility and activation rate in these layers are evaluated in conjunction with doping method and activation process.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130335063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203877
R. Hillard, J. Borland, M. Benjamin
This paper describes newly developed techniques to accurately measure the 4pp sheet resistance without the influences of probe penetration. Also, the electrically active surface dopant density (NSURF) is measured directly with a single non-penetrating, non-damaging and non-contaminating EM-probe. There are two types of EM-probes available; one for capacitance-voltage (CV) applications and the other for current-voltage (IV) applications. It was found that the EM-probe 4pp could measure source-drain extensions (SDE) structures and p/n ultra-shallow junction (USJ) structures. Conventional 4pp were found to be limited to about 30 to 40 nm and deeper. Variations in dose and sheet resistance reveal valuable information about the ion implantation and annealing processes which seems to be a powerful characterization tool.
{"title":"Ultra low energy (ULE) implant dose and activation monitoring","authors":"R. Hillard, J. Borland, M. Benjamin","doi":"10.1109/IWJT.2005.203877","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203877","url":null,"abstract":"This paper describes newly developed techniques to accurately measure the 4pp sheet resistance without the influences of probe penetration. Also, the electrically active surface dopant density (NSURF) is measured directly with a single non-penetrating, non-damaging and non-contaminating EM-probe. There are two types of EM-probes available; one for capacitance-voltage (CV) applications and the other for current-voltage (IV) applications. It was found that the EM-probe 4pp could measure source-drain extensions (SDE) structures and p/n ultra-shallow junction (USJ) structures. Conventional 4pp were found to be limited to about 30 to 40 nm and deeper. Variations in dose and sheet resistance reveal valuable information about the ion implantation and annealing processes which seems to be a powerful characterization tool.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124239981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203873
T. Yamashita, T. Hayashi, Y. Nishida, Y. Kawasaki, T. Kuroi, H. Oda, T. Eimori, Y. Ohji
Boron doping using gas cluster ion beam (GCIB) is implemented for formation of source/drain-extension (SDE) of pMOSFETs with sub-50-nm gate length. As compared with low energy ion implantation, GCIB is confirmed to produce steep profile of /spl sim/2.5 nm/decade without tail distribution. By simple replacement of low energy boron implantation with GCIB doping, about 20-nm improvement in short-channel effect and almost the same current drivability are obtained for pMOSFETs. Considering that conventional spike RTA and no offset space were used in the fabrication process, GCIB doping is considered to be promising technology for 45-nm node and beyond.
{"title":"Formation of S/D-extension using boron gas cluster ion beam doping for sub-50-nm PMOSFET","authors":"T. Yamashita, T. Hayashi, Y. Nishida, Y. Kawasaki, T. Kuroi, H. Oda, T. Eimori, Y. Ohji","doi":"10.1109/IWJT.2005.203873","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203873","url":null,"abstract":"Boron doping using gas cluster ion beam (GCIB) is implemented for formation of source/drain-extension (SDE) of pMOSFETs with sub-50-nm gate length. As compared with low energy ion implantation, GCIB is confirmed to produce steep profile of /spl sim/2.5 nm/decade without tail distribution. By simple replacement of low energy boron implantation with GCIB doping, about 20-nm improvement in short-channel effect and almost the same current drivability are obtained for pMOSFETs. Considering that conventional spike RTA and no offset space were used in the fabrication process, GCIB doping is considered to be promising technology for 45-nm node and beyond.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131304216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203872
M. Ishibashi, Y. Kawasaki, K. Horita, T. Kuroi, T. Yamashita, K. Shiga, T. Hayashi, M. Togawa, T. Eimori, Y. Ohji
In this paper, the impact of cluster ion (B/sub 18/H/sub x//sup +/) implantation on SDE formation are investigated in detail. It has been shown that B/sub 18/H/sub x//sup +/ ion implantation not only can make ultra-shallow junction for 45 nm node and beyond and but also has self-amorphization property and can reduce the channeling tail in the boron distribution without pre-amorphization implantation. In addition, B/sub 18/H/sub x//sup +/ ion implantation can be expected to reduce a fluctuation of MOSFETs, compared with B/sup +/ implantation. Cluster implantation is the reliability issue by hydrogen atom, because a large amount of hydrogen atoms are simultaneously introduced with boron into the silicon substrate. Moreover, neither the increase of junction leakage current nor influences of hydrogen which is introduced during B/sub 18/H/sub x//sup +/ implantation on PMOS reliability does not occur. The amorphization effect are evaluated by TEM observation and boron and hydrogen profiles by SIMS analysis.
{"title":"Advantages of B/sub 18/H/sub 22/ ion implantation and influence on PMOS reliability","authors":"M. Ishibashi, Y. Kawasaki, K. Horita, T. Kuroi, T. Yamashita, K. Shiga, T. Hayashi, M. Togawa, T. Eimori, Y. Ohji","doi":"10.1109/IWJT.2005.203872","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203872","url":null,"abstract":"In this paper, the impact of cluster ion (B/sub 18/H/sub x//sup +/) implantation on SDE formation are investigated in detail. It has been shown that B/sub 18/H/sub x//sup +/ ion implantation not only can make ultra-shallow junction for 45 nm node and beyond and but also has self-amorphization property and can reduce the channeling tail in the boron distribution without pre-amorphization implantation. In addition, B/sub 18/H/sub x//sup +/ ion implantation can be expected to reduce a fluctuation of MOSFETs, compared with B/sup +/ implantation. Cluster implantation is the reliability issue by hydrogen atom, because a large amount of hydrogen atoms are simultaneously introduced with boron into the silicon substrate. Moreover, neither the increase of junction leakage current nor influences of hydrogen which is introduced during B/sub 18/H/sub x//sup +/ implantation on PMOS reliability does not occur. The amorphization effect are evaluated by TEM observation and boron and hydrogen profiles by SIMS analysis.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126798122","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203868
T. Yamamoto, T. Kubo, T. Sukegawa, Y. Wang, L. Feng, S. Talwar, M. Kase
We have investigated in depth the impact of higher carrier activation by laser spike annealing (LSA), and demonstrate that LSA can improve the ion current while suppressing short channel effect in sub-40-nm CMOS devices compared to the conventional spike RTA. A shallower junction depth and shorter SDE overlap length can be achieved for the same SDE sheet resistance by using LSA, and as a result, Vth-rolloff can be improved dramatically. Moreover, the higher carrier activation of LSA produced improvements in ion current of 3%/14% for PMOS/NMOS. We also demonstrate that a 13% improvement in ion can be achieved for PMOS at the same Vth-rolloff.
{"title":"Performance enhancement in aggressively scaled CMOS devices higher carrier activation with laser spike annealing","authors":"T. Yamamoto, T. Kubo, T. Sukegawa, Y. Wang, L. Feng, S. Talwar, M. Kase","doi":"10.1109/IWJT.2005.203868","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203868","url":null,"abstract":"We have investigated in depth the impact of higher carrier activation by laser spike annealing (LSA), and demonstrate that LSA can improve the ion current while suppressing short channel effect in sub-40-nm CMOS devices compared to the conventional spike RTA. A shallower junction depth and shorter SDE overlap length can be achieved for the same SDE sheet resistance by using LSA, and as a result, Vth-rolloff can be improved dramatically. Moreover, the higher carrier activation of LSA produced improvements in ion current of 3%/14% for PMOS/NMOS. We also demonstrate that a 13% improvement in ion can be achieved for PMOS at the same Vth-rolloff.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124693630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203897
H. Tsujii, K. Adachi, K. Ohuchi, N. Aoki, T. Ito, K. Matsuo, K. Suguro, K. Ishimaru, H. Ishiuchi
We fabricated MOSFET devices using flash lamp annealing (FLA), and studied the halo profile dependence on CMOSFETs performance. Although FLA is high temperature anneal of 1000/spl deg/C or more and has soaking time corresponding to millisecond, it causes anomalous low level of halo dopant activation and redistribution. This anomaly degrades threshold voltage roll-off characteristics and Ion-Ioff characteristics. In this paper, we investigated halo dopant redistribution at each process step and the halo condition dependence of CMOSFETs characteristics, and proposed the design guideline of halo condition using FLA.
{"title":"Design guideline for halo condition on CMOSFETs utilizing FLA","authors":"H. Tsujii, K. Adachi, K. Ohuchi, N. Aoki, T. Ito, K. Matsuo, K. Suguro, K. Ishimaru, H. Ishiuchi","doi":"10.1109/IWJT.2005.203897","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203897","url":null,"abstract":"We fabricated MOSFET devices using flash lamp annealing (FLA), and studied the halo profile dependence on CMOSFETs performance. Although FLA is high temperature anneal of 1000/spl deg/C or more and has soaking time corresponding to millisecond, it causes anomalous low level of halo dopant activation and redistribution. This anomaly degrades threshold voltage roll-off characteristics and Ion-Ioff characteristics. In this paper, we investigated halo dopant redistribution at each process step and the halo condition dependence of CMOSFETs characteristics, and proposed the design guideline of halo condition using FLA.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116540119","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-06-07DOI: 10.1109/IWJT.2005.203869
Yimao Cai, Chuan Xu, X. Shan, Ru Huang, Yangyuan Wang
In this paper the impact of Ge-implantation on the work function of fully silicided NiSi gate is investigated. C-V measurement shows that work functions of NiSi gates with and without Ge implantation vary slightly, from 4.759 eV to 4.729 eV. The increase of interface state and fixed oxide charge introduced by Ge preamorphization implantation is not observed. These results demonstrate that fully silicided NiSi gate technology can be integrated with Ge preamorphization implantation in self alignment CMOS process.
{"title":"Study on the impact of Ge-implantation on the work function of fully silicided NiSi gate as ultra-shallow junction formed by using germanium preamorphization","authors":"Yimao Cai, Chuan Xu, X. Shan, Ru Huang, Yangyuan Wang","doi":"10.1109/IWJT.2005.203869","DOIUrl":"https://doi.org/10.1109/IWJT.2005.203869","url":null,"abstract":"In this paper the impact of Ge-implantation on the work function of fully silicided NiSi gate is investigated. C-V measurement shows that work functions of NiSi gates with and without Ge implantation vary slightly, from 4.759 eV to 4.729 eV. The increase of interface state and fixed oxide charge introduced by Ge preamorphization implantation is not observed. These results demonstrate that fully silicided NiSi gate technology can be integrated with Ge preamorphization implantation in self alignment CMOS process.","PeriodicalId":307038,"journal":{"name":"Extended Abstracts of the Fifth International Workshop on Junction Technology","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134485200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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