Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286214
T. Sutory, Z. Kolka
The paper deals with a modification of CBCM (charge-based capacitance measurements) for nonlinear capacitance characterization. The method is characterized by high resolution although it is based on equipment found in any average laboratory. CBCM was originally developed for linear interconnect measurements. The proposed modification uses two DC swept sources to measure the whole nonlinear Q-v characteristic in both polarities without the necessity to switch the measured object. A test-chip implementing the method was designed and manufactured in 0.35 mum CMOS process. Verification against known capacitances proved the method correctness and accuracy. It was successfully used for MOSCAPs characterization in full operating voltage range.
本文讨论了一种用于非线性电容表征的基于电荷的电容测量方法。该方法的特点是高分辨率，尽管它是基于在任何普通实验室发现的设备。CBCM最初是为线性互连测量开发的。提出的改进方法使用两个直流扫频源来测量两个极性下的整个非线性Q-v特性，而无需切换被测对象。采用0.35 μ m CMOS工艺设计并制作了实现该方法的测试芯片。对已知电容进行了验证，证明了方法的正确性和准确性。该方法已成功用于全工作电压范围内的MOSCAPs表征。
{"title":"C-V Characterization of Nonlinear Capacitors using CBCM Method","authors":"T. Sutory, Z. Kolka","doi":"10.1109/MIXDES.2007.4286214","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286214","url":null,"abstract":"The paper deals with a modification of CBCM (charge-based capacitance measurements) for nonlinear capacitance characterization. The method is characterized by high resolution although it is based on equipment found in any average laboratory. CBCM was originally developed for linear interconnect measurements. The proposed modification uses two DC swept sources to measure the whole nonlinear Q-v characteristic in both polarities without the necessity to switch the measured object. A test-chip implementing the method was designed and manufactured in 0.35 mum CMOS process. Verification against known capacitances proved the method correctness and accuracy. It was successfully used for MOSCAPs characterization in full operating voltage range.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129736768","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286165
A. Wielgus, M. Maciąg
This paper presents the design of a digital CMOS integrated circuit implementing fuzzy finite state automaton as a fuzzy logic controller. The parameterised VHDL model allows to synthesise the circuit of the required size for a particular application. Moreover, on-chip programming and reconfiguration of the automaton is performed.
{"title":"Digital Implementation of a Programmable Reconfigurable Fuzzy Automaton for Control Applications","authors":"A. Wielgus, M. Maciąg","doi":"10.1109/MIXDES.2007.4286165","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286165","url":null,"abstract":"This paper presents the design of a digital CMOS integrated circuit implementing fuzzy finite state automaton as a fuzzy logic controller. The parameterised VHDL model allows to synthesise the circuit of the required size for a particular application. Moreover, on-chip programming and reconfiguration of the automaton is performed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133399315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286209
B. Torbiéro, J. Launay, A. Benyahia, A. Martinez, P. Temple-Boyer
Most chemical or biochemical analysis use current-voltage I(V) characterization as detection principle. Thus, the development of microelectrodes using standard silicon technologies process is required: they show advantages of mass production, generic structure, small dimensions, low cost, and are well adapted for the detection of chemical, biochemical or biological species in aqueous environment using specific impedimetric measurement methods.
{"title":"Polysiloxane Thin Films Optimisation for Potassium Detection using EIS Characterisation with Microelectrode Structures","authors":"B. Torbiéro, J. Launay, A. Benyahia, A. Martinez, P. Temple-Boyer","doi":"10.1109/MIXDES.2007.4286209","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286209","url":null,"abstract":"Most chemical or biochemical analysis use current-voltage I(V) characterization as detection principle. Thus, the development of microelectrodes using standard silicon technologies process is required: they show advantages of mass production, generic structure, small dimensions, low cost, and are well adapted for the detection of chemical, biochemical or biological species in aqueous environment using specific impedimetric measurement methods.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"375 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133445711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286201
S. Senczyna
A designing of digital circuits is based on hardware description languages (HDLs). The dominating standard of HDLs is the VHDL, which basing on a digital circuit structure, a net-list, and an event-driven algorithm. In the publication is presented a description of the digital circuit built in an object-oriented programming. The base assumptions of a description are a digital circuit diagram and an event-driven algorithm. The descriptions are expressed in terms of the C#. A first part of the method based on a conception, which is widely published. A second part of the method is our conception of implementing an event-driven algorithm, using "a reformulating".
{"title":"Modeling and the Simulator of Digital Circuits in Object-Oriented Programming","authors":"S. Senczyna","doi":"10.1109/MIXDES.2007.4286201","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286201","url":null,"abstract":"A designing of digital circuits is based on hardware description languages (HDLs). The dominating standard of HDLs is the VHDL, which basing on a digital circuit structure, a net-list, and an event-driven algorithm. In the publication is presented a description of the digital circuit built in an object-oriented programming. The base assumptions of a description are a digital circuit diagram and an event-driven algorithm. The descriptions are expressed in terms of the C#. A first part of the method based on a conception, which is widely published. A second part of the method is our conception of implementing an event-driven algorithm, using \"a reformulating\".","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"134 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133212936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286148
A. Pułka
The paper concerns the problem of system level design i.e. generation of high quality abstract models of modern electronic embedded systems for simulation, verification and technology mapping. The work focuses on methodology and AI techniques that can be incorporated to CAD tools. The main effort has been done on formulation of the algorithm and inference engine that controls the process of SoC modeling. The presented methodology binds AI techniques and formal verification methods with complex digital systems modeling. The author's SMOG algorithm is briefly recalled as a basis for the presented approach. Then the algorithm modifications are proposed. Some aspects of the implementation of the method in PROLOG are emphasized. The results and conclusions summarize the work.
{"title":"A Heuristic Approach to System-Level Design Problems","authors":"A. Pułka","doi":"10.1109/MIXDES.2007.4286148","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286148","url":null,"abstract":"The paper concerns the problem of system level design i.e. generation of high quality abstract models of modern electronic embedded systems for simulation, verification and technology mapping. The work focuses on methodology and AI techniques that can be incorporated to CAD tools. The main effort has been done on formulation of the algorithm and inference engine that controls the process of SoC modeling. The presented methodology binds AI techniques and formal verification methods with complex digital systems modeling. The author's SMOG algorithm is briefly recalled as a basis for the presented approach. Then the algorithm modifications are proposed. Some aspects of the implementation of the method in PROLOG are emphasized. The results and conclusions summarize the work.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125523866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286173
Y. Sun, Y.S. Wang, F. Lai
Current mode implementation provides an alternative to high speed data conversion systems for low voltage applications. The pursuing of speed and accuracy of data conversion makes comparator critical. This paper presents a novel switched current (SI) comparator which achieves high speed without sacrificing either accuracy or power dissipation. Employing a class AB current mirror as the input stage, the desired accuracy is attained and a dynamic class AB latched comparator is used to achieve high operation speed. Both of the input stage and the latched comparator are low power blocks and the average supply current is only 85 muA during comparison. The proposed comparator is designed and simulated in TSMC 0.25 mum CMOS process with 1.8 V supply voltage. The proposed SI comparator achieves a current sensitivity up to 0.2 muA and a sampling frequency up to 100 MHz, with only 153 muW of total power consumption.
电流模式实现为低压应用提供了高速数据转换系统的替代方案。对数据转换速度和准确性的追求使得比较器至关重要。本文提出了一种新颖的开关电流比较器，在不牺牲精度和功耗的情况下实现了高速。采用AB类电流反射镜作为输入级，可以达到所需的精度，并使用动态AB类锁存比较器来实现高运算速度。输入级和锁存比较器都是低功率模块，在比较期间平均电源电流仅为85 muA。采用TSMC 0.25 μ m CMOS工艺，在1.8 V电源电压下对该比较器进行了设计和仿真。所提出的SI比较器实现了高达0.2 muA的电流灵敏度和高达100 MHz的采样频率，总功耗仅为153 muW。
{"title":"Low Power High Speed Switched Current Comparator","authors":"Y. Sun, Y.S. Wang, F. Lai","doi":"10.1109/MIXDES.2007.4286173","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286173","url":null,"abstract":"Current mode implementation provides an alternative to high speed data conversion systems for low voltage applications. The pursuing of speed and accuracy of data conversion makes comparator critical. This paper presents a novel switched current (SI) comparator which achieves high speed without sacrificing either accuracy or power dissipation. Employing a class AB current mirror as the input stage, the desired accuracy is attained and a dynamic class AB latched comparator is used to achieve high operation speed. Both of the input stage and the latched comparator are low power blocks and the average supply current is only 85 muA during comparison. The proposed comparator is designed and simulated in TSMC 0.25 mum CMOS process with 1.8 V supply voltage. The proposed SI comparator achieves a current sensitivity up to 0.2 muA and a sampling frequency up to 100 MHz, with only 153 muW of total power consumption.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130006181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286226
J. Kaczmarek, A. Mazurek
In the paper verification of new DC/DC converters control method, designed by authors with use of law of conservation of energy is presented. A comparison was made between classic DC/DC converters used widely in industry (for comparison LT1074 Linear Technology device was chosen), with converters equipped with analog-digital controller designed by authors. Results of conducted simulation research confirmed superior parameters of proposed solution when compared to classic converters, and much better immunity to changes in loads resistance. Both solutions have similar static parameters. Proposed method is an attractive alternative for actual DC/DC converters control methods.
{"title":"Comparison of Classic DC/DC Converters with Converters Equipped with Analog-Digital Regulator Based on Law of Conservation of Energy (Bumblebee Type)","authors":"J. Kaczmarek, A. Mazurek","doi":"10.1109/MIXDES.2007.4286226","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286226","url":null,"abstract":"In the paper verification of new DC/DC converters control method, designed by authors with use of law of conservation of energy is presented. A comparison was made between classic DC/DC converters used widely in industry (for comparison LT1074 Linear Technology device was chosen), with converters equipped with analog-digital controller designed by authors. Results of conducted simulation research confirmed superior parameters of proposed solution when compared to classic converters, and much better immunity to changes in loads resistance. Both solutions have similar static parameters. Proposed method is an attractive alternative for actual DC/DC converters control methods.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130885989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286212
P. Sniatala, J. Pierzchlewski, A. Handkiewicz, B. Nowakowski
This paper presents an original testing board dedicated for SI ASIC chips. The board is based on a programmable logic device, which generates the required signals for the tested chip. The parameters of the signals are set with a simple interface. The project was written in a VHDL and implemented in Xilinx CPLD. The board was used to test a new structure of a SI integrator, and the results are also presented.
{"title":"CPLD Based Development Board for Mixed Signal Chip Testing","authors":"P. Sniatala, J. Pierzchlewski, A. Handkiewicz, B. Nowakowski","doi":"10.1109/MIXDES.2007.4286212","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286212","url":null,"abstract":"This paper presents an original testing board dedicated for SI ASIC chips. The board is based on a programmable logic device, which generates the required signals for the tested chip. The parameters of the signals are set with a simple interface. The project was written in a VHDL and implemented in Xilinx CPLD. The board was used to test a new structure of a SI integrator, and the results are also presented.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123435359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286158
P. Grybos, P. Maj, R. Szczygiel
The problem of charge sensitive amplifier and pole-zero cancellation circuit designed in CMOS technology for high rates of input pulses is considered. The continuously sensitive charge amplifier uses a MOS transistor biased in triode region to discharge the integration capacitance. Low noise requirements of the front-end electronics place the feedback CSA resistance in hundreds of the megaohm range. However the high counting rate of input pulses generates a DC voltage shift at the CSA output which could degrade the circuit performance. We analyze two circuit architectures for biasing transistors in feedback of CSA and PZC circuit taking into account the pile-up effects in the signal processing chain.
{"title":"Comparison of Two Pole-Zero Cancellation Circuits for Fast Charge Sensitive Amplifier in CMOS Technology","authors":"P. Grybos, P. Maj, R. Szczygiel","doi":"10.1109/MIXDES.2007.4286158","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286158","url":null,"abstract":"The problem of charge sensitive amplifier and pole-zero cancellation circuit designed in CMOS technology for high rates of input pulses is considered. The continuously sensitive charge amplifier uses a MOS transistor biased in triode region to discharge the integration capacitance. Low noise requirements of the front-end electronics place the feedback CSA resistance in hundreds of the megaohm range. However the high counting rate of input pulses generates a DC voltage shift at the CSA output which could degrade the circuit performance. We analyze two circuit architectures for biasing transistors in feedback of CSA and PZC circuit taking into account the pile-up effects in the signal processing chain.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125702422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286228
F. Capy, A. Bourennane, M. Breil, F. Richardeau, E. Imbernon, J. Sanchez, J. Laur, P. Austin
In this paper, we present a design procedure for the integration of a new specific function based on the association of a ZVS mode thyristor and a circuit breaker dedicated to self-switching mode power converters. This function, based on the functional integration concept, monolithically associates protection, self-drive and power switch functions. This function uses an original switching mode of operation. After presenting the characteristics of the function and the function specifications, we focus on the different design steps: function optimization and cells sizing using 2D electrical and technological simulations, and mask design.
{"title":"Design of an Integrated Self-Switching Mode Device for Power Converters","authors":"F. Capy, A. Bourennane, M. Breil, F. Richardeau, E. Imbernon, J. Sanchez, J. Laur, P. Austin","doi":"10.1109/MIXDES.2007.4286228","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286228","url":null,"abstract":"In this paper, we present a design procedure for the integration of a new specific function based on the association of a ZVS mode thyristor and a circuit breaker dedicated to self-switching mode power converters. This function, based on the functional integration concept, monolithically associates protection, self-drive and power switch functions. This function uses an original switching mode of operation. After presenting the characteristics of the function and the function specifications, we focus on the different design steps: function optimization and cells sizing using 2D electrical and technological simulations, and mask design.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128700138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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