Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286219
A. A. Ivaniuk
This paper describes a new method of random access memory faults description using VHDL language. The fault injection technique, which uses behavioral synthesis VHDL descriptions, is proposed. The injection can be easily automated for memory test algorithms verification using only VHDL language and standard simulation software. No other applications and simulation tools are needed.
{"title":"Random Access Memory Faults Descriptions and Simulation using VHDL","authors":"A. A. Ivaniuk","doi":"10.1109/MIXDES.2007.4286219","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286219","url":null,"abstract":"This paper describes a new method of random access memory faults description using VHDL language. The fault injection technique, which uses behavioral synthesis VHDL descriptions, is proposed. The injection can be easily automated for memory test algorithms verification using only VHDL language and standard simulation software. No other applications and simulation tools are needed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132919706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286234
A. Verenik, M. Parfieniuk, A. Petrovsky
If a digital paraunitary filter bank (PUFB) designed using hypercomplex number theory is to be implemented in hardware, the throughput and chip area of used quaternion multipliers are of critical importance. In this paper, digit (L-bit)-serial quaternion multipliers based on the distributed arithmetic are presented as circuits well suited for FPGA-based fixed-point implementations of PUFBs. Apart from a theoretical development, experimental design results obtained using a Xilinx Virtex FPGA are reported.
{"title":"An FPGA Implementation of the Distributed Arithmetic Based Quaternionic Multipliers for Paraunitary Filter Banks","authors":"A. Verenik, M. Parfieniuk, A. Petrovsky","doi":"10.1109/MIXDES.2007.4286234","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286234","url":null,"abstract":"If a digital paraunitary filter bank (PUFB) designed using hypercomplex number theory is to be implemented in hardware, the throughput and chip area of used quaternion multipliers are of critical importance. In this paper, digit (L-bit)-serial quaternion multipliers based on the distributed arithmetic are presented as circuits well suited for FPGA-based fixed-point implementations of PUFBs. Apart from a theoretical development, experimental design results obtained using a Xilinx Virtex FPGA are reported.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117156333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286176
X. Ren, T. Kazmierski
The paper presents a novel approach to efficient performance modelling and optimisation which can be applied to automatic synthesis of circuit-level radio frequency (RF) analogue circuits. Support vector machines regression models are used to construct automatically general performance models for RF circuits which lend themselves naturally to pattern-search optimisation by exploring the design space. Experiments show that the approach can provide accurate and extremely fast performance estimation.
{"title":"Performance Modelling and Optimisation of RF Circuits using Support Vector Machines","authors":"X. Ren, T. Kazmierski","doi":"10.1109/MIXDES.2007.4286176","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286176","url":null,"abstract":"The paper presents a novel approach to efficient performance modelling and optimisation which can be applied to automatic synthesis of circuit-level radio frequency (RF) analogue circuits. Support vector machines regression models are used to construct automatically general performance models for RF circuits which lend themselves naturally to pattern-search optimisation by exploring the design space. Experiments show that the approach can provide accurate and extremely fast performance estimation.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115627418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286124
H. Momose, S. Yoshitomi, K. Kojima, T. Ohguro, Y. Toyoshima, H. Ishiuchi
Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. It was also found that the gate leakage current and 1/f noise in (110) samples were sensitive to off-axis angle.
{"title":"Electrical Characteristics in N- and P-MOSFETS with Slightly Tilted Off-Axis (110) Channel","authors":"H. Momose, S. Yoshitomi, K. Kojima, T. Ohguro, Y. Toyoshima, H. Ishiuchi","doi":"10.1109/MIXDES.2007.4286124","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286124","url":null,"abstract":"Si surface properties and electrical characteristics in n- and p-MOSFETs with 2-6 degree tilted off-axis (110) channel were investigated for the first time. The transconductance of p-MOSFET with off-axis channel was significantly degraded than that of normal channel on (110) plane, whereas that of n-MOSFET was slightly improved than that of normal channel. The changes were larger than those observed in slightly off-axis (100) samples. It was also found that the gate leakage current and 1/f noise in (110) samples were sensitive to off-axis angle.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115657299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286161
T. Kulej
A new structure of a current-mode LP active filter in CMOS technology, suitable for applications in very low frequency filters is presented in the paper. On the basis of this structure, particular solution of a sixth-order Bessel filter has been designed and tested by SPICE simulations. The main features of this design are; very low cutoff frequency (2.4 Hz), very low dissipation power (9 nW) and low supply voltage (1 V with additional auxiliary supply voltage equal to -1 V).
{"title":"Current-Mode LP CMOS Active Filter for Very Low Frequency Applications","authors":"T. Kulej","doi":"10.1109/MIXDES.2007.4286161","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286161","url":null,"abstract":"A new structure of a current-mode LP active filter in CMOS technology, suitable for applications in very low frequency filters is presented in the paper. On the basis of this structure, particular solution of a sixth-order Bessel filter has been designed and tested by SPICE simulations. The main features of this design are; very low cutoff frequency (2.4 Hz), very low dissipation power (9 nW) and low supply voltage (1 V with additional auxiliary supply voltage equal to -1 V).","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130454444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286130
B. Mukherjee, D. Makowski, V. Mareš, D. Rybka, S. Simrock
During a long range intercontinental commercial flight from Europe to Australia the neutron and photon dose equivalents have been evaluated using a pair of electronic pocket dosemeters ALOKA PDM-313 and ALOKA PDM-111, respectively. A temperature compensated superheated emulsion (bubble) detector and an aluminium oxide TL-Dosimeter were carried together for the purpose of in-flight calibration of the electronic dosemeters. We have evaluated the radiation doses during flights from various cities in the northern hemisphere to Sydney (Australia). The results were compared with the cosmic radiation exposure calculated using the EPCARD and CARI 6 flight dose computation codes developed by GSF (Germany) and FAA (USA), respectively. A simple method of aviation dose interpolation based on polynomial fitting has been proposed.
{"title":"In Situ Measurement of Neutron and Gamma Radiation Exposures During Intercontinental Flights using Electronic Personal Dosimeters and Bubble Detectors","authors":"B. Mukherjee, D. Makowski, V. Mareš, D. Rybka, S. Simrock","doi":"10.1109/MIXDES.2007.4286130","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286130","url":null,"abstract":"During a long range intercontinental commercial flight from Europe to Australia the neutron and photon dose equivalents have been evaluated using a pair of electronic pocket dosemeters ALOKA PDM-313 and ALOKA PDM-111, respectively. A temperature compensated superheated emulsion (bubble) detector and an aluminium oxide TL-Dosimeter were carried together for the purpose of in-flight calibration of the electronic dosemeters. We have evaluated the radiation doses during flights from various cities in the northern hemisphere to Sydney (Australia). The results were compared with the cosmic radiation exposure calculated using the EPCARD and CARI 6 flight dose computation codes developed by GSF (Germany) and FAA (USA), respectively. A simple method of aviation dose interpolation based on polynomial fitting has been proposed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130795455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286157
A. Sobczyk, A. W. Luczyk, W. Pleskacz
In this paper local clock signal generator basing on three different ring oscillators is discussed. The structure was designed to verify possibility of local clock signal generation using basic delay stages. General simulations were performed to analyze power dissipation and stability of frequency in regard to temperature, transistor model and layout extraction parameters. All circuits were designed in standard CMOS 0.35 mum technology.
{"title":"Analysis of Basic Pausable Local Clock Signal Generator","authors":"A. Sobczyk, A. W. Luczyk, W. Pleskacz","doi":"10.1109/MIXDES.2007.4286157","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286157","url":null,"abstract":"In this paper local clock signal generator basing on three different ring oscillators is discussed. The structure was designed to verify possibility of local clock signal generation using basic delay stages. General simulations were performed to analyze power dissipation and stability of frequency in regard to temperature, transistor model and layout extraction parameters. All circuits were designed in standard CMOS 0.35 mum technology.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128382822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286164
J. Kolczynski
This article covers the topic of designing the operational amplifiers, it describes the design of a compact, low power amplifier utilizing 0.35 μm CMOS technology. The main motivation behind this work was the existing need at the Technical University of Lodz for compact device that could be easily employed in larger designs. This article describes best topology for each stage in terms of meeting the design goals. The final circuit is a unique combination of low power topologies with solutions from large gain, high power amplifiers. This was done to achieve largest possible value of amplifier's gain within total power consumption constraint. The device performance was verified positively both at the schematic and at the layout level.
{"title":"Design of Operational Amplifier with Low Power Consumption in 0.35 μm Technology","authors":"J. Kolczynski","doi":"10.1109/MIXDES.2007.4286164","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286164","url":null,"abstract":"This article covers the topic of designing the operational amplifiers, it describes the design of a compact, low power amplifier utilizing 0.35 μm CMOS technology. The main motivation behind this work was the existing need at the Technical University of Lodz for compact device that could be easily employed in larger designs. This article describes best topology for each stage in terms of meeting the design goals. The final circuit is a unique combination of low power topologies with solutions from large gain, high power amplifiers. This was done to achieve largest possible value of amplifier's gain within total power consumption constraint. The device performance was verified positively both at the schematic and at the layout level.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114219179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286149
Timmy Sundström, A. Alvandpour
This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6times, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90 nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.
{"title":"A Kick-Back Reduced Comparator for a 4-6-Bit 3-GS/s Flash ADC in a 90nm CMOS Process","authors":"Timmy Sundström, A. Alvandpour","doi":"10.1109/MIXDES.2007.4286149","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286149","url":null,"abstract":"This paper presents a kick-back reduced comparator based on a sense-amplifier type comparator. The kickback charge and resulting voltage peak is reduced by 6times, which corresponds to a power reduction in the input driver and the resistance ladder of the same magnitude. A 4-6-bit 3-GS/s low-power flash ADC using the proposed comparator has been implemented in a 90 nm CMOS process. The significantly lower requirements on input driver and resistance ladder have reduced the overall ADC power dissipation by 50%.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127682517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286208
M. Zaborowski, B. Jaroszewicz, D. Tomaszewski, P. Prokaryn, E. Malinowska, E. Grygolowicz-Pawlak, P. Grabiec
Preparation of pH-sensors and structures ready for ion-sensitive coating for in-line water pollution monitoring was the aim of the paper. Au and AgCl electrodes with Au backside contacts were developed using mono-Si substrates. Sequence of manufacturing process was presented. Device series resistance and potentiometric response were positively tested. ISFET pH sensors were manufactured and fully characterized. They were suitable for current use and found to be a basis for further industrialization of the sensor fabrication process.
{"title":"Fabrication of MOS - Compatible Ion - Sensitive Devices for Water Pollution Monitoring (Warmer)","authors":"M. Zaborowski, B. Jaroszewicz, D. Tomaszewski, P. Prokaryn, E. Malinowska, E. Grygolowicz-Pawlak, P. Grabiec","doi":"10.1109/MIXDES.2007.4286208","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286208","url":null,"abstract":"Preparation of pH-sensors and structures ready for ion-sensitive coating for in-line water pollution monitoring was the aim of the paper. Au and AgCl electrodes with Au backside contacts were developed using mono-Si substrates. Sequence of manufacturing process was presented. Device series resistance and potentiometric response were positively tested. ISFET pH sensors were manufactured and fully characterized. They were suitable for current use and found to be a basis for further industrialization of the sensor fabrication process.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127869417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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