Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286230
J. Kaczmarek, A. Mazurek
In the paper the new, original concept of controlling output voltage of DC/DC converters by using law of conservation of energy is presented. This concept was invented specifically to be used in mixed analog-digital and digital converter control devices. Conducted research shown, that controllers based on this method, practically aren't vulnerable to changes of working point and converters working mode (CCM, DCM), also they do not require information about values of state variables from previous cycles.
{"title":"New Concept of DC/DC Converters Digital Control Based on Law of Conservation of Energy - Project \"Bumblebee\"","authors":"J. Kaczmarek, A. Mazurek","doi":"10.1109/MIXDES.2007.4286230","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286230","url":null,"abstract":"In the paper the new, original concept of controlling output voltage of DC/DC converters by using law of conservation of energy is presented. This concept was invented specifically to be used in mixed analog-digital and digital converter control devices. Conducted research shown, that controllers based on this method, practically aren't vulnerable to changes of working point and converters working mode (CCM, DCM), also they do not require information about values of state variables from previous cycles.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126442019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286123
S. Yoshitomi, A. Bazigos, M. Bucher
EKV3 is a circuit-design-oriented compact MOSFET model for analog/RF IC design. The paper presents parameter extraction guidelines and modelling using EKV3 for TOSHIBA's 90 nm RF-CMOS technology covering DC, CV and RF (S-parameter) and temperature scalability. RF verification was done by the use of multi-finger MOSFETs with many variations of gate length, width of unit fingers and number of fingers. A scalable RF model was successfully created. Extraction of RF parasitics and their scaling with RF layout is investigated. The EKV3 model successfully predicted high-frequency behaviour of 90 nm CMOS up to 20 GHz over a wide range of bias conditions.
{"title":"EKV3 Parameter Extraction and Characterization of 90nm RF-CMOS Technology","authors":"S. Yoshitomi, A. Bazigos, M. Bucher","doi":"10.1109/MIXDES.2007.4286123","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286123","url":null,"abstract":"EKV3 is a circuit-design-oriented compact MOSFET model for analog/RF IC design. The paper presents parameter extraction guidelines and modelling using EKV3 for TOSHIBA's 90 nm RF-CMOS technology covering DC, CV and RF (S-parameter) and temperature scalability. RF verification was done by the use of multi-finger MOSFETs with many variations of gate length, width of unit fingers and number of fingers. A scalable RF model was successfully created. Extraction of RF parasitics and their scaling with RF layout is investigated. The EKV3 model successfully predicted high-frequency behaviour of 90 nm CMOS up to 20 GHz over a wide range of bias conditions.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123897302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286178
S. El Rai, A. Pawlikiewicz, D. Jager, R. Tempel
Differential transmission lines (DTL) can be synthesized as a chain of identical 4-Port unit cells (UC). These DTL are interesting to use for either matching the circuits or for realizing small resonators in filters or oscillators. One very interesting aspect is the tunability of such a transmission line. Tunability means the ability to tune the electrical length and the characteristic impedance by applying appropriate voltage. In this paper, we introduce a new method to realize the tunability of these transmission lines thru magnetic coupling. This tunable Periodical DTL (PDTL) provides highly interesting applications for silicon MMICs.
{"title":"Realization of Tunable Periodical Differential Transmission Lines on Silicon","authors":"S. El Rai, A. Pawlikiewicz, D. Jager, R. Tempel","doi":"10.1109/MIXDES.2007.4286178","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286178","url":null,"abstract":"Differential transmission lines (DTL) can be synthesized as a chain of identical 4-Port unit cells (UC). These DTL are interesting to use for either matching the circuits or for realizing small resonators in filters or oscillators. One very interesting aspect is the tunability of such a transmission line. Tunability means the ability to tune the electrical length and the characteristic impedance by applying appropriate voltage. In this paper, we introduce a new method to realize the tunability of these transmission lines thru magnetic coupling. This tunable Periodical DTL (PDTL) provides highly interesting applications for silicon MMICs.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116820237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286188
A. Golda, A. Kos
The paper presents new supervisors dedicated to predictive methods of dynamic power management, i.e. DCT (dynamic clock throttling), DFS (dynamic frequency scaling), and DVS (dynamic voltage scaling). The presented supervisors make decisions on the basis of current chip temperature; future, current and previous power dissipations. They consist in cooperation with operating system and they are dedicated to high efficiency systems. The proposed supervisors can be implemented in both software and hardware, e.g. as neural network. Not only performance gain but also energy profit can be made in systems that use these supervisors. Simulations results of considered cases show that theoretical improvement of the ideal supervisor is in the range of 7.38 to 16.17% for performance and of 2.47 to 9.88% for energy. The profit of the real supervise method depends on the complexity of supervisor.
{"title":"Effective Supervisors for Predictive Methods of Dynamic Power Management","authors":"A. Golda, A. Kos","doi":"10.1109/MIXDES.2007.4286188","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286188","url":null,"abstract":"The paper presents new supervisors dedicated to predictive methods of dynamic power management, i.e. DCT (dynamic clock throttling), DFS (dynamic frequency scaling), and DVS (dynamic voltage scaling). The presented supervisors make decisions on the basis of current chip temperature; future, current and previous power dissipations. They consist in cooperation with operating system and they are dedicated to high efficiency systems. The proposed supervisors can be implemented in both software and hardware, e.g. as neural network. Not only performance gain but also energy profit can be made in systems that use these supervisors. Simulations results of considered cases show that theoretical improvement of the ideal supervisor is in the range of 7.38 to 16.17% for performance and of 2.47 to 9.88% for energy. The profit of the real supervise method depends on the complexity of supervisor.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125939757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286180
E. Kurjata-Pfitzner, A. Szymanski, J. Lesiński
The paper describes real, successive steps of the design of fully integrated QVCO for 2.4 GHz. First version of the design, correct in simulation, does not fulfil the requirements when it was measured. The detailed reasons of changes introduced in the design are presented. Comparison of measured tuning characteristic with simulated one proves the validity of design steps.
{"title":"Some Practical Aspects of Integrated 2.4 GHz Quadrature VCO Design","authors":"E. Kurjata-Pfitzner, A. Szymanski, J. Lesiński","doi":"10.1109/MIXDES.2007.4286180","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286180","url":null,"abstract":"The paper describes real, successive steps of the design of fully integrated QVCO for 2.4 GHz. First version of the design, correct in simulation, does not fulfil the requirements when it was measured. The detailed reasons of changes introduced in the design are presented. Comparison of measured tuning characteristic with simulated one proves the validity of design steps.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121907256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286184
M. Kamiński, M. Janicki, A. Napieralski
The main goal of this paper is to present an extension of a numerical solver dedicated to thermal simulation of electronic structures. This solver implements the finite difference method and employs the RC equivalent network approach. The hereby-proposed extension renders possible thermal simulation taking into account non-linear cases when material thermal properties and heat transfer coefficient values depend on temperature. For this purpose, the standard equivalent RC circuit method has been significantly modified. All the required modifications are presented in this paper in detail. Additionally, the differences between the results obtained with both the linear and non-linear simulators have been compared and discussed based on the examples of selected test structures.
{"title":"Application of RC Equivalent Networks to Modelling of Nonlinear Thermal Phenomena","authors":"M. Kamiński, M. Janicki, A. Napieralski","doi":"10.1109/MIXDES.2007.4286184","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286184","url":null,"abstract":"The main goal of this paper is to present an extension of a numerical solver dedicated to thermal simulation of electronic structures. This solver implements the finite difference method and employs the RC equivalent network approach. The hereby-proposed extension renders possible thermal simulation taking into account non-linear cases when material thermal properties and heat transfer coefficient values depend on temperature. For this purpose, the standard equivalent RC circuit method has been significantly modified. All the required modifications are presented in this paper in detail. Additionally, the differences between the results obtained with both the linear and non-linear simulators have been compared and discussed based on the examples of selected test structures.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131405228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286197
V. Hahanov, M. Kaminska, W. Ghribi, A. Hahanova
In the paper structure functional multi-valued hardware model of digital device is offered; two-circuits structure functional multi-valued hardware model of digital device for multiple input patterns co-simulation and multiple increasing of performance transient analysis in sequential structures is proposed; automatic model of HDL-code transmission process to data structure for digital system on chip analysis and verification with hardware is proposed.
{"title":"Hardware Fault Free Simulation for SOC","authors":"V. Hahanov, M. Kaminska, W. Ghribi, A. Hahanova","doi":"10.1109/MIXDES.2007.4286197","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286197","url":null,"abstract":"In the paper structure functional multi-valued hardware model of digital device is offered; two-circuits structure functional multi-valued hardware model of digital device for multiple input patterns co-simulation and multiple increasing of performance transient analysis in sequential structures is proposed; automatic model of HDL-code transmission process to data structure for digital system on chip analysis and verification with hardware is proposed.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130757885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286248
H. Esmaeilzadeh, M. Jamali, P. Saeedi, A. Moghimi, C. Lucas, S. M. Fakhraie
With time-to-market getting the most important issue in system design, reusing the design experiences as well as the IP cores is becoming very critical. Design patterns, intended for simplifying the reuse process, are design experiences that worked well in the past and documented to be reused in the future. In this paper, a design pattern named NnEP (Neural-network-based Embedded systems design Pattern) is introduced for employing neural networks, common bio-inspired solutions, in SoC-based embedded systems. This pattern is based on NnSP IP suite, a stream processing core and its tool chain, NnSP Builder and Stream Compiler. NnEP is introduced for enhancing and automating reuse in design of intelligent SoC's requiring high-speed parallel computations specially those based on neural networks. The NnEP pattern consists of the semi-automated steps, extracted from design experiences, a designer takes using the provided software suite to realize a NN application in an intelligent SoC. This includes the application analysis and pre-processing procedure, building the best-match IP core with the application, and finally compiling the intended NN application on the target IP core. On the other hand, ASIC 0.18 mum implementation results of NnSP soft core show that the core can achieve the speed of 51.2 GOPS, 25.6 GMAC/s. This throughput is comparable with the existing parallel solutions and higher in an order of magnitude from common general-purpose-processor-based solutions. This high throughput in conjunction with the inherent reusable architecture of NnSP, makes NnEP a powerful design pattern for cutting-edge neural-network-based embedded applications such as pattern recognition which is elaborated as a case study in the proposed design pattern.
{"title":"NNEP, Design Pattern for Neural-Network-Based Embedded Systems","authors":"H. Esmaeilzadeh, M. Jamali, P. Saeedi, A. Moghimi, C. Lucas, S. M. Fakhraie","doi":"10.1109/MIXDES.2007.4286248","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286248","url":null,"abstract":"With time-to-market getting the most important issue in system design, reusing the design experiences as well as the IP cores is becoming very critical. Design patterns, intended for simplifying the reuse process, are design experiences that worked well in the past and documented to be reused in the future. In this paper, a design pattern named NnEP (Neural-network-based Embedded systems design Pattern) is introduced for employing neural networks, common bio-inspired solutions, in SoC-based embedded systems. This pattern is based on NnSP IP suite, a stream processing core and its tool chain, NnSP Builder and Stream Compiler. NnEP is introduced for enhancing and automating reuse in design of intelligent SoC's requiring high-speed parallel computations specially those based on neural networks. The NnEP pattern consists of the semi-automated steps, extracted from design experiences, a designer takes using the provided software suite to realize a NN application in an intelligent SoC. This includes the application analysis and pre-processing procedure, building the best-match IP core with the application, and finally compiling the intended NN application on the target IP core. On the other hand, ASIC 0.18 mum implementation results of NnSP soft core show that the core can achieve the speed of 51.2 GOPS, 25.6 GMAC/s. This throughput is comparable with the existing parallel solutions and higher in an order of magnitude from common general-purpose-processor-based solutions. This high throughput in conjunction with the inherent reusable architecture of NnSP, makes NnEP a powerful design pattern for cutting-edge neural-network-based embedded applications such as pattern recognition which is elaborated as a case study in the proposed design pattern.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134115980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286132
G. Jablonski, K. Przygoda
The paper presents a low-latency implementation of Cartesian-polar coordinate conversion in a Virtex II pro FPGA. The accuracy and resource consumption of the module is comparable to the one obtained with the Xilinx CORDIC IP Core, but the latency has been reduced to 65%. The application of the conversion module to the cavity detuning computation in low-level radio frequency control system for a FLASH accelerator has been also presented.
本文介绍了在Virtex II pro FPGA上实现笛卡尔-极坐标转换的低延迟实现。该模块的精度和资源消耗与Xilinx CORDIC IP Core相当，但延迟已减少到65%。本文还介绍了该转换模块在FLASH加速器低电平射频控制系统中腔体失谐计算中的应用。
{"title":"Low-Latency Implementation of Coordinate Conversion in Virtex II pro FPGA","authors":"G. Jablonski, K. Przygoda","doi":"10.1109/MIXDES.2007.4286132","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286132","url":null,"abstract":"The paper presents a low-latency implementation of Cartesian-polar coordinate conversion in a Virtex II pro FPGA. The accuracy and resource consumption of the module is comparable to the one obtained with the Xilinx CORDIC IP Core, but the latency has been reduced to 65%. The application of the conversion module to the cavity detuning computation in low-level radio frequency control system for a FLASH accelerator has been also presented.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114244500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-06-21DOI: 10.1109/MIXDES.2007.4286122
D. Obrbski, K. Kucharski, M. Grodner, A. Kokoszka, A. Malinowski, J. Lesiński, D. Tomaszewski, J. Malesinska
A MPW service has been arranged in the ITE in order to offer facility to academies for prototyping of CMOS ICs. This service is based on the proprietary CMOS process. The technology has been characterized via electrical measurements of dedicated test structures. The characteristics have been implemented in the form of design kit. Cadence reg design system has been chosen as a target tool for ICs design because of its popularity in European academies due to availability via EUROPRACTICE program. A number of functionalities have been implemented in the design kit. Namely, layout verification procedures (DRC, extraction, LVS) for Diva (TM) and Assura (TM) applications, automated generation of auxiliary technological layers (using Assura), layout import / export (GDSII, CIF formats) and corner analysis. Hence, a complete tool for ASICs design at the universities has been established.
{"title":"Development of MPW Service for Academies Based on ITE Proprietary CMOS Process","authors":"D. Obrbski, K. Kucharski, M. Grodner, A. Kokoszka, A. Malinowski, J. Lesiński, D. Tomaszewski, J. Malesinska","doi":"10.1109/MIXDES.2007.4286122","DOIUrl":"https://doi.org/10.1109/MIXDES.2007.4286122","url":null,"abstract":"A MPW service has been arranged in the ITE in order to offer facility to academies for prototyping of CMOS ICs. This service is based on the proprietary CMOS process. The technology has been characterized via electrical measurements of dedicated test structures. The characteristics have been implemented in the form of design kit. Cadence reg design system has been chosen as a target tool for ICs design because of its popularity in European academies due to availability via EUROPRACTICE program. A number of functionalities have been implemented in the design kit. Namely, layout verification procedures (DRC, extraction, LVS) for Diva (TM) and Assura (TM) applications, automated generation of auxiliary technological layers (using Assura), layout import / export (GDSII, CIF formats) and corner analysis. Hence, a complete tool for ASICs design at the universities has been established.","PeriodicalId":310187,"journal":{"name":"2007 14th International Conference on Mixed Design of Integrated Circuits and Systems","volume":"10 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116754889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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