Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690552
D. Hauschild, P. Harten, L. Aschke, V. Lissotschenko
The use of laser technologies for the well defined selective heating of wafers and thin film semiconductors for melt and non-melt RTP processes is an alternative way to fulfil the design goals of next generation semiconductor devices for data processing or photovoltaic. A variety of efficient and reliable laser sources are available from UV to IR that can match the absorption characteristics of nearly any material. To make technical and economical use of these advantages the laser power has to be focussed on the surface with a well defined beam geometry and intensity profile. For a fast processing of 300mm wafers or Gen 8 LCD or solar panels a beam with line or rectangular geometry is needed. In addition to the beam geometry, the intensity distribution in scanning direction is an essential parameter for a controlled temporal heating and cooling profile of the materials. These beam profiles control the vertical thermal penetration depth and reduce the thermal load of the semiconductor layers and substrates by faster scanning speed and μs- and ns-illumination regime.
{"title":"Free form microlens sysems enable new laser beam profiles for RTP","authors":"D. Hauschild, P. Harten, L. Aschke, V. Lissotschenko","doi":"10.1109/RTP.2008.4690552","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690552","url":null,"abstract":"The use of laser technologies for the well defined selective heating of wafers and thin film semiconductors for melt and non-melt RTP processes is an alternative way to fulfil the design goals of next generation semiconductor devices for data processing or photovoltaic. A variety of efficient and reliable laser sources are available from UV to IR that can match the absorption characteristics of nearly any material. To make technical and economical use of these advantages the laser power has to be focussed on the surface with a well defined beam geometry and intensity profile. For a fast processing of 300mm wafers or Gen 8 LCD or solar panels a beam with line or rectangular geometry is needed. In addition to the beam geometry, the intensity distribution in scanning direction is an essential parameter for a controlled temporal heating and cooling profile of the materials. These beam profiles control the vertical thermal penetration depth and reduce the thermal load of the semiconductor layers and substrates by faster scanning speed and μs- and ns-illumination regime.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"245 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131882365","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690563
D. H. Petersen, O. Hansen, R. Lin, P. Nielsen, T. Clarysse, J. Goossens, E. Rosseel, W. Vandervorst
Accurate characterization of ultra shallow junctions (USJ) is important in order to understand the principles of junction formation and to develop the appropriate implant and annealing technologies. We investigate the capabilities of a new micro-scale Hall effect measurement method where Hall effect is measured with collinear micro four-point probes (M4PP). We derive the sensitivity to electrode position errors and describe a position error suppression method to enable rapid reliable Hall effect measurements with just two measurement points. We show with both Monte Carlo simulations and experimental measurements, that the repeatability of a micro-scale Hall effect measurement is better than 1 %. We demonstrate the ability to spatially resolve Hall effect on micro-scale by characterization of an USJ with a single laser stripe anneal. The micro sheet resistance variations resulting from a spatially inhomogeneous anneal temperature are found to be directly correlated to the degree of dopant activation.
{"title":"High precision micro-scale Hall effect characterization method using in-line micro four-point probes","authors":"D. H. Petersen, O. Hansen, R. Lin, P. Nielsen, T. Clarysse, J. Goossens, E. Rosseel, W. Vandervorst","doi":"10.1109/RTP.2008.4690563","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690563","url":null,"abstract":"Accurate characterization of ultra shallow junctions (USJ) is important in order to understand the principles of junction formation and to develop the appropriate implant and annealing technologies. We investigate the capabilities of a new micro-scale Hall effect measurement method where Hall effect is measured with collinear micro four-point probes (M4PP). We derive the sensitivity to electrode position errors and describe a position error suppression method to enable rapid reliable Hall effect measurements with just two measurement points. We show with both Monte Carlo simulations and experimental measurements, that the repeatability of a micro-scale Hall effect measurement is better than 1 %. We demonstrate the ability to spatially resolve Hall effect on micro-scale by characterization of an USJ with a single laser stripe anneal. The micro sheet resistance variations resulting from a spatially inhomogeneous anneal temperature are found to be directly correlated to the degree of dopant activation.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114526445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690538
Y. Wang, Shaoyin Chen, M. Shen, Xiaoru Wang, Senquan Zhou, A. Hawryluk, J. Hebb, D. Owen
Laser spike annealing (LSA) is a disruptive technology which has been successfully demonstrated for advanced junction engineering—creating highly activated ultra-shallow junctions with near diffusion-less boundaries. These produce higher performing devices with improved drive currents and/or lower leakage currents, and provide design engineers more opportunities for product enhancements. LSA has become the “process of record” for a majority of the industry’s high-performance, logic device manufacturers. LSA produces more uniform temperature and stress distributions in product wafers than lamp-based short time annealing processes. Furthermore, LSA is compatible with new materials such as strained Si, SiGe, high-k and metal gates, and is extendable to new device structures. This paper will review the current LSA capabilities, process and integration methods, summarize its unique capabilities to reduce temperature-induced stress and misalignment, and discuss future opportunities both in junction engineering and other integration areas.
{"title":"Laser spike annealing and its application to leading-edge logic devices","authors":"Y. Wang, Shaoyin Chen, M. Shen, Xiaoru Wang, Senquan Zhou, A. Hawryluk, J. Hebb, D. Owen","doi":"10.1109/RTP.2008.4690538","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690538","url":null,"abstract":"Laser spike annealing (LSA) is a disruptive technology which has been successfully demonstrated for advanced junction engineering—creating highly activated ultra-shallow junctions with near diffusion-less boundaries. These produce higher performing devices with improved drive currents and/or lower leakage currents, and provide design engineers more opportunities for product enhancements. LSA has become the “process of record” for a majority of the industry’s high-performance, logic device manufacturers. LSA produces more uniform temperature and stress distributions in product wafers than lamp-based short time annealing processes. Furthermore, LSA is compatible with new materials such as strained Si, SiGe, high-k and metal gates, and is extendable to new device structures. This paper will review the current LSA capabilities, process and integration methods, summarize its unique capabilities to reduce temperature-induced stress and misalignment, and discuss future opportunities both in junction engineering and other integration areas.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114694435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690540
S. Catlett, J. Shepard
Temperature control requirements for Rapid Thermal Anneal (RTA) process steps, notably the source/drain activation anneal, have reached the limits of process capability at the 65 nm node. Device requirements dictate the tools be matched to better than 2°C and peak-temperature controlled to better than 1°C at ramp-up rates between 75°C/s and 230°C/s. It is important to understand all sources of variation in the time-temperature profile and the effects of this variation on measured parameters such as sheet resistance (Rs) on both monitor and product wafers. This work examines the effect of wafer thickness on the time-temperature behavior during the RTA process and its subsequent effect on Rs. It is shown that thicker wafers lead to a lower Rs. Nominal wafer thickness is 750 μm, but a variation in thickness of 10 μm results in an Rs shift of 0.5 ohms/square, the equivalent to a peak-temperature change of 0.63°C. This behavior is shown to have a significant effect on both monitor and product wafers. A study of 100 Hz data from the RTA chamber shows that this effect is likely due to two factors: (1) Thicker wafers reach a higher peak temperature, and (2) after reaching peak temperature, thicker wafers cool more slowly. Peak temperature reached is seen to change by 0.34°C per 10 μm of thickness change. The cooling rate changes by approximately 1°C/s per 10 μm of thickness change. Together, higher peak temperature and lower cooling rate result in a higher thermal budget, greater activation, and lower Rs for thicker wafers.
{"title":"Effect of wafer thickness on sheet resistance during spike annealing","authors":"S. Catlett, J. Shepard","doi":"10.1109/RTP.2008.4690540","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690540","url":null,"abstract":"Temperature control requirements for Rapid Thermal Anneal (RTA) process steps, notably the source/drain activation anneal, have reached the limits of process capability at the 65 nm node. Device requirements dictate the tools be matched to better than 2°C and peak-temperature controlled to better than 1°C at ramp-up rates between 75°C/s and 230°C/s. It is important to understand all sources of variation in the time-temperature profile and the effects of this variation on measured parameters such as sheet resistance (Rs) on both monitor and product wafers. This work examines the effect of wafer thickness on the time-temperature behavior during the RTA process and its subsequent effect on Rs. It is shown that thicker wafers lead to a lower Rs. Nominal wafer thickness is 750 μm, but a variation in thickness of 10 μm results in an Rs shift of 0.5 ohms/square, the equivalent to a peak-temperature change of 0.63°C. This behavior is shown to have a significant effect on both monitor and product wafers. A study of 100 Hz data from the RTA chamber shows that this effect is likely due to two factors: (1) Thicker wafers reach a higher peak temperature, and (2) after reaching peak temperature, thicker wafers cool more slowly. Peak temperature reached is seen to change by 0.34°C per 10 μm of thickness change. The cooling rate changes by approximately 1°C/s per 10 μm of thickness change. Together, higher peak temperature and lower cooling rate result in a higher thermal budget, greater activation, and lower Rs for thicker wafers.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114175928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690543
K. Sekar, W. Krull, J. Chan, S. Mccoy, J. Gelpey
We report here the use of a novel cluster carbon (C7H7+) implant along with n-type source drain dopant implants (As and P2) to form an embedded Silicon-Carbon (Si:C) layer. The implanted wafers were annealed using millisecond flash anneal (fRTP) followed by a post impulse spike RTP anneal (iRTP) for deactivation studies. The percentage of substitutional carbon ([C]subs) in the formed Si:C layer is characterized by a high-resolution x-ray diffraction (HRXRD) technique. The dependence of post spike anneal temperature on [C]subs show similar behavior for both As and P2 implants. With this clustercarbon implant approach the strain relaxation is only about 10% (90% strain retention) for the post spike anneal temperature of 1000°C. Higher flash anneal temperature leads to lower [C]subs. The sheet resistance is lower in the case of P2 implants when compared to As implants. We present here the detailed characterization of Si:C layer using HRXRD, SIMS, XTEM and activation of n-type dopants using SIMS and Rs measurements.
{"title":"Annealing behavior of clustercarbon™ implants","authors":"K. Sekar, W. Krull, J. Chan, S. Mccoy, J. Gelpey","doi":"10.1109/RTP.2008.4690543","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690543","url":null,"abstract":"We report here the use of a novel cluster carbon (C7H7+) implant along with n-type source drain dopant implants (As and P2) to form an embedded Silicon-Carbon (Si:C) layer. The implanted wafers were annealed using millisecond flash anneal (fRTP) followed by a post impulse spike RTP anneal (iRTP) for deactivation studies. The percentage of substitutional carbon ([C]subs) in the formed Si:C layer is characterized by a high-resolution x-ray diffraction (HRXRD) technique. The dependence of post spike anneal temperature on [C]subs show similar behavior for both As and P2 implants. With this clustercarbon implant approach the strain relaxation is only about 10% (90% strain retention) for the post spike anneal temperature of 1000°C. Higher flash anneal temperature leads to lower [C]subs. The sheet resistance is lower in the case of P2 implants when compared to As implants. We present here the detailed characterization of Si:C layer using HRXRD, SIMS, XTEM and activation of n-type dopants using SIMS and Rs measurements.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125648678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-01DOI: 10.1109/RTP.2008.4690533
V. Carron
▪ Strained and Ge-based materials have great interests for CMOS technology enhancement ▪ However, their introduction as channel and/or S&D materials has a strong impact on the Salicide process which needs adaptations in order to keep the expected benefit induced by these new materials ▪ Indeed, new issues related to the silicidation (germanidation) of these advanced materials have emerged and most of them have been solved (exemple : Ge lateral diffusion) ▪ In addition to strained and Ge-based materials, the choice of the silicide/germanide contact material in itself, as well as the associated salicide process, are key areas for further performance enhancement (interface engineering, dual silicide approach…)
{"title":"S&D salicidation for advanced CMOS technology: Ge, SiGe, Si:C, and sSibased devices","authors":"V. Carron","doi":"10.1109/RTP.2008.4690533","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690533","url":null,"abstract":"▪ Strained and Ge-based materials have great interests for CMOS technology enhancement ▪ However, their introduction as channel and/or S&D materials has a strong impact on the Salicide process which needs adaptations in order to keep the expected benefit induced by these new materials ▪ Indeed, new issues related to the silicidation (germanidation) of these advanced materials have emerged and most of them have been solved (exemple : Ge lateral diffusion) ▪ In addition to strained and Ge-based materials, the choice of the silicide/germanide contact material in itself, as well as the associated salicide process, are key areas for further performance enhancement (interface engineering, dual silicide approach…)","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128911126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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