Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690553
C. Sabatier, S. Rack, Hervé Beseaucele, J. Venturini, T. Hoffmann, E. Rosseel, J. Steenbergen
As microelectronic Power Devices increase their performances, there is a need to implement low thermal budget annealing processes on thin silicon wafers, typically few tenth of micron thick. To enhance the performance of these devices, particularly for Insulated Gate Bipolar Transistor (IGBT), there is a need to activate two different layers of doped silicon at different depth from the backside of the wafers, one P-doped and another N-doped (buffer layer). These annealing processes have to be able to localize a high temperature heat front limited to a very thin layer not to damage the other side of the wafer, where metallic structures would not allow temperature above 400°C. In this work, we annealed wafers implanted with Boron and Phosphorous with Excico Long Pulse Exciplex laser (308nm excimer laser, 180ns pulse) to induce two different silicon phases where both a liquid and a solid phase process activate the 2 different dopant layers. SIMS and SRP measurements were performed to quantify the amount of dopant activated during the laser annealing. The rate of defects in the silicon was measured by RBS. Depending on the laser energy density and implantation conditions, we were able to identify a process window within we achieve a high activation rate of Boron in the melting phase and of the Phosphorus in the solid phase.
{"title":"Laser annealing of double implanted layers for IGBT Power Devices","authors":"C. Sabatier, S. Rack, Hervé Beseaucele, J. Venturini, T. Hoffmann, E. Rosseel, J. Steenbergen","doi":"10.1109/RTP.2008.4690553","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690553","url":null,"abstract":"As microelectronic Power Devices increase their performances, there is a need to implement low thermal budget annealing processes on thin silicon wafers, typically few tenth of micron thick. To enhance the performance of these devices, particularly for Insulated Gate Bipolar Transistor (IGBT), there is a need to activate two different layers of doped silicon at different depth from the backside of the wafers, one P-doped and another N-doped (buffer layer). These annealing processes have to be able to localize a high temperature heat front limited to a very thin layer not to damage the other side of the wafer, where metallic structures would not allow temperature above 400°C. In this work, we annealed wafers implanted with Boron and Phosphorous with Excico Long Pulse Exciplex laser (308nm excimer laser, 180ns pulse) to induce two different silicon phases where both a liquid and a solid phase process activate the 2 different dopant layers. SIMS and SRP measurements were performed to quantify the amount of dopant activated during the laser annealing. The rate of defects in the silicon was measured by RBS. Depending on the laser energy density and implantation conditions, we were able to identify a process window within we achieve a high activation rate of Boron in the melting phase and of the Phosphorus in the solid phase.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115183116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690548
M. Popadic, L. Nanver, C. Biasotto, V. Gonda, J. van der Cingel
Reduced pressure CVD of arsenic has been investigated as a source of dopants in combination with excimer laser annealing (LA). Energy densities used for LA are above the Si melt limit and abrupt, highly doped, nearly defect-free, ultrashallow junctions have been formed. The junction depth is determined by the melt depth and is independent of the doping level, which is determined by the As deposition. Multiple LA of the surface deposited As layer was performed to yield improved uniformity while multiple cycles of As deposition plus LA have been performed to yield a higher dose and consequently lower sheet resistance, which in the case of three depositions drops to around 80 Ω/sq for layers of an estimated depth of less than 20 nm. Near-ideal diode characteristics have been measured.
{"title":"Ultrashallow doping by excimer laser drive-in of RPCVD surface deposited arsenic monolayers","authors":"M. Popadic, L. Nanver, C. Biasotto, V. Gonda, J. van der Cingel","doi":"10.1109/RTP.2008.4690548","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690548","url":null,"abstract":"Reduced pressure CVD of arsenic has been investigated as a source of dopants in combination with excimer laser annealing (LA). Energy densities used for LA are above the Si melt limit and abrupt, highly doped, nearly defect-free, ultrashallow junctions have been formed. The junction depth is determined by the melt depth and is independent of the doping level, which is determined by the As deposition. Multiple LA of the surface deposited As layer was performed to yield improved uniformity while multiple cycles of As deposition plus LA have been performed to yield a higher dose and consequently lower sheet resistance, which in the case of three depositions drops to around 80 Ω/sq for layers of an estimated depth of less than 20 nm. Near-ideal diode characteristics have been measured.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121924218","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690566
E. Granneman, X. Pagès, K. Vanormelingen, P. Vermont
In conduction-based RTP systems the heating relies on the conduction of energy through a thin gas layer of gas between the wafer and the surrounding chamber walls. In most of these types of systems a gas flow is used to control the heating ambient. It turns out that the pressure drop in the system is a direct measure of the wafer temperature. This principle is used to determine the wafer temperature in the Levitor system. With this method, temperature measurements can be carried out in the range 200–1100°C. The absolute accuracy and repeatability in steady state (i.e. long processing times) is 4°C and 1.5°C (1σ), respectively. The time resolution is in the ms range. Transient phenomena that influence the measurements in short anneal processes are discussed in detail, and procedures are given to correct for such effects.
{"title":"Wafer temperature measurement in conduction-based RTP systems","authors":"E. Granneman, X. Pagès, K. Vanormelingen, P. Vermont","doi":"10.1109/RTP.2008.4690566","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690566","url":null,"abstract":"In conduction-based RTP systems the heating relies on the conduction of energy through a thin gas layer of gas between the wafer and the surrounding chamber walls. In most of these types of systems a gas flow is used to control the heating ambient. It turns out that the pressure drop in the system is a direct measure of the wafer temperature. This principle is used to determine the wafer temperature in the Levitor system. With this method, temperature measurements can be carried out in the range 200–1100°C. The absolute accuracy and repeatability in steady state (i.e. long processing times) is 4°C and 1.5°C (1σ), respectively. The time resolution is in the ms range. Transient phenomena that influence the measurements in short anneal processes are discussed in detail, and procedures are given to correct for such effects.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131813153","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690549
H. Maynard, C. Hatem, H. Gossmann, Y. Erokhin, N. Variam, Shaoyin Chen, Yun Wang
Strain engineering has become a workhorse in increasing charge carrier mobility to boost performance for sub-45nm CMOS logic technologies. While pFET transistors with embedded Si1−xGex layers in the S/D region have been widely employed to induce compressive strain in the silicon channel, nFET transistors have mostly depended on either tensile liners or stress memorization techniques (SMT) to introduce tensile strain. Recently, there have been reports on the use of Si:C in the nFET S/D enhancing transistor performance. In this paper we discuss results from novel ion implantation schemes employed to maximize carbon incorporation and to achieve defect free, strained Si:C layers. In addition, high activation of the dopant is maintained even in the presence of relatively high carbon incorporation. Several anneal techniques including SPE anneal, spike RTP, and laser spike anneals have been used to optimize carbon incorporation, strain and activation. Results from these different anneal techniques will be compared and discussed.
{"title":"Enhancing tensile stress and source/drain activation with Si:C with innovations in ion implant and millisecond laser spike annealing","authors":"H. Maynard, C. Hatem, H. Gossmann, Y. Erokhin, N. Variam, Shaoyin Chen, Yun Wang","doi":"10.1109/RTP.2008.4690549","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690549","url":null,"abstract":"Strain engineering has become a workhorse in increasing charge carrier mobility to boost performance for sub-45nm CMOS logic technologies. While pFET transistors with embedded Si1−xGex layers in the S/D region have been widely employed to induce compressive strain in the silicon channel, nFET transistors have mostly depended on either tensile liners or stress memorization techniques (SMT) to introduce tensile strain. Recently, there have been reports on the use of Si:C in the nFET S/D enhancing transistor performance. In this paper we discuss results from novel ion implantation schemes employed to maximize carbon incorporation and to achieve defect free, strained Si:C layers. In addition, high activation of the dopant is maintained even in the presence of relatively high carbon incorporation. Several anneal techniques including SPE anneal, spike RTP, and laser spike anneals have been used to optimize carbon incorporation, strain and activation. Results from these different anneal techniques will be compared and discussed.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114436704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690539
P. Timans, Y. Z. Hu, Y. Lee, J. Gelpey, S. Mccoy, W. Lerch, S. Paul, D. Bolze, H. Kheyrandish, J. Reyes, S. Prussin
Advances in CMOS technology require continuous reductions in the thermal budget employed for activating ion implanted dopants. However, low thermal budget annealing approaches, such as millisecond annealing, must also remove implant damage to minimize junction leakage. This paper explores the trade-offs between dopant diffusion, electrical activation and damage annealing for ultra-shallow junctions (USJ) formed by low energy B implants into both crystalline and pre-amorphized silicon. The study also addressed how low-thermal budget annealing affects the use of strong halo-style doping from As implants. Several annealing methods were studied, with the main focus on flash-assisted RTP™ (fRTP™) at temperatures between 1250°C and 1350°C. Activation was assessed with RsL™ non-contact measurements and Hg-probe four point-probe sheet resistance measurements, as well as a continuous anodic oxidation technique for depth profiling of carrier concentrations and mobility. Residual damage was assessed by photoluminescence, thermal wave studies, optical reflectance and RsL junction leakage current measurements. fRTP effectively activates high-dose, low-energy B implants, while limiting the diffusion to a few nm of profile movement. The limited thermal budget of millisecond annealing reduces, but does not fully eliminate, implant damage from heavy ions implanted at high energy, although very high process temperatures, e.g. ∼1300°C, are more effective in this regard. Strong halo doping greatly increases the junction leakage and for future device nodes it will be important to reduce implantation damage from both USJ and halo implants. Non-invasive damage metrology can help rapid optimization of implantation and annealing conditions. Such measurements will be even more useful when quantitative models can accurately link them to doping and damage profiles.
{"title":"Optimization of diffusion, activation and damage annealing in millisecond annealing","authors":"P. Timans, Y. Z. Hu, Y. Lee, J. Gelpey, S. Mccoy, W. Lerch, S. Paul, D. Bolze, H. Kheyrandish, J. Reyes, S. Prussin","doi":"10.1109/RTP.2008.4690539","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690539","url":null,"abstract":"Advances in CMOS technology require continuous reductions in the thermal budget employed for activating ion implanted dopants. However, low thermal budget annealing approaches, such as millisecond annealing, must also remove implant damage to minimize junction leakage. This paper explores the trade-offs between dopant diffusion, electrical activation and damage annealing for ultra-shallow junctions (USJ) formed by low energy B implants into both crystalline and pre-amorphized silicon. The study also addressed how low-thermal budget annealing affects the use of strong halo-style doping from As implants. Several annealing methods were studied, with the main focus on flash-assisted RTP™ (fRTP™) at temperatures between 1250°C and 1350°C. Activation was assessed with RsL™ non-contact measurements and Hg-probe four point-probe sheet resistance measurements, as well as a continuous anodic oxidation technique for depth profiling of carrier concentrations and mobility. Residual damage was assessed by photoluminescence, thermal wave studies, optical reflectance and RsL junction leakage current measurements. fRTP effectively activates high-dose, low-energy B implants, while limiting the diffusion to a few nm of profile movement. The limited thermal budget of millisecond annealing reduces, but does not fully eliminate, implant damage from heavy ions implanted at high energy, although very high process temperatures, e.g. ∼1300°C, are more effective in this regard. Strong halo doping greatly increases the junction leakage and for future device nodes it will be important to reduce implantation damage from both USJ and halo implants. Non-invasive damage metrology can help rapid optimization of implantation and annealing conditions. Such measurements will be even more useful when quantitative models can accurately link them to doping and damage profiles.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129180367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690537
M. Current, J. Borland
New metrologies for process characterization of annealing for dopant activation in CMOS transistors now include 4-point probes with probe spacing on the micron scale as well as non-contact methods using optical excitation of carriers for measurements of sheet resistance, leakage currents and various indications of the effects of carrier recombination at residual defects. In addition, optical methods have been extended to characterize the effects of annealing and film growth on local strain as measured by bow, site flatness and Raman spectroscopy. These new metrologies allow characterization of anneal process variations across whole wafers to the sub-mm scale and beyond for Rapid Process Optimization.
{"title":"New metrologies for annealing of USJs and thin films","authors":"M. Current, J. Borland","doi":"10.1109/RTP.2008.4690537","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690537","url":null,"abstract":"New metrologies for process characterization of annealing for dopant activation in CMOS transistors now include 4-point probes with probe spacing on the micron scale as well as non-contact methods using optical excitation of carriers for measurements of sheet resistance, leakage currents and various indications of the effects of carrier recombination at residual defects. In addition, optical methods have been extended to characterize the effects of annealing and film growth on local strain as measured by bow, site flatness and Raman spectroscopy. These new metrologies allow characterization of anneal process variations across whole wafers to the sub-mm scale and beyond for Rapid Process Optimization.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121727561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690562
C. Wundisch, M. Posselt, W. Anwand, B. Schmidt, A. Mucklich, W. Skorupa, T. Clarysse, E. Simoen
The formation of ultra-shallow n+ layers by P or As implantation and subsequent rapid thermal annealing (RTA) or flash-lamp annealing (FLA) is investigated. The focus is on diffusion and activation of dopants. RTA leads to considerable broadening of the shallow as-implanted profiles by concentration-dependent diffusion. In contrast, FLA does not cause any diffusion and is therefore a promising method for producing ultra-shallow n+p junctions in Ge. Under present annealing conditions RTA yields maximum activation levels of about 1.1E19 and 6.5E18 cm−3 for P and As, respectively. The maximum activation achieved by FLA is about 4.0E19 and 2.1E19 cm−3 for P and As, respectively. Possible mechanisms for diffusion and deactivation of dopants are discussed.
{"title":"RTA and FLA of ultra-shallow implanted layers in Ge","authors":"C. Wundisch, M. Posselt, W. Anwand, B. Schmidt, A. Mucklich, W. Skorupa, T. Clarysse, E. Simoen","doi":"10.1109/RTP.2008.4690562","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690562","url":null,"abstract":"The formation of ultra-shallow n+ layers by P or As implantation and subsequent rapid thermal annealing (RTA) or flash-lamp annealing (FLA) is investigated. The focus is on diffusion and activation of dopants. RTA leads to considerable broadening of the shallow as-implanted profiles by concentration-dependent diffusion. In contrast, FLA does not cause any diffusion and is therefore a promising method for producing ultra-shallow n+p junctions in Ge. Under present annealing conditions RTA yields maximum activation levels of about 1.1E19 and 6.5E18 cm−3 for P and As, respectively. The maximum activation achieved by FLA is about 4.0E19 and 2.1E19 cm−3 for P and As, respectively. Possible mechanisms for diffusion and deactivation of dopants are discussed.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690554
R. Beneyton, A. Colin, H. Bono, F. Cacho, M. Bidaud, B. Dumont, P. Morin, K. Barla
Local thermal variation occurring during light enhanced rapid thermal process (RTP) and millisecond anneals called “pattern effects” have various origin, with more or less impact as function of the used process. The main issues concern the variation of thermal conductivity and the variation of the light absorption by optical interference or diffraction effects. In this paper, a large panel of experiments is described in order to put in evidence the various root causes previously mentioned and their magnitudes are also determined as function of the used process. Experiments were done on full sheet wafer for all phenomena regarding stacked layers and specific patterned structure or full flow wafer are used to evaluate the impact of pattern on temperature variation. Theoretical computation by finite element methodology (FEM) allows a comparison with the experimental results. Thanks to all our results some ways for intradie dispersion reduction will be considered.
{"title":"Origin of local temperature variation during spike anneal and millisecond anneal","authors":"R. Beneyton, A. Colin, H. Bono, F. Cacho, M. Bidaud, B. Dumont, P. Morin, K. Barla","doi":"10.1109/RTP.2008.4690554","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690554","url":null,"abstract":"Local thermal variation occurring during light enhanced rapid thermal process (RTP) and millisecond anneals called “pattern effects” have various origin, with more or less impact as function of the used process. The main issues concern the variation of thermal conductivity and the variation of the light absorption by optical interference or diffraction effects. In this paper, a large panel of experiments is described in order to put in evidence the various root causes previously mentioned and their magnitudes are also determined as function of the used process. Experiments were done on full sheet wafer for all phenomena regarding stacked layers and specific patterned structure or full flow wafer are used to evaluate the impact of pattern on temperature variation. Theoretical computation by finite element methodology (FEM) allows a comparison with the experimental results. Thanks to all our results some ways for intradie dispersion reduction will be considered.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690535
T. Feudel, M. Horstmann
SOI technology is leading edge for high performance microprocessors. Performance per Watt is key and multiple core devices and their improved functionality are required to keep power comsumption low. AMD runs a unique transistor node to node progression model which devlivers at all times top notch performance from technology and lowers risk when moving to next technology generation. AMD gained leadership on strained Si and multi stressor integration. In a very mature state already DSL, SMT and SiGe. Besides stressors, advanced anneal is important to reduce diffusion and asymmetric device will help transistor performance. Reduction of parametric scattering is especially important for 45nm/32nm technology nodes. A special in-die measurement method has been developed to assess scattering in a thorough statistical way. Existing stressors like DSL, SMT, SiGe fully scale to 45nm pitches. HK/MG materials are the key for 32nm to keep GOX leakage under control and to allow gate scaling again.
{"title":"Recent advances in stress and activation engineering for high-performance logic transistors","authors":"T. Feudel, M. Horstmann","doi":"10.1109/RTP.2008.4690535","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690535","url":null,"abstract":"SOI technology is leading edge for high performance microprocessors. Performance per Watt is key and multiple core devices and their improved functionality are required to keep power comsumption low. AMD runs a unique transistor node to node progression model which devlivers at all times top notch performance from technology and lowers risk when moving to next technology generation. AMD gained leadership on strained Si and multi stressor integration. In a very mature state already DSL, SMT and SiGe. Besides stressors, advanced anneal is important to reduce diffusion and asymmetric device will help transistor performance. Reduction of parametric scattering is especially important for 45nm/32nm technology nodes. A special in-die measurement method has been developed to assess scattering in a thorough statistical way. Existing stressors like DSL, SMT, SiGe fully scale to 45nm pitches. HK/MG materials are the key for 32nm to keep GOX leakage under control and to allow gate scaling again.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690567
B. Lojek, H. Geiler
The study of the effects of microwave annealing of ion-implanted layers in silicon substrate evaluated by photo-thermal technique is reported. The technique allows nondestructive and fast characterization of the annihilation processes of damage layer defects as a function of microwave annealing conditions. The preliminary data are suggesting that the microwave field is affecting damaged and heavily doped regions, the remaining undamaged region of the semiconductor wafer is essentially transparent to the electromagnetic waves in the GHz wave range.
{"title":"Investigation of microwave annealed implanted layers with TWIN metrology system","authors":"B. Lojek, H. Geiler","doi":"10.1109/RTP.2008.4690567","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690567","url":null,"abstract":"The study of the effects of microwave annealing of ion-implanted layers in silicon substrate evaluated by photo-thermal technique is reported. The technique allows nondestructive and fast characterization of the annihilation processes of damage layer defects as a function of microwave annealing conditions. The preliminary data are suggesting that the microwave field is affecting damaged and heavily doped regions, the remaining undamaged region of the semiconductor wafer is essentially transparent to the electromagnetic waves in the GHz wave range.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121827722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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