Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690562
C. Wundisch, M. Posselt, W. Anwand, B. Schmidt, A. Mucklich, W. Skorupa, T. Clarysse, E. Simoen
The formation of ultra-shallow n+ layers by P or As implantation and subsequent rapid thermal annealing (RTA) or flash-lamp annealing (FLA) is investigated. The focus is on diffusion and activation of dopants. RTA leads to considerable broadening of the shallow as-implanted profiles by concentration-dependent diffusion. In contrast, FLA does not cause any diffusion and is therefore a promising method for producing ultra-shallow n+p junctions in Ge. Under present annealing conditions RTA yields maximum activation levels of about 1.1E19 and 6.5E18 cm−3 for P and As, respectively. The maximum activation achieved by FLA is about 4.0E19 and 2.1E19 cm−3 for P and As, respectively. Possible mechanisms for diffusion and deactivation of dopants are discussed.
{"title":"RTA and FLA of ultra-shallow implanted layers in Ge","authors":"C. Wundisch, M. Posselt, W. Anwand, B. Schmidt, A. Mucklich, W. Skorupa, T. Clarysse, E. Simoen","doi":"10.1109/RTP.2008.4690562","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690562","url":null,"abstract":"The formation of ultra-shallow n+ layers by P or As implantation and subsequent rapid thermal annealing (RTA) or flash-lamp annealing (FLA) is investigated. The focus is on diffusion and activation of dopants. RTA leads to considerable broadening of the shallow as-implanted profiles by concentration-dependent diffusion. In contrast, FLA does not cause any diffusion and is therefore a promising method for producing ultra-shallow n+p junctions in Ge. Under present annealing conditions RTA yields maximum activation levels of about 1.1E19 and 6.5E18 cm−3 for P and As, respectively. The maximum activation achieved by FLA is about 4.0E19 and 2.1E19 cm−3 for P and As, respectively. Possible mechanisms for diffusion and deactivation of dopants are discussed.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115721464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690554
R. Beneyton, A. Colin, H. Bono, F. Cacho, M. Bidaud, B. Dumont, P. Morin, K. Barla
Local thermal variation occurring during light enhanced rapid thermal process (RTP) and millisecond anneals called “pattern effects” have various origin, with more or less impact as function of the used process. The main issues concern the variation of thermal conductivity and the variation of the light absorption by optical interference or diffraction effects. In this paper, a large panel of experiments is described in order to put in evidence the various root causes previously mentioned and their magnitudes are also determined as function of the used process. Experiments were done on full sheet wafer for all phenomena regarding stacked layers and specific patterned structure or full flow wafer are used to evaluate the impact of pattern on temperature variation. Theoretical computation by finite element methodology (FEM) allows a comparison with the experimental results. Thanks to all our results some ways for intradie dispersion reduction will be considered.
{"title":"Origin of local temperature variation during spike anneal and millisecond anneal","authors":"R. Beneyton, A. Colin, H. Bono, F. Cacho, M. Bidaud, B. Dumont, P. Morin, K. Barla","doi":"10.1109/RTP.2008.4690554","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690554","url":null,"abstract":"Local thermal variation occurring during light enhanced rapid thermal process (RTP) and millisecond anneals called “pattern effects” have various origin, with more or less impact as function of the used process. The main issues concern the variation of thermal conductivity and the variation of the light absorption by optical interference or diffraction effects. In this paper, a large panel of experiments is described in order to put in evidence the various root causes previously mentioned and their magnitudes are also determined as function of the used process. Experiments were done on full sheet wafer for all phenomena regarding stacked layers and specific patterned structure or full flow wafer are used to evaluate the impact of pattern on temperature variation. Theoretical computation by finite element methodology (FEM) allows a comparison with the experimental results. Thanks to all our results some ways for intradie dispersion reduction will be considered.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"07 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128946386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690535
T. Feudel, M. Horstmann
SOI technology is leading edge for high performance microprocessors. Performance per Watt is key and multiple core devices and their improved functionality are required to keep power comsumption low. AMD runs a unique transistor node to node progression model which devlivers at all times top notch performance from technology and lowers risk when moving to next technology generation. AMD gained leadership on strained Si and multi stressor integration. In a very mature state already DSL, SMT and SiGe. Besides stressors, advanced anneal is important to reduce diffusion and asymmetric device will help transistor performance. Reduction of parametric scattering is especially important for 45nm/32nm technology nodes. A special in-die measurement method has been developed to assess scattering in a thorough statistical way. Existing stressors like DSL, SMT, SiGe fully scale to 45nm pitches. HK/MG materials are the key for 32nm to keep GOX leakage under control and to allow gate scaling again.
{"title":"Recent advances in stress and activation engineering for high-performance logic transistors","authors":"T. Feudel, M. Horstmann","doi":"10.1109/RTP.2008.4690535","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690535","url":null,"abstract":"SOI technology is leading edge for high performance microprocessors. Performance per Watt is key and multiple core devices and their improved functionality are required to keep power comsumption low. AMD runs a unique transistor node to node progression model which devlivers at all times top notch performance from technology and lowers risk when moving to next technology generation. AMD gained leadership on strained Si and multi stressor integration. In a very mature state already DSL, SMT and SiGe. Besides stressors, advanced anneal is important to reduce diffusion and asymmetric device will help transistor performance. Reduction of parametric scattering is especially important for 45nm/32nm technology nodes. A special in-die measurement method has been developed to assess scattering in a thorough statistical way. Existing stressors like DSL, SMT, SiGe fully scale to 45nm pitches. HK/MG materials are the key for 32nm to keep GOX leakage under control and to allow gate scaling again.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124495516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690560
A. La Magna, G. Fisicaro, G. Mannino, V. Privitera, G. Piccitto, L. Vines, B. Svensson
A modeling approach is formalized and implemented to investigate the kinetics of the defects-dopant system in the extremely far-from-the equilibrium conditions induced by laser irradiation of Si. The master equations for the evolution of the defect-impurity system is rigorously obtained starting from the Boltzmann’s formalism. The formalism allows to simulate beyond the hypothesis of instantaneous equilibration of the local system energy to the lattice thermal field. Comparisons between simulations and experimental analysis of the processes are discussed. These results indicate the general reliability of the Si self-interstitial clusters energetic derived using conventional thermal processes. The impact of the formalism for other non-conventional annealing techniques is discussed.
{"title":"Thermal and non-thermal kinetics of defects and dopant in Si","authors":"A. La Magna, G. Fisicaro, G. Mannino, V. Privitera, G. Piccitto, L. Vines, B. Svensson","doi":"10.1109/RTP.2008.4690560","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690560","url":null,"abstract":"A modeling approach is formalized and implemented to investigate the kinetics of the defects-dopant system in the extremely far-from-the equilibrium conditions induced by laser irradiation of Si. The master equations for the evolution of the defect-impurity system is rigorously obtained starting from the Boltzmann’s formalism. The formalism allows to simulate beyond the hypothesis of instantaneous equilibration of the local system energy to the lattice thermal field. Comparisons between simulations and experimental analysis of the processes are discussed. These results indicate the general reliability of the Si self-interstitial clusters energetic derived using conventional thermal processes. The impact of the formalism for other non-conventional annealing techniques is discussed.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121138912","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690545
B. Adams
RTP emerged as a mainstream technology during the last two decades in part by solving a difficult technical challenge, that of reliable temperature measurement using optical thermometry. Current thermal processing chambers are capable of controlling temperatures which change at hundreds of degrees celsius per second with repeatability of less than one degree with uniformity on the order of a degree. This is accomplished in a radiatively heated environment where the optical properties of the substrate may vary arbitrarily and contact with it is not acceptable or even feasible. This high degree of thermal stability has enabled the production of the current generation of integrated circuits. Processing requirements are pushing the limits of traditional lamp based technology, and new techniques for sub-second anneals are starting to emerge. With the development of the sub-second anneal, temperature heating and cooling rates may exceed millions of degrees per second, and temperature control may become the limiting factor as it was in the early days of the evolution of the industry.
{"title":"Temperature measurement in RTP: Past and future","authors":"B. Adams","doi":"10.1109/RTP.2008.4690545","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690545","url":null,"abstract":"RTP emerged as a mainstream technology during the last two decades in part by solving a difficult technical challenge, that of reliable temperature measurement using optical thermometry. Current thermal processing chambers are capable of controlling temperatures which change at hundreds of degrees celsius per second with repeatability of less than one degree with uniformity on the order of a degree. This is accomplished in a radiatively heated environment where the optical properties of the substrate may vary arbitrarily and contact with it is not acceptable or even feasible. This high degree of thermal stability has enabled the production of the current generation of integrated circuits. Processing requirements are pushing the limits of traditional lamp based technology, and new techniques for sub-second anneals are starting to emerge. With the development of the sub-second anneal, temperature heating and cooling rates may exceed millions of degrees per second, and temperature control may become the limiting factor as it was in the early days of the evolution of the industry.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130675503","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690544
J. Everaert, G. Zschatzsch, G. Vecchio, W. Vandervorst, L. Cunnane
We show that accurate mass metrology can determine how dopants are added or material is removed during the plasma doping process. In case of erosion, information of mass reduction rate and selectivity can be obtained. Although deposition and erosion can occur simultaneous with implantation, a method is presented how to distinguish these basic reactions. Mass monitoring before and after anneal, reveals that As is very volatile. In the search for a solution we present a post treatment which reduces this loss, hence achieving lower sheet resistance.
{"title":"Plasma doping control by mass metrology","authors":"J. Everaert, G. Zschatzsch, G. Vecchio, W. Vandervorst, L. Cunnane","doi":"10.1109/RTP.2008.4690544","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690544","url":null,"abstract":"We show that accurate mass metrology can determine how dopants are added or material is removed during the plasma doping process. In case of erosion, information of mass reduction rate and selectivity can be obtained. Although deposition and erosion can occur simultaneous with implantation, a method is presented how to distinguish these basic reactions. Mass monitoring before and after anneal, reveals that As is very volatile. In the search for a solution we present a post treatment which reduces this loss, hence achieving lower sheet resistance.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123436785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690534
Jungwoo Oh, P. Majhi, R. Jammy
• Ge based channels appear promising for high mobility pMOSFETs - Need for module level (epi, gate stack, junctions, contacts) optimization as demonstrated • Demonstrated additivity of strain (uniaxial) to the mobility of Ge based channels • Several challenges remain but exciting opportunities for focused research (academic and industry collaboration)
{"title":"High mobility and advanced channels materials","authors":"Jungwoo Oh, P. Majhi, R. Jammy","doi":"10.1109/RTP.2008.4690534","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690534","url":null,"abstract":"• Ge based channels appear promising for high mobility pMOSFETs - Need for module level (epi, gate stack, junctions, contacts) optimization as demonstrated • Demonstrated additivity of strain (uniaxial) to the mobility of Ge based channels • Several challenges remain but exciting opportunities for focused research (academic and industry collaboration)","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129227473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690561
K. Yako, Toyoji Yamamoto, K. Uejima, T. Ikezawa, M. Hane
We designed and fabricated sub-30 nm gate length pMOSFETs developing the raised source/drain extension (RSDext) process. Our process features usages of cluster-ion (B18H22) implantation and high-temperature millisecond annealing processes and a facet-structure-control of the RSDext of less than 10 nm thickness for suppressing a fringe capacitance increase for the “effective” ultra-shallower junction formation. As the results, experimentally obtained our pMOSFETs with raised source/drain extension show almost the same LMIN, 1/2 times lower parasitic resistance and lower junction leakage.
{"title":"Parasitic resistance and leakage reduction by raised source / drain extention fabricated with cluster ion implantation and millisecond annealing","authors":"K. Yako, Toyoji Yamamoto, K. Uejima, T. Ikezawa, M. Hane","doi":"10.1109/RTP.2008.4690561","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690561","url":null,"abstract":"We designed and fabricated sub-30 nm gate length pMOSFETs developing the raised source/drain extension (RSDext) process. Our process features usages of cluster-ion (B18H22) implantation and high-temperature millisecond annealing processes and a facet-structure-control of the RSDext of less than 10 nm thickness for suppressing a fringe capacitance increase for the “effective” ultra-shallower junction formation. As the results, experimentally obtained our pMOSFETs with raised source/drain extension show almost the same LMIN, 1/2 times lower parasitic resistance and lower junction leakage.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129043130","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690557
D. Ceperley, A. Neureuther, A. Hawryluk, Xiaoru Wang, M. Shen, Yun Wang
Finite difference time domain simulation of the electromagnetic coupling in millisecond radiation heating is used to explore how the energy couples, where it goes in the device structure, and wavelength dependencies. Millisecond annealing is advantageous for improving IC device characteristics; however, the application of short time scale annealing requires very careful control over the localized heating that can be pattern, device structure, and material dependent. The presence of metal gate structure introduces extra complexity. This paper considers the case of tungsten gates on poly-silicon pedestals with or without silicon nitride caps. Rigorous finite difference time domain techniques are used to compute the fields throughout the device structure as a function of polarization, angle of incidence, wavelength, CD, and pitch. One of the dominant effects is that a grating formed by a metal gate array acts like a polarizer. Thus the coupling changes with grating orientation. The coupling is the strongest when the incident plane is perpendicular to the gate and the electric field is p-polarized. In the case of laser light with a 10 μm wavelength incident near silicon’s Brewster angle, the absorptivity approaches 100% just as if the tungsten metal gates do not exist. Data from similar studies at shorter wavelengths is also presented as well as a comparison with experimental measurements.
{"title":"Wavelength and polarization dependent absorbtion effects in millisecond annealing of metal gate structures","authors":"D. Ceperley, A. Neureuther, A. Hawryluk, Xiaoru Wang, M. Shen, Yun Wang","doi":"10.1109/RTP.2008.4690557","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690557","url":null,"abstract":"Finite difference time domain simulation of the electromagnetic coupling in millisecond radiation heating is used to explore how the energy couples, where it goes in the device structure, and wavelength dependencies. Millisecond annealing is advantageous for improving IC device characteristics; however, the application of short time scale annealing requires very careful control over the localized heating that can be pattern, device structure, and material dependent. The presence of metal gate structure introduces extra complexity. This paper considers the case of tungsten gates on poly-silicon pedestals with or without silicon nitride caps. Rigorous finite difference time domain techniques are used to compute the fields throughout the device structure as a function of polarization, angle of incidence, wavelength, CD, and pitch. One of the dominant effects is that a grating formed by a metal gate array acts like a polarizer. Thus the coupling changes with grating orientation. The coupling is the strongest when the incident plane is perpendicular to the gate and the electric field is p-polarized. In the case of laser light with a 10 μm wavelength incident near silicon’s Brewster angle, the absorptivity approaches 100% just as if the tungsten metal gates do not exist. Data from similar studies at shorter wavelengths is also presented as well as a comparison with experimental measurements.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133193584","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-02DOI: 10.1109/RTP.2008.4690550
J. Mcwhirter, D. Gaines, P. Zambon
For the successful implementation of any advanced annealing system in a production environment, real-time measurement and control of wafer peak temperature is critical. For sub-millisecond laser anneal (SMA), the uniformity and repeatability of wafer peak temperature is limited by a variety of local and global effects. Two examples are variations in substrate temperature, and optical power fluctuations which are primarily caused by changes in the transmittance of the beam delivery system. We report on characterization and temperature uniformity performance of a laser spike anneal (LSA) system utilizing a closed loop feedback control system based on thermal emission from the local anneal site. We also report on the results of a characterization of a silicon wafer’s thermal response to temporal variations in incident optical power. Finally, we show that a properly designed measurement and control system enables the achievement of uniform and repeatable peak anneal temperatures.
{"title":"Emission feedback control system for sub-millisecond laser spike anneal","authors":"J. Mcwhirter, D. Gaines, P. Zambon","doi":"10.1109/RTP.2008.4690550","DOIUrl":"https://doi.org/10.1109/RTP.2008.4690550","url":null,"abstract":"For the successful implementation of any advanced annealing system in a production environment, real-time measurement and control of wafer peak temperature is critical. For sub-millisecond laser anneal (SMA), the uniformity and repeatability of wafer peak temperature is limited by a variety of local and global effects. Two examples are variations in substrate temperature, and optical power fluctuations which are primarily caused by changes in the transmittance of the beam delivery system. We report on characterization and temperature uniformity performance of a laser spike anneal (LSA) system utilizing a closed loop feedback control system based on thermal emission from the local anneal site. We also report on the results of a characterization of a silicon wafer’s thermal response to temporal variations in incident optical power. Finally, we show that a properly designed measurement and control system enables the achievement of uniform and repeatable peak anneal temperatures.","PeriodicalId":317927,"journal":{"name":"2008 16th IEEE International Conference on Advanced Thermal Processing of Semiconductors","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-12-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131674189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：