Pub Date : 2019-10-01DOI: 10.1109/asicon47005.2019.8983628
Y. Sheng, Xinyu Chen, Fuyou Liao, Jianan Deng, J. Wan, W. Bao
MoS2 phototransistor has been widely investigated for its high sensitivity to light ranging from visible to near-infrared owing to the layer-dependent bandgap of MoS2. However, most of the devices in the previous studies employed a back-gate device structure, which limits its future practical application. Here, we take advantage of the high transparency of atomically thin graphene membrane to propose a top-gate phototransistor structure, in which the graphene acts as the top-gate electrode. Such MoS2 photodetector exhibits ultrahigh responsivity reaching 1.4×105 AW−1 under the 550 nm incident light. The spectral response is also studied under the illumination of wavelength from 300 nm to 1000 nm. Other factors correlated with the lifetime of photogenerated carriers, including source-drain bias, gate bias, incident light intensity, are also systematically investigated.
{"title":"Graphene Top-gated Mos2 Phototransistors","authors":"Y. Sheng, Xinyu Chen, Fuyou Liao, Jianan Deng, J. Wan, W. Bao","doi":"10.1109/asicon47005.2019.8983628","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983628","url":null,"abstract":"MoS2 phototransistor has been widely investigated for its high sensitivity to light ranging from visible to near-infrared owing to the layer-dependent bandgap of MoS2. However, most of the devices in the previous studies employed a back-gate device structure, which limits its future practical application. Here, we take advantage of the high transparency of atomically thin graphene membrane to propose a top-gate phototransistor structure, in which the graphene acts as the top-gate electrode. Such MoS2 photodetector exhibits ultrahigh responsivity reaching 1.4×105 AW−1 under the 550 nm incident light. The spectral response is also studied under the illumination of wavelength from 300 nm to 1000 nm. Other factors correlated with the lifetime of photogenerated carriers, including source-drain bias, gate bias, incident light intensity, are also systematically investigated.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116031977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983542
Xubo Song, Yuangang Wang, Zhihong Feng, Y. Lv, Yamin Zhang, Lisen Zhang, S. Liang, X. Tan, S. Dun, Dabao Yang, Zhirong Zhang
We presented a GaN Schottky diode model with consideration of self-heating effect of devices in operation. The impact of diode chip temperature on the current and capacitance was taken into account in this model. The thermal resistance of diode chip was extracted by simulation combined measurement to calculate the temperature of Schottky junction with different pumping power. Advantages of established device model in the design of a 220GHz frequency doubler were presented in the end.
{"title":"GaN Schottky Diode Model for THz Multiplier Design with Consideration of Self-heating Effect","authors":"Xubo Song, Yuangang Wang, Zhihong Feng, Y. Lv, Yamin Zhang, Lisen Zhang, S. Liang, X. Tan, S. Dun, Dabao Yang, Zhirong Zhang","doi":"10.1109/ASICON47005.2019.8983542","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983542","url":null,"abstract":"We presented a GaN Schottky diode model with consideration of self-heating effect of devices in operation. The impact of diode chip temperature on the current and capacitance was taken into account in this model. The thermal resistance of diode chip was extracted by simulation combined measurement to calculate the temperature of Schottky junction with different pumping power. Advantages of established device model in the design of a 220GHz frequency doubler were presented in the end.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116308731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983446
Xiaozhi Kang, Xiaoxu Kang, Zijian Zhao, Jingxiu Ding, Yi Hu, Dapeng Xu, Qingqing Sun, D. Zhang
This paper describes an op-amp free low-dropout regulator with a high PSRR over a broad frequency range. The design merges the high PSRR bandgap and LDO without op-amp involved and thus greatly reduces the silicon area. As no high impedence node engaged in the circuit, it is easy to achieve a good high frequency PSRR performance by using a locally regulated supply voltage. The op-amp free LDO is then developed by embedding replica technique in the bandgap. The circuit is evaluated with HHGrace 0.35µm CMOS technology. It generates a reference voltage of 1.152V and has a temperature coefficient of 0.01mV/K at 27C. LDO has a PSRR of −96dB at DC and still −48.5dB at 1MHz.
{"title":"Low-Dropout Regulator design with a simple structure for good high frequency PSRR performance based on Bandgap Circuit","authors":"Xiaozhi Kang, Xiaoxu Kang, Zijian Zhao, Jingxiu Ding, Yi Hu, Dapeng Xu, Qingqing Sun, D. Zhang","doi":"10.1109/ASICON47005.2019.8983446","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983446","url":null,"abstract":"This paper describes an op-amp free low-dropout regulator with a high PSRR over a broad frequency range. The design merges the high PSRR bandgap and LDO without op-amp involved and thus greatly reduces the silicon area. As no high impedence node engaged in the circuit, it is easy to achieve a good high frequency PSRR performance by using a locally regulated supply voltage. The op-amp free LDO is then developed by embedding replica technique in the bandgap. The circuit is evaluated with HHGrace 0.35µm CMOS technology. It generates a reference voltage of 1.152V and has a temperature coefficient of 0.01mV/K at 27C. LDO has a PSRR of −96dB at DC and still −48.5dB at 1MHz.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123514097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Automatic hardware design is currently drawing research attentions as it has the potential to free designers from low level manual design process. In this paper, we propose an automatic hardware design tool, which is able to automatically perform reusing transformation on circuits. With the number of available computation modules as input, the proposed hardware design tool automatically designs circuit and generates corresponding register transfer level (RTL) codes in term of Verilog HDL. Our FPGA implementation results show that this design tool can efficiently perform resource planning according to user specifications.
{"title":"Automatic Hardware Design Tool Based on Reusing Transformation","authors":"Chongzhou Fang, Zaichen Zhang, X. You, Chuan Zhang","doi":"10.1109/ASICON47005.2019.8983487","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983487","url":null,"abstract":"Automatic hardware design is currently drawing research attentions as it has the potential to free designers from low level manual design process. In this paper, we propose an automatic hardware design tool, which is able to automatically perform reusing transformation on circuits. With the number of available computation modules as input, the proposed hardware design tool automatically designs circuit and generates corresponding register transfer level (RTL) codes in term of Verilog HDL. Our FPGA implementation results show that this design tool can efficiently perform resource planning according to user specifications.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983498
Xuefeng Ye, D. Zeng, Xiangliang Jin, Yang Wang
In this paper, a bandgap voltage reference (BGR) with a low temperature coefficient, used for readout circuits of SPAD, has been designed and fabricated successfully in the standard MXIC 0.5µm 1P3M CMOS process. The area of the core circuit occupies 244×215µm2. The test results show that the designed bandgap reference could work normally under the power supply voltage of 2.8V to 8V with a line regulation (LNR) of 0.0096%. At room temperature (25°C), the stable reference output voltage is 1.168V. The reference voltage varies by only 1.8mV within the temperature range of 0~150°C, and leads to a temperature coefficient of 10.28ppm/°C. Under the power supply of 5V, the BGR chip exhibits a power supply rejection ratio (PSRR) of 76.4dB at 1KHz.
{"title":"A Low-Temperature-Coefficient and High-PSRR Bandgap Reference for Readout Circuit of SPAD","authors":"Xuefeng Ye, D. Zeng, Xiangliang Jin, Yang Wang","doi":"10.1109/ASICON47005.2019.8983498","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983498","url":null,"abstract":"In this paper, a bandgap voltage reference (BGR) with a low temperature coefficient, used for readout circuits of SPAD, has been designed and fabricated successfully in the standard MXIC 0.5µm 1P3M CMOS process. The area of the core circuit occupies 244×215µm2. The test results show that the designed bandgap reference could work normally under the power supply voltage of 2.8V to 8V with a line regulation (LNR) of 0.0096%. At room temperature (25°C), the stable reference output voltage is 1.168V. The reference voltage varies by only 1.8mV within the temperature range of 0~150°C, and leads to a temperature coefficient of 10.28ppm/°C. Under the power supply of 5V, the BGR chip exhibits a power supply rejection ratio (PSRR) of 76.4dB at 1KHz.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128338762","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983510
Dehong Lv, Heng Ma, Fuqiang Liu, Zhiliang Hong
A curvature corrected bandgap reference (BGR) with 1ppm/°C temperature coefficient from −40°C to 150°C is presented. Random mismatch and 1/f noise are moved to high frequency by opamp chopping. Chopping ripple is removed by a switched capacitor notch filter which has a small area. It is designed in TSMC180 BCD process with 42uA current consumption and 0.06 mm2chip area.
{"title":"A curvature corrected bandgap reference with mismatch cancelling and noise reduction","authors":"Dehong Lv, Heng Ma, Fuqiang Liu, Zhiliang Hong","doi":"10.1109/ASICON47005.2019.8983510","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983510","url":null,"abstract":"A curvature corrected bandgap reference (BGR) with 1ppm/°C temperature coefficient from −40°C to 150°C is presented. Random mismatch and 1/f noise are moved to high frequency by opamp chopping. Chopping ripple is removed by a switched capacitor notch filter which has a small area. It is designed in TSMC180 BCD process with 42uA current consumption and 0.06 mm2chip area.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129597923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983522
Jiaqiang Li, Liyi Xiao, Liu He, Haotian Wu
Space applications face severe challenges from soft errors caused by cosmic rays. Soft errors can change the storage state of memories used in electronic system, leading to system failure. To avoid the system corruption, error correction codes (ECCs) as the general mitigation strategy in system level are utilized to eliminate the soft error influence. As the feature size goes down, more memory cells are integrated in the energy deposited range of radiation particles and MBU becomes the main error patterns. In this paper, we propose a new method to design 5-bit burst error correction code against more complex burst error. To achieve that, a technique to design a code with unequal correction ability and a customized interleaving plan combined with the proposed code is presented. The experiment result implies that this method is efficient for MBUs mitigation and a potential option for system designers.
{"title":"A Method to Design 5-Bit Burst Error Correction Code against the Multiple Bit Upset (MBU) in Memories","authors":"Jiaqiang Li, Liyi Xiao, Liu He, Haotian Wu","doi":"10.1109/ASICON47005.2019.8983522","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983522","url":null,"abstract":"Space applications face severe challenges from soft errors caused by cosmic rays. Soft errors can change the storage state of memories used in electronic system, leading to system failure. To avoid the system corruption, error correction codes (ECCs) as the general mitigation strategy in system level are utilized to eliminate the soft error influence. As the feature size goes down, more memory cells are integrated in the energy deposited range of radiation particles and MBU becomes the main error patterns. In this paper, we propose a new method to design 5-bit burst error correction code against more complex burst error. To achieve that, a technique to design a code with unequal correction ability and a customized interleaving plan combined with the proposed code is presented. The experiment result implies that this method is efficient for MBUs mitigation and a potential option for system designers.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127471915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/asicon47005.2019.8983679
E. Simoen, A. Oliveira, A. Veloso, A. Chasin, R. Ritzenthaler, H. Mertens, N. Horiguchi, C. Claeys
As will be shown, the architecture and gate stack processing have a clear impact on the low-frequency noise performance of horizontal nanowire (NW) transistors. In this work, the noise of single nanowires is compared with stacked devices. For single NWs, junctionless (JL) transistors tend to exhibit a better noise performance than inversion mode (IM) counterparts. In addition, a clear impact of the type of metal gate (MG) on the 1/f noise Power Spectral Density (PSD) will be demonstrated.
{"title":"Impact of Device Architecture and Gate Stack Processing on the Low-Frequency Noise of Silicon Nanowire Transistors","authors":"E. Simoen, A. Oliveira, A. Veloso, A. Chasin, R. Ritzenthaler, H. Mertens, N. Horiguchi, C. Claeys","doi":"10.1109/asicon47005.2019.8983679","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983679","url":null,"abstract":"As will be shown, the architecture and gate stack processing have a clear impact on the low-frequency noise performance of horizontal nanowire (NW) transistors. In this work, the noise of single nanowires is compared with stacked devices. For single NWs, junctionless (JL) transistors tend to exhibit a better noise performance than inversion mode (IM) counterparts. In addition, a clear impact of the type of metal gate (MG) on the 1/f noise Power Spectral Density (PSD) will be demonstrated.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127487873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983627
Xin Si, H. Qian, Meng-Fan Chang, Cheng-Xin Xue, Jian-Wei Su, Zhixiao Zhang, Sih-Han Li, S. Sheu, Heng-Yuan Lee, Ping-Cheng Chen, Huaqiang Wu
Computing-in-memory (CIM) structures are meant to overcome the memory bottleneck and improve energy efficiency for artificial intelligence (AI) edge devices. In this article, we review recent trends in the development of CIM macros for the Internet of Things and AI applications. We also look at recent advances in the development of CIMs based on SRAM and nonvolatile memory for AI edge devices as well as the challenges involved in circuit design.
{"title":"Circuit Design Challenges in Computing-in-Memory for AI Edge Devices","authors":"Xin Si, H. Qian, Meng-Fan Chang, Cheng-Xin Xue, Jian-Wei Su, Zhixiao Zhang, Sih-Han Li, S. Sheu, Heng-Yuan Lee, Ping-Cheng Chen, Huaqiang Wu","doi":"10.1109/ASICON47005.2019.8983627","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983627","url":null,"abstract":"Computing-in-memory (CIM) structures are meant to overcome the memory bottleneck and improve energy efficiency for artificial intelligence (AI) edge devices. In this article, we review recent trends in the development of CIM macros for the Internet of Things and AI applications. We also look at recent advances in the development of CIMs based on SRAM and nonvolatile memory for AI edge devices as well as the challenges involved in circuit design.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129097975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983585
Jianguo Yang, Xiaowen Li, Qingting Ding, X. Xue, Xiaoxin Xu, Q. Luo, H. Lv, Ming Liu
A low power re-configurable ring oscillator (RO) based interface circuit for SnO2 gas sensor is presented. The period of RO is dominated by the sampling voltage from gas sensor which is dependent on gas concentration. This proposed circuit improves the performance and power efficiency for resistive sensors. The interface circuit is implemented in 0.18 µm logic process with an area of 4000 µm2and 0.5 mW power consumption. The SnO2 thin films deposited on a micro hotplate machined by a MEMS process and is finally integrated with the interface chip in the form of a multi-chip package. Detection of Sub-ppm-Level ethanol gas has been demonstrated, the total power consumption of the sensor is less than 25 mW, which is suitable for IoT gas detection applications.
{"title":"A High Reliability 500 µW Resistance-to-Digital Interface Circuit for SnO2 Gas Sensor IoT Applications","authors":"Jianguo Yang, Xiaowen Li, Qingting Ding, X. Xue, Xiaoxin Xu, Q. Luo, H. Lv, Ming Liu","doi":"10.1109/ASICON47005.2019.8983585","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983585","url":null,"abstract":"A low power re-configurable ring oscillator (RO) based interface circuit for SnO2 gas sensor is presented. The period of RO is dominated by the sampling voltage from gas sensor which is dependent on gas concentration. This proposed circuit improves the performance and power efficiency for resistive sensors. The interface circuit is implemented in 0.18 µm logic process with an area of 4000 µm2and 0.5 mW power consumption. The SnO2 thin films deposited on a micro hotplate machined by a MEMS process and is finally integrated with the interface chip in the form of a multi-chip package. Detection of Sub-ppm-Level ethanol gas has been demonstrated, the total power consumption of the sensor is less than 25 mW, which is suitable for IoT gas detection applications.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126956124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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