Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983534
Xinning Liu, S. Jia, Hanzun Zhang
This paper presents a novel true random number generator with entropy source based on swappable matrix feedback ring oscillator (SMFRO). The proposed SMFRO structure utilizes multiple feedback mechanism to produce reliable chaotic oscillation. Three SMFROs implemented on FPGA with different resource configurations are tested. All of them can pass chaotic oscillation and NIST tests. Proposed design can generate random bits at 500MHz without extra post-processing.
{"title":"A Novel High-speed FPGA-based True Random Number Generator Based on Chaotic Ring Oscillator","authors":"Xinning Liu, S. Jia, Hanzun Zhang","doi":"10.1109/ASICON47005.2019.8983534","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983534","url":null,"abstract":"This paper presents a novel true random number generator with entropy source based on swappable matrix feedback ring oscillator (SMFRO). The proposed SMFRO structure utilizes multiple feedback mechanism to produce reliable chaotic oscillation. Three SMFROs implemented on FPGA with different resource configurations are tested. All of them can pass chaotic oscillation and NIST tests. Proposed design can generate random bits at 500MHz without extra post-processing.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131047414","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983476
Ruiqiang Song, Jinjin Shao, Bin Liang, Yaqing Chi, Jianjun Chen
This paper presents a circuit-level simulation approach. It is used to evaluate heavy ions induced single-event upset (SEU). The proposed approach firstly measures the ion-induce sensitive area with different LET values. Then, it calculates the distance between heavy ion locations and the sensitive transistor locations. The proposed approach compares the calculated distances with the measured sensitive area to determine the SEU characteristics. Heavy ion experiment is used to validate the capability of the proposed simulation approach. Simulated SEU cross sections show good agreement with experimental results.
{"title":"A Single-Event Upset Evaluation Approach Using Ion-Induced Sensitive Area","authors":"Ruiqiang Song, Jinjin Shao, Bin Liang, Yaqing Chi, Jianjun Chen","doi":"10.1109/ASICON47005.2019.8983476","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983476","url":null,"abstract":"This paper presents a circuit-level simulation approach. It is used to evaluate heavy ions induced single-event upset (SEU). The proposed approach firstly measures the ion-induce sensitive area with different LET values. Then, it calculates the distance between heavy ion locations and the sensitive transistor locations. The proposed approach compares the calculated distances with the measured sensitive area to determine the SEU characteristics. Heavy ion experiment is used to validate the capability of the proposed simulation approach. Simulated SEU cross sections show good agreement with experimental results.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131123842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983676
Shang Ma, Xuesi Wang, Yongjie Li, Kai Long, Bixin Zhu, Xin Lei
Aiming at the high-speed and low complexity of Direct Digital Frequency Synthesizer (DDS), this paper presents an improved structure of CORDIC algorithm (the excess-four algorithm). The mathematical approximate calculation is used to optimize the circuit structure of the rotating module in the excess-four algorithm, which reduces the adder in the rotating module and the hardware consumption of the circuit effectively. By removing the carry-over operation of the phase accumulating module, all the three-level rotating modules have the same structure, which ensures the same delay in all rotating units. The approach makes more advantages in the design of high-speed DDS circuits. Using the improved rotating structure, this paper implements the design of a highspeed DDS digital unit up to 6Gsps, with the SFDR above 88dBc, up to 104dBc. The single DDS core area is approximately 0.14 mm2 and the power consumption is 0.01mW/ MHz, using the Synopsys' SMIC 65nm process library tool to complete ASIC back-end design. In the case of SFDR that meets most of the high-speed DDS digital parts, the area and power consumption in this paper are greatly improved, compared with the conventional implementation method.
针对直接数字频率合成器(Direct Digital Frequency Synthesizer, DDS)高速、低复杂度的特点，提出了一种改进的CORDIC算法结构。在过四算法中，采用数学近似计算对旋转模块的电路结构进行优化，有效地减少了旋转模块中的加法器，降低了电路的硬件消耗。通过去掉积相模块的结转操作，所有的三级旋转模块都具有相同的结构，保证了所有旋转单元的延迟相同。该方法在高速DDS电路的设计中更有优势。本文采用改进的旋转结构，实现了高达6Gsps的高速DDS数字单元的设计，SFDR在88dBc以上，最高可达104dBc。单DDS核心面积约为0.14 mm2，功耗为0.01mW/ MHz，采用Synopsys的中芯国际65nm制程库工具完成ASIC后端设计。在满足大多数高速DDS数字器件的SFDR情况下，与传统实现方法相比，本文的面积和功耗大大提高。
{"title":"A Low Complexity DDS Based On Optimized CORDIC Algorithm","authors":"Shang Ma, Xuesi Wang, Yongjie Li, Kai Long, Bixin Zhu, Xin Lei","doi":"10.1109/ASICON47005.2019.8983676","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983676","url":null,"abstract":"Aiming at the high-speed and low complexity of Direct Digital Frequency Synthesizer (DDS), this paper presents an improved structure of CORDIC algorithm (the excess-four algorithm). The mathematical approximate calculation is used to optimize the circuit structure of the rotating module in the excess-four algorithm, which reduces the adder in the rotating module and the hardware consumption of the circuit effectively. By removing the carry-over operation of the phase accumulating module, all the three-level rotating modules have the same structure, which ensures the same delay in all rotating units. The approach makes more advantages in the design of high-speed DDS circuits. Using the improved rotating structure, this paper implements the design of a highspeed DDS digital unit up to 6Gsps, with the SFDR above 88dBc, up to 104dBc. The single DDS core area is approximately 0.14 mm2 and the power consumption is 0.01mW/ MHz, using the Synopsys' SMIC 65nm process library tool to complete ASIC back-end design. In the case of SFDR that meets most of the high-speed DDS digital parts, the area and power consumption in this paper are greatly improved, compared with the conventional implementation method.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133631818","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983622
Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, I. Jiang, Bei Yu, D. Pan
Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manufacturing. As a key step in the design flow, multiple patterning layout decomposition (MPLD) is critical to design closure. Due to the $mathcal{NP}$-hardness of the general decomposition problem, various efficient algorithms have been proposed with high quality solutions. However, with increasingly complicated design flow and peripheral processing steps, developing a high-quality layout decomposer becomes more and more difficult, slowing down the further advancement in this field. This paper presents OpenMPL [1], an open-source layout decomposition framework, with well-separated peripheral processing and the core solving steps. We demonstrate the flexibility of the framework with efficient implementations of various state-of-the-art algorithms, which enable us to reproduce most of the recent results on widely-recognized benchmarks. We believe OpenMPL can pave the road for developing layout decomposition engines and stimulate further researches on this problem.
{"title":"OpenMPL: An Open Source Layout Decomposer: Invited Paper","authors":"Wei Li, Yuzhe Ma, Qi Sun, Yibo Lin, I. Jiang, Bei Yu, D. Pan","doi":"10.1109/ASICON47005.2019.8983622","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983622","url":null,"abstract":"Multiple patterning lithography has been widely adopted in advanced technology nodes of VLSI manufacturing. As a key step in the design flow, multiple patterning layout decomposition (MPLD) is critical to design closure. Due to the $mathcal{NP}$-hardness of the general decomposition problem, various efficient algorithms have been proposed with high quality solutions. However, with increasingly complicated design flow and peripheral processing steps, developing a high-quality layout decomposer becomes more and more difficult, slowing down the further advancement in this field. This paper presents OpenMPL [1], an open-source layout decomposition framework, with well-separated peripheral processing and the core solving steps. We demonstrate the flexibility of the framework with efficient implementations of various state-of-the-art algorithms, which enable us to reproduce most of the recent results on widely-recognized benchmarks. We believe OpenMPL can pave the road for developing layout decomposition engines and stimulate further researches on this problem.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115393070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983531
Y. Deval, H. Lapuyade, F. Rivet
This paper addresses some design tricks that allow canceling - or at least reducing - the sensitivity of silicon integrated circuits to radiation effects. Both analog and digital circuits are here addressed. Redundancy, specific topology, system-level compensation: any combination is helpful as long as it avoids the implementation of radiation hardened specific technologies, as these are both expensive and unsuited to most of the state-of-the-art building blocks.
{"title":"Design of CMOS integrated circuits for radiation hardening and its application to space electronics","authors":"Y. Deval, H. Lapuyade, F. Rivet","doi":"10.1109/ASICON47005.2019.8983531","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983531","url":null,"abstract":"This paper addresses some design tricks that allow canceling - or at least reducing - the sensitivity of silicon integrated circuits to radiation effects. Both analog and digital circuits are here addressed. Redundancy, specific topology, system-level compensation: any combination is helpful as long as it avoids the implementation of radiation hardened specific technologies, as these are both expensive and unsuited to most of the state-of-the-art building blocks.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115416563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983518
Liang Qi, Sai-Weng Sin, R. Martins
This paper presents several techniques to enhance the resolution of sturdy multi-stage noise shaping (MASH) ΔΣ modulator (DSM). The proposed structure significantly suppresses the quantization noise (QN) by employing a high-resolution quantizer with a segmented MSB/LSB DAC feedback in the first loop as well as noise coupling techniques in both loops. Reducing QN of the first loop significantly decreases the output swings of the integrators, thus improving the stability of the first loop. Besides, the construction of one extra order shaping function mitigates the leakage of coarse QN introduced by a gain mismatch between MSB and LSB DACs of the high-resolution quantizer. Simulation results demonstrate the effectiveness of the proposed architecture to achieve high resolution while employing low-gain op-amps for all integrators.
{"title":"Multibit Sturdy MASH ΔΣ Modulator with Error-shaped Segmented DACs for Wideband Low-power Applications","authors":"Liang Qi, Sai-Weng Sin, R. Martins","doi":"10.1109/ASICON47005.2019.8983518","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983518","url":null,"abstract":"This paper presents several techniques to enhance the resolution of sturdy multi-stage noise shaping (MASH) ΔΣ modulator (DSM). The proposed structure significantly suppresses the quantization noise (QN) by employing a high-resolution quantizer with a segmented MSB/LSB DAC feedback in the first loop as well as noise coupling techniques in both loops. Reducing QN of the first loop significantly decreases the output swings of the integrators, thus improving the stability of the first loop. Besides, the construction of one extra order shaping function mitigates the leakage of coarse QN introduced by a gain mismatch between MSB and LSB DACs of the high-resolution quantizer. Simulation results demonstrate the effectiveness of the proposed architecture to achieve high resolution while employing low-gain op-amps for all integrators.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124251043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983525
Ze-kun Zhou, Zheng Jin, Jianwen Cao, Bo Zhang, Yue Shi
A zero-quiescent-power-consumption on-time generator is proposed in this paper, which is suitable for adaptive on-time (AOT) controlled Buck converters aiming at constant switching frequency. Instead of adopting operational amplifiers for voltage-to-current conversion in conventional methods, an adaptive compensation mechanism is presented to realize a current linearly proportional to regulated output voltage, Vo, with no operational amplifier, which is used to obtain a voltage proportional to output voltage. Besides, a resistor-capacitor filter is utilized to achieve a ramp signal with slope proportional to supply voltage, VIN. By this method, an on time, TON, proportional to Vo/VIN is realized, which is the core control law of AOT Buck converters. The proposed circuit is validated in a 0.18μm BCD technology, which demonstrates the accuracy of the TON is higher than 86% with temperatures and process variations. In the case of VIN=5V and Vo=1.2V, the average dynamic current of the proposed on-time generator is only 1.465μA in one switching period Tsw, while consuming zero quiescent power.
提出了一种适用于开关频率恒定的自适应on-time (AOT)控制降压变换器的零静态功耗on-time发生器。本文提出了一种自适应补偿机制，在不使用运放的情况下，实现与稳压输出电压Vo成线性比例的电流，而不使用运放来获得与输出电压成正比的电压。此外，利用电阻-电容滤波器实现斜率与电源电压VIN成正比的斜坡信号。通过该方法实现了与Vo/VIN成正比的on time TON，这是AOT降压变换器的核心控制规律。该电路在0.18μm BCD技术上进行了验证，结果表明，随温度和工艺变化，TON的精度高于86%。在VIN=5V, Vo=1.2V的情况下，所提出的导通发电机在一个开关周期(Tsw)内的平均动态电流仅为1.465μA，而静态功率为零。
{"title":"An On-Time Generator with Zero Quiescent Power Consumption Suitable for AOT Buck Converters","authors":"Ze-kun Zhou, Zheng Jin, Jianwen Cao, Bo Zhang, Yue Shi","doi":"10.1109/ASICON47005.2019.8983525","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983525","url":null,"abstract":"A zero-quiescent-power-consumption on-time generator is proposed in this paper, which is suitable for adaptive on-time (AOT) controlled Buck converters aiming at constant switching frequency. Instead of adopting operational amplifiers for voltage-to-current conversion in conventional methods, an adaptive compensation mechanism is presented to realize a current linearly proportional to regulated output voltage, Vo, with no operational amplifier, which is used to obtain a voltage proportional to output voltage. Besides, a resistor-capacitor filter is utilized to achieve a ramp signal with slope proportional to supply voltage, VIN. By this method, an on time, TON, proportional to Vo/VIN is realized, which is the core control law of AOT Buck converters. The proposed circuit is validated in a 0.18μm BCD technology, which demonstrates the accuracy of the TON is higher than 86% with temperatures and process variations. In the case of VIN=5V and Vo=1.2V, the average dynamic current of the proposed on-time generator is only 1.465μA in one switching period Tsw, while consuming zero quiescent power.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a ramp generator with automatic slope calibration which is able to compensate slope deviation due to process and environmental effects. A novel analog feedback circuit is proposed to regulate the stop voltage in successive approximation while fix the start voltage of the ramp automatically without much calibration code input or complicated auxiliary circuits, which reduces the complexity of circuitry and timing, meanwhile, saves area and power. A 12-bit single-slope ADC (SS-ADC), employing the proposed ramp generator, has been implemented in a 0.11-µm CMOS process. The simulation results show that the offset of the ramp's stop voltage is reduced to 0.1 LSB and the nonlinearity of the ramp is 0.034%. Besides, the measurement results verify that this structure can fulfill automatic slope calibration.
{"title":"An Automatic Slope-Calibrated Ramp Generator for Single-Slope ADCs","authors":"Shoudong Huang, Wengao Lu, Ye Zhou, Shanzhe Yu, Yacong Zhang, Xueyou Shi, Zhongjian Chen","doi":"10.1109/ASICON47005.2019.8983657","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983657","url":null,"abstract":"This paper presents a ramp generator with automatic slope calibration which is able to compensate slope deviation due to process and environmental effects. A novel analog feedback circuit is proposed to regulate the stop voltage in successive approximation while fix the start voltage of the ramp automatically without much calibration code input or complicated auxiliary circuits, which reduces the complexity of circuitry and timing, meanwhile, saves area and power. A 12-bit single-slope ADC (SS-ADC), employing the proposed ramp generator, has been implemented in a 0.11-µm CMOS process. The simulation results show that the offset of the ramp's stop voltage is reduced to 0.1 LSB and the nonlinearity of the ramp is 0.034%. Besides, the measurement results verify that this structure can fulfill automatic slope calibration.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114617320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983548
Haruo Kobayashi, Nene Kushita, MinhTri Tran, Koji Asami, H. San, A. Kuwana, Akemi Hatta
This paper describes the research history of the authors' group in the area of analog/mixed-signal circuits for complex or quadrature signal processing. Here the complex signal is composed of In-phase and Quadrature-phase signals (I, Q signals); the I-signal represents its real part while the Q-signal is its imaginary part. As complex signal processing circuits, the characteristics of the RC polyphaser filter, the complex active RC filter and the active Gm-C filter are shown and also our data weighted averaging (DWA) algorithms for complex ADCs/DACs are introduced.
{"title":"Analog / Mixed-Signal / RF Circuits for Complex Signal Processing","authors":"Haruo Kobayashi, Nene Kushita, MinhTri Tran, Koji Asami, H. San, A. Kuwana, Akemi Hatta","doi":"10.1109/ASICON47005.2019.8983548","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983548","url":null,"abstract":"This paper describes the research history of the authors' group in the area of analog/mixed-signal circuits for complex or quadrature signal processing. Here the complex signal is composed of In-phase and Quadrature-phase signals (I, Q signals); the I-signal represents its real part while the Q-signal is its imaginary part. As complex signal processing circuits, the characteristics of the RC polyphaser filter, the complex active RC filter and the active Gm-C filter are shown and also our data weighted averaging (DWA) algorithms for complex ADCs/DACs are introduced.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114703413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/asicon47005.2019.8983559
Jianfu Zhang, A. Manut, R. Gao, M. Mehedi, Z. Ji, Weidong Zhang, J. Marsland
Power consumption is a key issue especially for the edge devices/units in an IoT system. Lowering operation voltage is an effective way to reduce power. As the overdrive voltage, Vg-Vth, becomes smaller, the device is more vulnerable to threshold voltage jitters. One source for the jitter is Random Telegraph Noises (RTN), which cause a fluctuation in both drain current, ΔId, and threshold voltage, ΔVth. Early works on RTN were focused on measuring ΔId and then evaluate ΔVth from ΔId/gm, where gm is transconductance. The accuracy of ΔVth obtained in this way is not known. The objective of this work is to assess its accuracy by comparing it with the ΔVth directly measured from pulse Id-Vg. It will be shown that the correlation between these two is poor, so that ΔVth must not be evaluated from ΔId/gm. This is caused by the device-specific localized current distribution near the threshold.
{"title":"An assessment of RTN-induced threshold voltage jitter","authors":"Jianfu Zhang, A. Manut, R. Gao, M. Mehedi, Z. Ji, Weidong Zhang, J. Marsland","doi":"10.1109/asicon47005.2019.8983559","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983559","url":null,"abstract":"Power consumption is a key issue especially for the edge devices/units in an IoT system. Lowering operation voltage is an effective way to reduce power. As the overdrive voltage, Vg-Vth, becomes smaller, the device is more vulnerable to threshold voltage jitters. One source for the jitter is Random Telegraph Noises (RTN), which cause a fluctuation in both drain current, ΔId, and threshold voltage, ΔVth. Early works on RTN were focused on measuring ΔId and then evaluate ΔVth from ΔId/gm, where gm is transconductance. The accuracy of ΔVth obtained in this way is not known. The objective of this work is to assess its accuracy by comparing it with the ΔVth directly measured from pulse Id-Vg. It will be shown that the correlation between these two is poor, so that ΔVth must not be evaluated from ΔId/gm. This is caused by the device-specific localized current distribution near the threshold.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117140247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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