Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983575
Ru Ding, Xuemei Tian, Guoqiang Bai, G. Su, Xingjun Wu
As an important feed-forward neural network in the field of deep learning, convolutional neural network (CNN) has been widely used in image classification, face recognition, natural language processing and document analysis in recent years. CNN has a large amount of data and many multiply and accumulate (MAC) operations. With the diversity of application files, the channel sizes and kernel sizes of CNN are diverse, while the existing hardware platform mostly adopts the average optimization technology, which causes the waste of computing resources. In this paper, a special configurable convolution computing array is designed, which contains 15 convolution units, each PE contains 6×6 MAC operations, it can be configured to calculate three different kernel sizes of 5×5, 3×3 and 1×1. At the same time, pipeline structure is used to synchronize convolution and pooling operations, which reduces the storage of intermediate results. We design the special hardware structure to optimize DeepID network. Tested on Altera Cyclone V FPGA, the peak performance of each convolution layer at 50 MHz is 27 GOPS, and the average utilization of the MAC is 92%.
卷积神经网络(CNN)作为深度学习领域重要的前馈神经网络，近年来在图像分类、人脸识别、自然语言处理和文档分析等领域得到了广泛的应用。CNN的数据量很大，有很多的乘法和累加运算(MAC)。随着应用程序文件的多样性，CNN的通道大小和内核大小也是多种多样的，而现有的硬件平台大多采用平均优化技术，造成了计算资源的浪费。本文设计了一种特殊的可配置卷积计算阵列，该阵列包含15个卷积单元，每个PE包含6×6 MAC操作，可配置计算5×5、3×3和1×1三种不同内核大小。同时，采用流水线结构同步卷积和池化操作，减少了中间结果的存储。我们设计了特殊的硬件结构来优化DeepID网络。在Altera Cyclone V FPGA上测试，50 MHz时每个卷积层的峰值性能为27 GOPS, MAC的平均利用率为92%。
{"title":"Hardware Implementation of Convolutional Neural Network for Face Feature Extraction","authors":"Ru Ding, Xuemei Tian, Guoqiang Bai, G. Su, Xingjun Wu","doi":"10.1109/ASICON47005.2019.8983575","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983575","url":null,"abstract":"As an important feed-forward neural network in the field of deep learning, convolutional neural network (CNN) has been widely used in image classification, face recognition, natural language processing and document analysis in recent years. CNN has a large amount of data and many multiply and accumulate (MAC) operations. With the diversity of application files, the channel sizes and kernel sizes of CNN are diverse, while the existing hardware platform mostly adopts the average optimization technology, which causes the waste of computing resources. In this paper, a special configurable convolution computing array is designed, which contains 15 convolution units, each PE contains 6×6 MAC operations, it can be configured to calculate three different kernel sizes of 5×5, 3×3 and 1×1. At the same time, pipeline structure is used to synchronize convolution and pooling operations, which reduces the storage of intermediate results. We design the special hardware structure to optimize DeepID network. Tested on Altera Cyclone V FPGA, the peak performance of each convolution layer at 50 MHz is 27 GOPS, and the average utilization of the MAC is 92%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132676008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983642
Jintao Li, Yanhan Zeng, Hailong Wu, R. Li, Jun Zhang, Hongzhou Tan
An application of differential evolution for parameter optimization in the low dropout regulator (LDO) is presented in this paper. The parameters optimization by manual work for the analog integrated circuit, such as LDO, is laborious and time-consuming, and it is uncertain to find the relatively good result. In this paper, the differential evolution is used to optimize the parameters and find the relatively good performance of LDO. In order to improve the convergence speed and optimization effect, a new constraint solution and a fast weight-based non-dominated sorting method are proposed. Simulation results show that the gain-bandwidth product,load regulation and line regulation are improved by 206.5%, 58.1% and 87.6%, respectively, compared with the manual solution.
{"title":"Performance optimization for LDO regulator based on the differential evolution","authors":"Jintao Li, Yanhan Zeng, Hailong Wu, R. Li, Jun Zhang, Hongzhou Tan","doi":"10.1109/ASICON47005.2019.8983642","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983642","url":null,"abstract":"An application of differential evolution for parameter optimization in the low dropout regulator (LDO) is presented in this paper. The parameters optimization by manual work for the analog integrated circuit, such as LDO, is laborious and time-consuming, and it is uncertain to find the relatively good result. In this paper, the differential evolution is used to optimize the parameters and find the relatively good performance of LDO. In order to improve the convergence speed and optimization effect, a new constraint solution and a fast weight-based non-dominated sorting method are proposed. Simulation results show that the gain-bandwidth product,load regulation and line regulation are improved by 206.5%, 58.1% and 87.6%, respectively, compared with the manual solution.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133436993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/asicon47005.2019.8983616
Hao Sun, Jun Fu, Wenpu Cui, Tianling Ren, Linlin Liu, Wei Zhou, Quan Wang, Ao Guo
The coplanar waveguide (CPW) gap discontinuity is an important component of many applications in the monolithic microwave integrated circuits (MMICs). Therefore, accurate modeling of the CPW gap discontinuity is very important and fundamental for the design of MMICs. In this work, a new lumped equiva1ent-circuit model which can accurately describe the characterization of the CPW gap discontinuity from 0 to 150 GHz is proposed. The parameters are extracted from electromagnetic (EM) simulations simply and conveniently without any complicated optimization algorithms. And we make the model scalable in gap length, width and space. Satisfactory fitting accuracy is obtained between the model data and EM simulations, which verifies that our model can be implemented in computer-aided design software to reduce design time and save computer resources.
{"title":"Scalable Modeling for the CPW Gap Discontinuity at Frequency up to 150 GHz","authors":"Hao Sun, Jun Fu, Wenpu Cui, Tianling Ren, Linlin Liu, Wei Zhou, Quan Wang, Ao Guo","doi":"10.1109/asicon47005.2019.8983616","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983616","url":null,"abstract":"The coplanar waveguide (CPW) gap discontinuity is an important component of many applications in the monolithic microwave integrated circuits (MMICs). Therefore, accurate modeling of the CPW gap discontinuity is very important and fundamental for the design of MMICs. In this work, a new lumped equiva1ent-circuit model which can accurately describe the characterization of the CPW gap discontinuity from 0 to 150 GHz is proposed. The parameters are extracted from electromagnetic (EM) simulations simply and conveniently without any complicated optimization algorithms. And we make the model scalable in gap length, width and space. Satisfactory fitting accuracy is obtained between the model data and EM simulations, which verifies that our model can be implemented in computer-aided design software to reduce design time and save computer resources.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114012906","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A low-delay configurable register for FPGA is designed in this paper. This design is based on the basic master-slave D flip-flop, uses transmission gates on key nodes to control the register into four modes: register mode, latch mode, synchronous overwrite mode and asynchronous overwrite mode, then inputs desired signals to complete the functions of registers, latches, global initialization, synchronous reset, asynchronous reset, capture and write-back. The control signals and the D input are separated so that control circuit will not affect the register's timing parameters. A pre-simulation is carried out under the 28nm process and the results show that the configurable register's various functions are correct. The timing parameters are equivalent to the non-configurable master-slave D flip-flops, which proves that the control circuit does not affect the timing parameters. In this paper, configurable register has a 41-ps delay of CK to Q, a 7-ps setup time and a 0-ps hold time.
{"title":"A Low-delay Configurable Register for FPGA","authors":"Zhiyin Lu, Jiafeng Liu, Yunbing Pang, Zhengjie Li, Yufan Zhang, Jinmei Lai, Jian Wang","doi":"10.1109/ASICON47005.2019.8983553","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983553","url":null,"abstract":"A low-delay configurable register for FPGA is designed in this paper. This design is based on the basic master-slave D flip-flop, uses transmission gates on key nodes to control the register into four modes: register mode, latch mode, synchronous overwrite mode and asynchronous overwrite mode, then inputs desired signals to complete the functions of registers, latches, global initialization, synchronous reset, asynchronous reset, capture and write-back. The control signals and the D input are separated so that control circuit will not affect the register's timing parameters. A pre-simulation is carried out under the 28nm process and the results show that the configurable register's various functions are correct. The timing parameters are equivalent to the non-configurable master-slave D flip-flops, which proves that the control circuit does not affect the timing parameters. In this paper, configurable register has a 41-ps delay of CK to Q, a 7-ps setup time and a 0-ps hold time.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"36 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114022807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983457
Yue Shi, Jiawen Wang, Jianwen Cao, Ze-kun Zhou
A high performance, low power cycle-by-cycle current limiter is proposed in this paper, which can prevent switching-mode power supply from damage under over current or short circuit conditions. With the clamping effect formed by feedback loop with operational amplifier, the output current can be proportionally sampled and transferred to a voltage relative to ground. In order to further reduce power consumption, the sampling loop with low bias current is only enabled during the on time of high-side transistors. Besides, an assistant clamping circuit is presented to accelerate the settling time of every cycle for high-speed applications. What's more, a source-input comparator with voltage clamper is adopted to judge the status of output current, which can realize reference level and comparison at the same time for further speed improvement with lower power requirement. The proposed current limiter is implemented in a standard 0.18µm CMOS process, whose verification results within a 3A, 2.2MHz Buck converter show that a 39ns response time with 8.6MHz bandwidth is realized with only 2µA on-state and zero off-state current consumption.
{"title":"An Ultra-Low Power Cycle-by-Cycle Current Limiter Suitable for Switching-Mode Power Supply with 2.2 MHz Frequency","authors":"Yue Shi, Jiawen Wang, Jianwen Cao, Ze-kun Zhou","doi":"10.1109/ASICON47005.2019.8983457","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983457","url":null,"abstract":"A high performance, low power cycle-by-cycle current limiter is proposed in this paper, which can prevent switching-mode power supply from damage under over current or short circuit conditions. With the clamping effect formed by feedback loop with operational amplifier, the output current can be proportionally sampled and transferred to a voltage relative to ground. In order to further reduce power consumption, the sampling loop with low bias current is only enabled during the on time of high-side transistors. Besides, an assistant clamping circuit is presented to accelerate the settling time of every cycle for high-speed applications. What's more, a source-input comparator with voltage clamper is adopted to judge the status of output current, which can realize reference level and comparison at the same time for further speed improvement with lower power requirement. The proposed current limiter is implemented in a standard 0.18µm CMOS process, whose verification results within a 3A, 2.2MHz Buck converter show that a 39ns response time with 8.6MHz bandwidth is realized with only 2µA on-state and zero off-state current consumption.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115612315","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983433
J. Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, N. Wu, Gang Luo
This paper proposes a low-cost hardware system for rapid classification of visual objects encoded in the address-event representation (AER) format. A lightweight statistical inference algorithm is implemented in the proposed hardware to process the asynchronous pixel address streams from an AER visual sensor. The algorithm involves only a few simple operations for patch-based binary feature extraction and Random Ferns inference, which are highly parallelized and accelerated by our dedicated hardware architecture. Simulation results suggested that our hardware system was able to process as many as 50M address events per second and achieved 75% classification accuracy for the popular MNIST-DVS dataset. Compared to other AER classification systems, our low-cost FPGA implementation is more plausible for embedded applications because of its similar accuracy and higher system throughput.
{"title":"High-speed Classification of AER Data Based on a Low-cost Hardware System","authors":"J. Huang, Yingcheng Lin, Wei He, Xichuan Zhou, Cong Shi, N. Wu, Gang Luo","doi":"10.1109/ASICON47005.2019.8983433","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983433","url":null,"abstract":"This paper proposes a low-cost hardware system for rapid classification of visual objects encoded in the address-event representation (AER) format. A lightweight statistical inference algorithm is implemented in the proposed hardware to process the asynchronous pixel address streams from an AER visual sensor. The algorithm involves only a few simple operations for patch-based binary feature extraction and Random Ferns inference, which are highly parallelized and accelerated by our dedicated hardware architecture. Simulation results suggested that our hardware system was able to process as many as 50M address events per second and achieved 75% classification accuracy for the popular MNIST-DVS dataset. Compared to other AER classification systems, our low-cost FPGA implementation is more plausible for embedded applications because of its similar accuracy and higher system throughput.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114509298","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983539
Zhao Tuo, Tao Chen, Wei Li, Danyang Yang
The reconfigurable very-long instruction word (VLIW) cipher processor need a large number of instructions and a long execution period when processing the elliptic curve cryptographic algorithm. By adding a modular operation acceleration unit to the cryptographic processor, the energy efficiency of the cipher processor processing the elliptic curve cryptographic algorithm is improved. After synthesis under the 130nm process standard cell library, the experimental results show that the module operation acceleration unit area is 30 Kgate, accounting for 6% of the processor area, and the 256-bit binary domain point multiplication operation time is reduced from 22.8ms to 5.8ms, and the energy efficiency is improved by about 372%.
{"title":"Method for improving energy efficiency of elliptic curve cryptography algorithm on reconfigurable symmetric cipher processor","authors":"Zhao Tuo, Tao Chen, Wei Li, Danyang Yang","doi":"10.1109/ASICON47005.2019.8983539","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983539","url":null,"abstract":"The reconfigurable very-long instruction word (VLIW) cipher processor need a large number of instructions and a long execution period when processing the elliptic curve cryptographic algorithm. By adding a modular operation acceleration unit to the cryptographic processor, the energy efficiency of the cipher processor processing the elliptic curve cryptographic algorithm is improved. After synthesis under the 130nm process standard cell library, the experimental results show that the module operation acceleration unit area is 30 Kgate, accounting for 6% of the processor area, and the 256-bit binary domain point multiplication operation time is reduced from 22.8ms to 5.8ms, and the energy efficiency is improved by about 372%.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114647271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/asicon47005.2019.8983454
R. Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-Yan Zhang, Yi Zhao
In this work, we studied the performance enhancement of uniaxially tensile stressed n-FinFETs realized on the biaxially strained GeOI (sGOI) wafer and its impact on the performance of a Ge CMOS inverter. Uniaxially strained Ge film with nanoscale film width could be patterned on sGOI substrates and used for the fabrication of strained Ge FinFETs. The performance of this novelly proposed Ge FinFET was compared with the unstrained ones with similar dimensions and fabrication processes. The impact of strain on devices with different geometric parameters are also studied. As the strained FinFETs lead to higher on-current, its impact on the circuit speed was simulated. By comparing the output signal of the strained Ge CMOS inverter with the unstrained one, the former shows obvious speed improvement.
{"title":"Performance Investigation of Uniaxially Tensile Stressed Ge n-FinFETs Formed on Biaxially Strained GeOI Substrates And Its Impact On Ge CMOS Inverters","authors":"R. Cheng, Ming Tian, Changfeng Wang, Zhimei Cai, Jie Zhang, Yan-Yan Zhang, Yi Zhao","doi":"10.1109/asicon47005.2019.8983454","DOIUrl":"https://doi.org/10.1109/asicon47005.2019.8983454","url":null,"abstract":"In this work, we studied the performance enhancement of uniaxially tensile stressed n-FinFETs realized on the biaxially strained GeOI (sGOI) wafer and its impact on the performance of a Ge CMOS inverter. Uniaxially strained Ge film with nanoscale film width could be patterned on sGOI substrates and used for the fabrication of strained Ge FinFETs. The performance of this novelly proposed Ge FinFET was compared with the unstrained ones with similar dimensions and fabrication processes. The impact of strain on devices with different geometric parameters are also studied. As the strained FinFETs lead to higher on-current, its impact on the circuit speed was simulated. By comparing the output signal of the strained Ge CMOS inverter with the unstrained one, the former shows obvious speed improvement.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114404682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983641
Xuemei Fan, Rujin Wang, Qinghui Zeng, Hao Liu, Shengli Lu
The performance and reliability of integrated circuits are susceptible to PVTA variations. Conventional designs reserve certain timing margin and consider the worst-case to avoid these side effects. Timing resilient circuits can reduce the timing safe margin with the cost of excessive energy overhead and an unsteady state under a low voltage. In this study, we exploit a simple steady timing resilient sample by expanding previous works to save considerable extra power overhead. This sample executes timing errors detection based on the delay data sense detection and is implemented both on latches and data strobe flip-flops to recover errors with merely four extra transistors. The effectiveness and efficiency are evaluated by the design of a systolic array CNN accelerator in the 40-nm process. Simulation results demonstrate that the accelerator can achieve a stable performance without any accuracy loss, with the voltage scaled to 0.57V.
{"title":"A Simple Steady Timing Resilient Sample Based on Delay Data Sense Detection","authors":"Xuemei Fan, Rujin Wang, Qinghui Zeng, Hao Liu, Shengli Lu","doi":"10.1109/ASICON47005.2019.8983641","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983641","url":null,"abstract":"The performance and reliability of integrated circuits are susceptible to PVTA variations. Conventional designs reserve certain timing margin and consider the worst-case to avoid these side effects. Timing resilient circuits can reduce the timing safe margin with the cost of excessive energy overhead and an unsteady state under a low voltage. In this study, we exploit a simple steady timing resilient sample by expanding previous works to save considerable extra power overhead. This sample executes timing errors detection based on the delay data sense detection and is implemented both on latches and data strobe flip-flops to recover errors with merely four extra transistors. The effectiveness and efficiency are evaluated by the design of a systolic array CNN accelerator in the 40-nm process. Simulation results demonstrate that the accelerator can achieve a stable performance without any accuracy loss, with the voltage scaled to 0.57V.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123598015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ASICON47005.2019.8983582
Yangsheng Wang, Yanyan Gao, Chong Feng, N. Zhang
A radiation resistant standard cell library is completed based on SMIC 0.18 μm technology in this paper. Standard cell library includes combinatorial logic cells and sequential logic cells. SET (Single Event Transient) effect always occurs in combinatorial logic cells, and SEU (Single Event Upset) effect always occurs in sequential logic cells. SEL(Single Event Latchup) and TID(Total Ionizing Dose) effects affect all logic cells. According to radiation effects, logic cells in the standard cell library are designed with harden methods at the circuit level and the layout level. Combination logic cells adopt fault-tolerant delay filtering method in circuit level, and sequential logic cells use DICE structure in circuit design. A guard ring has been added to the layout design for the SEL and TID effects. Then physical information and timing information are extracted for all cells, and the library building process is completed. Finally we use EDA tools to verify the availability of the anti-radiation library.
{"title":"A radiation resistant library based on DICE and fault-tolerant delay filtering techniques in CMOS 0.18μm technology","authors":"Yangsheng Wang, Yanyan Gao, Chong Feng, N. Zhang","doi":"10.1109/ASICON47005.2019.8983582","DOIUrl":"https://doi.org/10.1109/ASICON47005.2019.8983582","url":null,"abstract":"A radiation resistant standard cell library is completed based on SMIC 0.18 μm technology in this paper. Standard cell library includes combinatorial logic cells and sequential logic cells. SET (Single Event Transient) effect always occurs in combinatorial logic cells, and SEU (Single Event Upset) effect always occurs in sequential logic cells. SEL(Single Event Latchup) and TID(Total Ionizing Dose) effects affect all logic cells. According to radiation effects, logic cells in the standard cell library are designed with harden methods at the circuit level and the layout level. Combination logic cells adopt fault-tolerant delay filtering method in circuit level, and sequential logic cells use DICE structure in circuit design. A guard ring has been added to the layout design for the SEL and TID effects. Then physical information and timing information are extracted for all cells, and the library building process is completed. Finally we use EDA tools to verify the availability of the anti-radiation library.","PeriodicalId":319342,"journal":{"name":"2019 IEEE 13th International Conference on ASIC (ASICON)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123004920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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