Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446867
E. Dharmarajan, Shengnian Song, L. Mclaughlin, J. Guan, J. Gazda, E. Lin, W. Qi, H. Shiraiwa, J. Hussey, J. Lansford, B. Banerjee
Through this work, we present a core leakage failure mechanism in our 90 nm high density memory products which was found to be related to etch process loading sensitivity to high density. Process optimization was done to fix the problem while maintaining sufficient etch margin against stringers.
{"title":"Spacer etch optimization on high density memory products to eliminate core leakage failures","authors":"E. Dharmarajan, Shengnian Song, L. Mclaughlin, J. Guan, J. Gazda, E. Lin, W. Qi, H. Shiraiwa, J. Hussey, J. Lansford, B. Banerjee","doi":"10.1109/ISSM.2007.4446867","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446867","url":null,"abstract":"Through this work, we present a core leakage failure mechanism in our 90 nm high density memory products which was found to be related to etch process loading sensitivity to high density. Process optimization was done to fix the problem while maintaining sufficient etch margin against stringers.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123095682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446823
Chih-Chiang Chen, Yu-Shian Chiang, Chen-Fu Chien
This study aims to propose a real option analysis to evaluate capital investment decisions for capacity expansion under demand uncertainty. Comparing to conventional analysis, this approach can provide a decision framework to incorporate management flexibility and thus provide a better measurement of optional value of capacity investment from potential benefits to avoid capacity shortage and losing growth opportunity. In particular, a binomial model with risk neutral method was employed to illustrate the expansion of the uncertainty event tree and the assessment of option value for supporting top managers' decision flexibility in light of dynamic decision contexts.
{"title":"Real option analysis for capacity investment planning for semiconductor manufacturing","authors":"Chih-Chiang Chen, Yu-Shian Chiang, Chen-Fu Chien","doi":"10.1109/ISSM.2007.4446823","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446823","url":null,"abstract":"This study aims to propose a real option analysis to evaluate capital investment decisions for capacity expansion under demand uncertainty. Comparing to conventional analysis, this approach can provide a decision framework to incorporate management flexibility and thus provide a better measurement of optional value of capacity investment from potential benefits to avoid capacity shortage and losing growth opportunity. In particular, a binomial model with risk neutral method was employed to illustrate the expansion of the uncertainty event tree and the assessment of option value for supporting top managers' decision flexibility in light of dynamic decision contexts.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116715319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446885
Y. Ogawa, H. Nagashima, Y. Yoshimizu, H. Tomita, T. Kishimoto, K. Miya, A. Izumi
In this paper, we indicate the difficulty of high-k film stripping of edge cut area using conventional bevel and backside etching tool and propose a fine edge cut control process using a novel bevel and backside etching tool with edge dispense nozzles.
{"title":"Fine edge and bevel film stripping process by novel wet cleaning tool beyond 45nm node","authors":"Y. Ogawa, H. Nagashima, Y. Yoshimizu, H. Tomita, T. Kishimoto, K. Miya, A. Izumi","doi":"10.1109/ISSM.2007.4446885","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446885","url":null,"abstract":"In this paper, we indicate the difficulty of high-k film stripping of edge cut area using conventional bevel and backside etching tool and propose a fine edge cut control process using a novel bevel and backside etching tool with edge dispense nozzles.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"24 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121012914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446872
M. Yang, H. Kim, F. Mieno
The transition of photoresist from KrF photoresist to ArF photoresist poses new challenges for etching process, especially for dielectric etching. In this article we design two types of dielectric etching applications, hole (contact) etching and LS (line space) etching. SAS software is employed for DOE (design of experiment) analysis of hole etching process optimization, best condition is derived and confirmed by experiment . To address LER, which is a persistent issue in LS application, mechanism is proposed and LER is successfully solved by new process.
{"title":"ArF photoresist etching behavior evaluation","authors":"M. Yang, H. Kim, F. Mieno","doi":"10.1109/ISSM.2007.4446872","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446872","url":null,"abstract":"The transition of photoresist from KrF photoresist to ArF photoresist poses new challenges for etching process, especially for dielectric etching. In this article we design two types of dielectric etching applications, hole (contact) etching and LS (line space) etching. SAS software is employed for DOE (design of experiment) analysis of hole etching process optimization, best condition is derived and confirmed by experiment . To address LER, which is a persistent issue in LS application, mechanism is proposed and LER is successfully solved by new process.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128412002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446803
A. Liu, Chia-Cheng Kuo, Chien‐Chih Chiu
This paper addresses the challenges facing PSC in the automation transport of twin FAB (FAB12AB). According to FAB output strategy, we have to consider the bottleneck of transportation and equipments/AMHS layout constraints. Further improved the INTER-FAB transportation capability. In our original INTER-FAB design capacity is 4400 move/day. After improved, we gained the extra 4600 move/day. It means we have improved the INTER-FAB transportation capability by 105%. In addition, the INTER-FAB transport time decreases from 18 min/move to 13 min/move.
{"title":"Efficiency AMHS for twin FAB manufacture","authors":"A. Liu, Chia-Cheng Kuo, Chien‐Chih Chiu","doi":"10.1109/ISSM.2007.4446803","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446803","url":null,"abstract":"This paper addresses the challenges facing PSC in the automation transport of twin FAB (FAB12AB). According to FAB output strategy, we have to consider the bottleneck of transportation and equipments/AMHS layout constraints. Further improved the INTER-FAB transportation capability. In our original INTER-FAB design capacity is 4400 move/day. After improved, we gained the extra 4600 move/day. It means we have improved the INTER-FAB transportation capability by 105%. In addition, the INTER-FAB transport time decreases from 18 min/move to 13 min/move.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132441343","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446811
E. Grinfeld, E. Paz
Information is a processed data that provides us the ability to make effective decisions. In these days, when no one is experiencing lack of data, the most valuable thing is the transformation of the data to information. In this paper we would like to present Implant source optimization system (iSOS) which was implemented in Intel HVM facility running Flash NOR technologies at Implant area. The implant area has experienced short source life duration as results of ineffective running mode of operation. This running mode has decreased the tools availability and increased the implant time which has caused lower throughput. In order to improve implant tools availability and utilization a set of "run rules" were defined by the area's engineers, utilizing different gases properties to extend the source's life. Though the run rules were well defined it was a difficult task to implement them and monitor the running history. iSOS was designed to transform mass of data from the tools into unique, effective and presentable information. By enabling fast and accurate decision making iSOS enabled Implant area to achieve additional capacity (improved availability by 4%-6%) at lower cost (saving of $10,000 per week) by doubling source life duration.
{"title":"Breakthrough system to optimize implant filament source usage","authors":"E. Grinfeld, E. Paz","doi":"10.1109/ISSM.2007.4446811","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446811","url":null,"abstract":"Information is a processed data that provides us the ability to make effective decisions. In these days, when no one is experiencing lack of data, the most valuable thing is the transformation of the data to information. In this paper we would like to present Implant source optimization system (iSOS) which was implemented in Intel HVM facility running Flash NOR technologies at Implant area. The implant area has experienced short source life duration as results of ineffective running mode of operation. This running mode has decreased the tools availability and increased the implant time which has caused lower throughput. In order to improve implant tools availability and utilization a set of \"run rules\" were defined by the area's engineers, utilizing different gases properties to extend the source's life. Though the run rules were well defined it was a difficult task to implement them and monitor the running history. iSOS was designed to transform mass of data from the tools into unique, effective and presentable information. By enabling fast and accurate decision making iSOS enabled Implant area to achieve additional capacity (improved availability by 4%-6%) at lower cost (saving of $10,000 per week) by doubling source life duration.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"144 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133826722","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446850
Jean-Yves Rosaye
Recently, competitive semiconductor manufacturing becomes indispensable to satisfy market requirements for failure prevention and process parameter control is of major concern. Mechanism of designing experiments used for process optimization in a large size fab. with Taguchi method or other statistical tool is not often considered. Instead, minimal design of experiment as with L8 orthogonal array is used because of trend to minimal experimentation. However, limits exist in minimal design, which introduced a lack of precision because of only two parameter levels in L8 for example. Simulation of experiment is suggested as to conciliate cost reduction, minimal experimentation with better design to obtain further and adequate information for process optimization.
{"title":"Study of S/N Ratio by simulation of experiment in a semiconductor manufacturing line","authors":"Jean-Yves Rosaye","doi":"10.1109/ISSM.2007.4446850","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446850","url":null,"abstract":"Recently, competitive semiconductor manufacturing becomes indispensable to satisfy market requirements for failure prevention and process parameter control is of major concern. Mechanism of designing experiments used for process optimization in a large size fab. with Taguchi method or other statistical tool is not often considered. Instead, minimal design of experiment as with L8 orthogonal array is used because of trend to minimal experimentation. However, limits exist in minimal design, which introduced a lack of precision because of only two parameter levels in L8 for example. Simulation of experiment is suggested as to conciliate cost reduction, minimal experimentation with better design to obtain further and adequate information for process optimization.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124782815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446807
E. Englhardt, V. Shah
The historical growth of the semiconductor industry is the result of a relentless, collaborative, industry-wide drive to decrease device costs. Much of the cost reduction that has been achieved over the last decade can be attributed to the vast productivity enhancement of device geometry reduction. However, further scaling is becoming increasingly complex and expensive; therefore, the semiconductor industry needs new methods for productivity improvement. This paper approaches productivity from the perspective of waste reduction. This new perspective reveals untapped opportunities for productivity improvement. New metrics are defined for evaluating fab waste. These metrics can then be used to quantify the value of potential solutions, as well as to define a roadmap for industry waste reduction.
{"title":"Eliminating waste: A roadmap for semiconductor industry productivity growth","authors":"E. Englhardt, V. Shah","doi":"10.1109/ISSM.2007.4446807","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446807","url":null,"abstract":"The historical growth of the semiconductor industry is the result of a relentless, collaborative, industry-wide drive to decrease device costs. Much of the cost reduction that has been achieved over the last decade can be attributed to the vast productivity enhancement of device geometry reduction. However, further scaling is becoming increasingly complex and expensive; therefore, the semiconductor industry needs new methods for productivity improvement. This paper approaches productivity from the perspective of waste reduction. This new perspective reveals untapped opportunities for productivity improvement. New metrics are defined for evaluating fab waste. These metrics can then be used to quantify the value of potential solutions, as well as to define a roadmap for industry waste reduction.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123737620","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446888
K. Umezawa, M. Inukai, S. Mori, T. Sato, I. Mizushima, H. Tomita, A. Yomoda
Epitaxial growth process strongly depends on the substrate surface cleanliness. In this study, advanced surface cleanness evaluation techniques for 32 nm node and beyond such as light point defects (LPDs) and haze measurements are studied using epitaxial silicon germanium (SiGe) process on 300 mm wafers. Small water marks formed during wafer drying can be detected as small LPDs just after pre-cleaning. These water marks inhibit SiGe growth during the epitaxial process. In addition, SiGe film LPDs increase drastically with increasing queue time between pre-cleaning process and SiGe CVD process. Finally, SURFimage haze measurement is shown to be a powerful advanced technique to monitor the localized "abnormal growth defects" and the surface morphology of the SiGe CVD film over the full wafer surface.
{"title":"Advanced surface cleanness evaluation technique using epitaxial silicon germanium (SiGe) process beyond 32nm node","authors":"K. Umezawa, M. Inukai, S. Mori, T. Sato, I. Mizushima, H. Tomita, A. Yomoda","doi":"10.1109/ISSM.2007.4446888","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446888","url":null,"abstract":"Epitaxial growth process strongly depends on the substrate surface cleanliness. In this study, advanced surface cleanness evaluation techniques for 32 nm node and beyond such as light point defects (LPDs) and haze measurements are studied using epitaxial silicon germanium (SiGe) process on 300 mm wafers. Small water marks formed during wafer drying can be detected as small LPDs just after pre-cleaning. These water marks inhibit SiGe growth during the epitaxial process. In addition, SiGe film LPDs increase drastically with increasing queue time between pre-cleaning process and SiGe CVD process. Finally, SURFimage haze measurement is shown to be a powerful advanced technique to monitor the localized \"abnormal growth defects\" and the surface morphology of the SiGe CVD film over the full wafer surface.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130295418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-10-01DOI: 10.1109/ISSM.2007.4446887
V. Svidenko, R. Shimshi, Y. Nehmadi
In this paper, we present a new methodology for inline yield prediction based on defect inspection and design data. We derive a new metric called criticality factor (CF), which is essentially a fractional critical area for a defect of the reported size in a small layout window around the reported defect location. CF would be a good predictor of yield if geometrical considerations alone determined whether an electrical fail will result. Since other properties of the defect affect the electrical outcome (such as material properties), we employ a Training Set of wafers where the functional relation between CF and die yield is learned for each critical inspection step. From that point on these curves are used to predict the yield impact of in-line defects for new wafers. In addition, we show that highly-systematic defects (i.e. layout dependent) deviate from the CF functional curves, and hence add noise to the calculation. We suggest a technique to separate these defects from the random population, and calculate a corrected CF value for them.
{"title":"Dynamic defect-limited yield prediction by criticality factor","authors":"V. Svidenko, R. Shimshi, Y. Nehmadi","doi":"10.1109/ISSM.2007.4446887","DOIUrl":"https://doi.org/10.1109/ISSM.2007.4446887","url":null,"abstract":"In this paper, we present a new methodology for inline yield prediction based on defect inspection and design data. We derive a new metric called criticality factor (CF), which is essentially a fractional critical area for a defect of the reported size in a small layout window around the reported defect location. CF would be a good predictor of yield if geometrical considerations alone determined whether an electrical fail will result. Since other properties of the defect affect the electrical outcome (such as material properties), we employ a Training Set of wafers where the functional relation between CF and die yield is learned for each critical inspection step. From that point on these curves are used to predict the yield impact of in-line defects for new wafers. In addition, we show that highly-systematic defects (i.e. layout dependent) deviate from the CF functional curves, and hence add noise to the calculation. We suggest a technique to separate these defects from the random population, and calculate a corrected CF value for them.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123120180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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