Pub Date : 2009-12-09DOI: 10.1109/RECONFIG.2009.82
M. Gok
Multiple sequence alignment (MSA) is one of the essential operations for identifying functional and structural relations among proteins. The execution of an MSA algorithm requires high-performance platforms. This paper presents a hardware system that speeds up the popular MSA software ClustalW. The proposed design performs the computation of the most time consuming step of the ClustalW. Test results show that the proposed hardware increases the performance of this step up to 85 times.
{"title":"An Optimized System for Multiple Sequence Alignment","authors":"M. Gok","doi":"10.1109/RECONFIG.2009.82","DOIUrl":"https://doi.org/10.1109/RECONFIG.2009.82","url":null,"abstract":"Multiple sequence alignment (MSA) is one of the essential operations for identifying functional and structural relations among proteins. The execution of an MSA algorithm requires high-performance platforms. This paper presents a hardware system that speeds up the popular MSA software ClustalW. The proposed design performs the computation of the most time consuming step of the ClustalW. Test results show that the proposed hardware increases the performance of this step up to 85 times.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116306041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.57
Nathalie Bochard, F. Bernard, V. Fischer
The paper deals with true random number generators using a set of ring oscillators as proposed by Sunar et al. in 2007. The original generator has been recently enhanced by Wold and Tan by introducing flip-flops at the output of each ring. We show in the first part of the paper that both original and enhanced architectures have exactly the same behavior when composed of ideal components (they have the same mathematical model), but they have very different behavior in physical devices, as observed by Wold and Tan. However, while reducing the number of rings as they have proposed, the security proof of Sunar et al. does not hold any more. In order to demonstrate that, we will show that the proportion of the pseudo-randomness compared to the true-randomness in the generated random raw signal is much bigger than expected. Our simulation model shows that the generator using more than 18 ideal jitter-free rings having slightly different frequencies and producing thus only pseudo-randomness, will always let the tests pass. We conclude that reducing the number of rings not only makes the security proof of Sunar et al. not hold, but it makes the generator more vulnerable, since the pseudo-randomness is easy to manipulate.
{"title":"Observing the Randomness in RO-Based TRNG","authors":"Nathalie Bochard, F. Bernard, V. Fischer","doi":"10.1109/ReConFig.2009.57","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.57","url":null,"abstract":"The paper deals with true random number generators using a set of ring oscillators as proposed by Sunar et al. in 2007. The original generator has been recently enhanced by Wold and Tan by introducing flip-flops at the output of each ring. We show in the first part of the paper that both original and enhanced architectures have exactly the same behavior when composed of ideal components (they have the same mathematical model), but they have very different behavior in physical devices, as observed by Wold and Tan. However, while reducing the number of rings as they have proposed, the security proof of Sunar et al. does not hold any more. In order to demonstrate that, we will show that the proportion of the pseudo-randomness compared to the true-randomness in the generated random raw signal is much bigger than expected. Our simulation model shows that the generator using more than 18 ideal jitter-free rings having slightly different frequencies and producing thus only pseudo-randomness, will always let the tests pass. We conclude that reducing the number of rings not only makes the security proof of Sunar et al. not hold, but it makes the generator more vulnerable, since the pseudo-randomness is easy to manipulate.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127577717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.63
A. Silva-Filho, Sidney M. L. Lima, F. C. Cox
Cache memory is a usual architecture component, and has the function of increasing the system’s performance. Cache, however, may be responsible for a large part of energy consumption (about 50%) of microprocessors. Based on this, the paper proposes an automated architecture exploration mechanism based on parameter variation of a cache memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 12.5% of the design space, an energy consumption reduction of about 31% has been achieved, as well as an increase of 11% in the performance of the application. Additionally, it was observed that optimal results were found in 67% of the examined cases.
{"title":"Low Power RTL Exploration Mechanism Based on the Cache Parameters","authors":"A. Silva-Filho, Sidney M. L. Lima, F. C. Cox","doi":"10.1109/ReConFig.2009.63","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.63","url":null,"abstract":"Cache memory is a usual architecture component, and has the function of increasing the system’s performance. Cache, however, may be responsible for a large part of energy consumption (about 50%) of microprocessors. Based on this, the paper proposes an automated architecture exploration mechanism based on parameter variation of a cache memory hierarchy and NIOS II processor. Results based on Mibench and XiRisc suite have demonstrated that, on average, with 12.5% of the design space, an energy consumption reduction of about 31% has been achieved, as well as an increase of 11% in the performance of the application. Additionally, it was observed that optimal results were found in 67% of the examined cases.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124815445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.25
Yoann Guillemenet, S. Z. Ahmed, L. Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, G. Sassatelli
The need of non volatility along with the added flexibility of un limited reprogramming like SRAM has lead to the concept of universal memories. MRAM (Magnetoresistive Random Access Memory) is one prominent member of them. At present only Flash is providing a limited bridge for that. Flash based FPGAs have several benefits being non volatile but unfortunately also loose many of the features which are only possible with SRAM based FPGAs. MRAMs have potential to bridge this gap. This paper will present a brief survey of our work in this regard for creating the entire eco system of software and hardware tool flows, MRAM layout work at 120nm, exploration environments to conduct complex experiments especially Dynamic Reconfiguration and Multi Context FPGAs. MRAM opens new opportunities for them compared to SRAM and Flash. It will discuss the current status of MRAM in industry and our current and future test chips road maps. Provide several references to industry and our published work for details about MRAMs and eFPGAs, to show why we think MRAM can be very interesting element for FPGAs.
{"title":"MRAM Based eFPGAs: Programming and Silicon Flows, Exploration Environments, MRAM Current State in Industry and Its Unique Potentials for FPGAs","authors":"Yoann Guillemenet, S. Z. Ahmed, L. Torres, Alexandre Martheley, Julien Eydoux, Jean-Baptiste Cuelle, Laurent Rouge, G. Sassatelli","doi":"10.1109/ReConFig.2009.25","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.25","url":null,"abstract":"The need of non volatility along with the added flexibility of un limited reprogramming like SRAM has lead to the concept of universal memories. MRAM (Magnetoresistive Random Access Memory) is one prominent member of them. At present only Flash is providing a limited bridge for that. Flash based FPGAs have several benefits being non volatile but unfortunately also loose many of the features which are only possible with SRAM based FPGAs. MRAMs have potential to bridge this gap. This paper will present a brief survey of our work in this regard for creating the entire eco system of software and hardware tool flows, MRAM layout work at 120nm, exploration environments to conduct complex experiments especially Dynamic Reconfiguration and Multi Context FPGAs. MRAM opens new opportunities for them compared to SRAM and Flash. It will discuss the current status of MRAM in industry and our current and future test chips road maps. Provide several references to industry and our published work for details about MRAMs and eFPGAs, to show why we think MRAM can be very interesting element for FPGAs.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"9 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132241304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.64
Muhammad Aqeel Wahlah, K. Goossens
We envision that future FPGA will use a hardwired network on chip (HWNoC)~cite{Goossens08NoCS} as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a reconfiguration methodology which makes use of such a platform to realize composable inter-application communication and persistent-state intra-application when run-time partial reconfiguration is performed. The proposed methodology also ensures that the required performance constraints of the dynamically swapped in application are fulfilled. We describe the approach and steps required to achieve the above objectives. We model the application dynamic swapping behavior in cycle-accurate transaction-level SystemC which includes bitstream loading, HWNoC programming, clocking, reset, computation.
{"title":"Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip","authors":"Muhammad Aqeel Wahlah, K. Goossens","doi":"10.1109/ReConFig.2009.64","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.64","url":null,"abstract":"We envision that future FPGA will use a hardwired network on chip (HWNoC)~cite{Goossens08NoCS} as a unified interconnect for functional communications (data and control) as well as configuration (bitstream for soft IPs). In this paper we present a reconfiguration methodology which makes use of such a platform to realize composable inter-application communication and persistent-state intra-application when run-time partial reconfiguration is performed. The proposed methodology also ensures that the required performance constraints of the dynamically swapped in application are fulfilled. We describe the approach and steps required to achieve the above objectives. We model the application dynamic swapping behavior in cycle-accurate transaction-level SystemC which includes bitstream loading, HWNoC programming, clocking, reset, computation.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132787127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.46
Ahmet Onur Durahim, E. Savaş, Kazim Yumbul
We design and realize a protected zone inside a reconfigurable and extensible embedded RISC processor for isolated execution of cryptographic algorithms. The protected zone is a collection of processor subsystems such as functional units optimized for high-speed execution of integer operations, a small amount of local memory, and general- and special-purpose registers. We outline the principles for secure software implementation of cryptographic algorithms in a processor equipped with the protected zone. We also demonstrate the efficiency and effectiveness of the protected zone by implementing major cryptographic algorithms, namely RSA, elliptic curve cryptography, and AES in the protected zone. In terms of time efficiency, software implementations of these three cryptographic algorithms outperform equivalent software implementations on similar processors reported in the literature. The protected zone is designed in such a modular fashion that it can easily be integrated into any RISC processor; its area overhead is considerably moderate in the sense that it can be used in vast majority of embedded processors. The protected zone can also provide the necessary support to implement TPM functionality within the boundary of a processor.
{"title":"Implementing a Protected Zone in a Reconfigurable Processor for Isolated Execution of Cryptographic Algorithms","authors":"Ahmet Onur Durahim, E. Savaş, Kazim Yumbul","doi":"10.1109/ReConFig.2009.46","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.46","url":null,"abstract":"We design and realize a protected zone inside a reconfigurable and extensible embedded RISC processor for isolated execution of cryptographic algorithms. The protected zone is a collection of processor subsystems such as functional units optimized for high-speed execution of integer operations, a small amount of local memory, and general- and special-purpose registers. We outline the principles for secure software implementation of cryptographic algorithms in a processor equipped with the protected zone. We also demonstrate the efficiency and effectiveness of the protected zone by implementing major cryptographic algorithms, namely RSA, elliptic curve cryptography, and AES in the protected zone. In terms of time efficiency, software implementations of these three cryptographic algorithms outperform equivalent software implementations on similar processors reported in the literature. The protected zone is designed in such a modular fashion that it can easily be integrated into any RISC processor; its area overhead is considerably moderate in the sense that it can be used in vast majority of embedded processors. The protected zone can also provide the necessary support to implement TPM functionality within the boundary of a processor.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134405199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/RECONFIG.2009.27
G. Guindani, Frederico Ferlini, J. Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, F. Moraes
Integrated circuits for very high-speed telecommu¬nication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGAs, implemented in 65 or 45 nm technologies achieve high operating frequencies, and serializer/deserializer hardwired modules enable the reception of high speed aggregated rates (e.g. 10 Gbps or more), spanning the input stream for internal parallel computation. This paper presents a complete solution for an Optical Transport Network framer using FPGA devices. The framer receives a 10 Gbps stream originated from optical fiber medium, extracts its payload information, and transmits payload data at 10 Gbps. A working prototype was implemented in Virtex-4 and Virtex-5 devices.
{"title":"A 10 Gbps OTN Framer Implementation Targeting FPGA Devices","authors":"G. Guindani, Frederico Ferlini, J. Oliveira, Ney Laert Vilar Calazans, Daniel V. Pigatto, F. Moraes","doi":"10.1109/RECONFIG.2009.27","DOIUrl":"https://doi.org/10.1109/RECONFIG.2009.27","url":null,"abstract":"Integrated circuits for very high-speed telecommu¬nication protocols often use ASICs, due to their strict timing constraints. This scenario is changing, since modern FPGAs, implemented in 65 or 45 nm technologies achieve high operating frequencies, and serializer/deserializer hardwired modules enable the reception of high speed aggregated rates (e.g. 10 Gbps or more), spanning the input stream for internal parallel computation. This paper presents a complete solution for an Optical Transport Network framer using FPGA devices. The framer receives a 10 Gbps stream originated from optical fiber medium, extracts its payload information, and transmits payload data at 10 Gbps. A working prototype was implemented in Virtex-4 and Virtex-5 devices.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121857199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.11
L. Colavito, D. Silage
Linear feedback shift registers (LFSR) are commonly utilized in digital communication system simulations as noise and data sources because they are easily implemented and require minimal resources. However, the LFSR exhibits a deficiency common to all multiplicative congruential pseudorandom number generators (PNG). This class of PNG exhibits a correlation between successive values that gives an undesired low-pass characteristic to the generated sequence. This characteristic can affect the simulation results when whiteness of the pseudorandom random sequence is assumed. Several techniques have been proposed to mitigate this deficiency. In this paper we demonstrate how one of these proposed techniques, multiple-bit skip-ahead, can be efficiently implemented in programmable gate array hardware (PGA) so that under specific conditions, the computational complexity and required hardware resources are minimal.
{"title":"Efficient PGA LFSR Implementation Whitens Pseudorandom Numbers","authors":"L. Colavito, D. Silage","doi":"10.1109/ReConFig.2009.11","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.11","url":null,"abstract":"Linear feedback shift registers (LFSR) are commonly utilized in digital communication system simulations as noise and data sources because they are easily implemented and require minimal resources. However, the LFSR exhibits a deficiency common to all multiplicative congruential pseudorandom number generators (PNG). This class of PNG exhibits a correlation between successive values that gives an undesired low-pass characteristic to the generated sequence. This characteristic can affect the simulation results when whiteness of the pseudorandom random sequence is assumed. Several techniques have been proposed to mitigate this deficiency. In this paper we demonstrate how one of these proposed techniques, multiple-bit skip-ahead, can be efficiently implemented in programmable gate array hardware (PGA) so that under specific conditions, the computational complexity and required hardware resources are minimal.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124997042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.18
Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, T. Kuhn, W. Rosenstiel
With the increasing power density of deep submicron technology, temperature becomes one of the dominating factors for the reliability of integrated circuits. Coarse-grained reconfigurable devices typically exhibit spatially nonuniform activity, which results in areas of localized heating, so called hot spots. In this work we investigate the effects of continuous activity migration in order to prevent hot spots. By applying activity migration we are able to reduce temporal and spatial variations of temperature by up to 87%.
{"title":"Prevention of Hot Spot Development on Coarse-Grained Dynamically Reconfigurable Architectures","authors":"Sven Eisenhardt, Thomas Schweizer, Andreas Bernauer, T. Kuhn, W. Rosenstiel","doi":"10.1109/ReConFig.2009.18","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.18","url":null,"abstract":"With the increasing power density of deep submicron technology, temperature becomes one of the dominating factors for the reliability of integrated circuits. Coarse-grained reconfigurable devices typically exhibit spatially nonuniform activity, which results in areas of localized heating, so called hot spots. In this work we investigate the effects of continuous activity migration in order to prevent hot spots. By applying activity migration we are able to reduce temporal and spatial variations of temperature by up to 87%.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127169085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.49
Chenxin Zhang, T. Lenart, Henrik Svensson, V. Öwall
This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.
{"title":"Design of Coarse-Grained Dynamically Reconfigurable Architecture for DSP Applications","authors":"Chenxin Zhang, T. Lenart, Henrik Svensson, V. Öwall","doi":"10.1109/ReConFig.2009.49","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.49","url":null,"abstract":"This paper presents the design and implementation of a coarse-grained reconfigurable architecture, targeting digital signal processing applications. The proposed architecture is constructed from a mesh of resource cells, containing separated processing and memory elements that communicate via a hybrid interconnect network. Parameterizable design of resource cells enables flexible mapping of arbitrary applications at system compile-time, and the feature of dynamic reconfigurability provides mapping possibilities during system run-time to adapt to the current operational and processing conditions. Functionality and flexibility of the proposed architecture is demonstrated through mapping of a radix-22 FFT processor reconfigurable between 32 and 1024 points. Performance evaluation exhibits a great reconfigurability and execution time reduction when compared to a traditional DSP and ARM solution.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127281767","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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