Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.44
Emna Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez
In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in Wave Dynamic Differential Logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a Tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing techniques reduce the delay unbalance significantly. They achieve 93 % of average timing balancing improvement in WDDL designs.
{"title":"Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing","authors":"Emna Amouri, H. Mrabet, Z. Marrakchi, H. Mehrez","doi":"10.1109/ReConFig.2009.44","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.44","url":null,"abstract":"In this paper, we propose placement and routing techniques to deal with the timing unbalance problem in Wave Dynamic Differential Logic (WDDL) circuits. First, we study the impact of placement on the delay unbalance in a Tree-based FPGA. Then, we propose an adaptation to the Pathfinder routing algorithm to improve the delay balance. The experimental results demonstrate that our placement and routing techniques reduce the delay unbalance significantly. They achieve 93 % of average timing balancing improvement in WDDL designs.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127482757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.83
J. Großschädl, E. Savaş, Kazim Yumbul
Within the context of cryptographic hardware, the term scalability refers to the ability to process operands of any size, regardless of the precision of the underlying datapath or registers. In this paper we present a simple yet effective technique for increasing the scalability of a fixed-precision Montgomery multiplier. Our idea is to extend the datapath of a Montgomery multiplier in such a way that it can also perform an ordinary multiplication of two n-bit operands (without modular reduction), yielding a 2n-bit result. This conventional (n*n-≫2n)-bit multiplication is then used as a "sub-routine" to realize arbitrary-precision Montgomery multiplication according to standard software algorithms such as Coarsely Integrated Operand Scanning (CIOS). We show that performing a 2n-bit modular multiplication on an n-bit multiplier can be done in 5n clock cycles, whereby we assume that the n-bit modular multiplication takes $n$ cycles. Extending a Montgomery multiplier for this extra functionality requires just some minor modifications of the datapath and entails a slight increase in silicon area.
{"title":"Realizing Arbitrary-Precision Modular Multiplication with a Fixed-Precision Multiplier Datapath","authors":"J. Großschädl, E. Savaş, Kazim Yumbul","doi":"10.1109/ReConFig.2009.83","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.83","url":null,"abstract":"Within the context of cryptographic hardware, the term scalability refers to the ability to process operands of any size, regardless of the precision of the underlying datapath or registers. In this paper we present a simple yet effective technique for increasing the scalability of a fixed-precision Montgomery multiplier. Our idea is to extend the datapath of a Montgomery multiplier in such a way that it can also perform an ordinary multiplication of two n-bit operands (without modular reduction), yielding a 2n-bit result. This conventional (n*n-≫2n)-bit multiplication is then used as a \"sub-routine\" to realize arbitrary-precision Montgomery multiplication according to standard software algorithms such as Coarsely Integrated Operand Scanning (CIOS). We show that performing a 2n-bit modular multiplication on an n-bit multiplier can be done in 5n clock cycles, whereby we assume that the n-bit modular multiplication takes $n$ cycles. Extending a Montgomery multiplier for this extra functionality requires just some minor modifications of the datapath and entails a slight increase in silicon area.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"1238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126344302","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.76
O. A. Nava, A. Díaz-Pérez
Fractal Image Compression (FIC) is a lossy technique whose features are promising for computer systems with few resources, however, it has been ignored due to the large amount of operations needed to complete the codification. On the other hand, the development of VLSI technology allows for the creation of programmable devices with greater facilities, which not only offer a large gate density to program hardware modules, but also contain one or more embedded processors, allowing the creation of complete systems inside a single chip (SoC). The use of hardware and software components in a single electronic system allows to combine the flexibility offered by software and the high computing power and parallelism of hardware. This paper describes a Hardware-Software Co-Design (HSC) of FIC which improves the compression time, obtaining an acceleration factor between 6.6 and 8.5. The system was built on a SoC based on an FPGA.
{"title":"Acceleration of Fractal Image Compression Using the Hardware-Software Co-design Methodology","authors":"O. A. Nava, A. Díaz-Pérez","doi":"10.1109/ReConFig.2009.76","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.76","url":null,"abstract":"Fractal Image Compression (FIC) is a lossy technique whose features are promising for computer systems with few resources, however, it has been ignored due to the large amount of operations needed to complete the codification. On the other hand, the development of VLSI technology allows for the creation of programmable devices with greater facilities, which not only offer a large gate density to program hardware modules, but also contain one or more embedded processors, allowing the creation of complete systems inside a single chip (SoC). The use of hardware and software components in a single electronic system allows to combine the flexibility offered by software and the high computing power and parallelism of hardware. This paper describes a Hardware-Software Co-Design (HSC) of FIC which improves the compression time, obtaining an acceleration factor between 6.6 and 8.5. The system was built on a SoC based on an FPGA.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133878385","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/RECONFIG.2009.43
D. Llamocca, M. Pattichis, G. A. Vera
Many DSP, image and video processing applications use Finite Impulse Response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-computed, fixed-point realizations of different digital filters. Our platform relies on the use of Distributed Arithmetic blocks, mapped to the specific LUTs of the underlying FPGA. Dynamic reconfiguration of the coefficients is limited to changing a small number of relevant LUT contents, while leaving the rest of the architecture intact. We investigate the dynamic system throughput as a function of the dynamic reconfiguration rate.
{"title":"A Dynamically Reconfigurable Platform for Fixed-Point FIR Filters","authors":"D. Llamocca, M. Pattichis, G. A. Vera","doi":"10.1109/RECONFIG.2009.43","DOIUrl":"https://doi.org/10.1109/RECONFIG.2009.43","url":null,"abstract":"Many DSP, image and video processing applications use Finite Impulse Response (FIR) filters as basic computing blocks. Our paper introduces an efficient dynamically reconfigurable FIR system that can adapt the number of filter coefficients, and their values, in real time. Here, dynamic reconfiguration is used to switch between different, pre-computed, fixed-point realizations of different digital filters. Our platform relies on the use of Distributed Arithmetic blocks, mapped to the specific LUTs of the underlying FPGA. Dynamic reconfiguration of the coefficients is limited to changing a small number of relevant LUT contents, while leaving the rest of the architecture intact. We investigate the dynamic system throughput as a function of the dynamic reconfiguration rate.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114272256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.10
A. Stauffer, J. Rossier
Inspired by the basic processes of molecular biology, our previous studies resulted in defining self-testing and self-organizing mechanisms made up of simple processes. The goal of our paper is to introduce a configurable molecule able to implement these bio-inspired mechanisms as well as their underlying processes. The hardware description of the molecule leads to the simulation of a multiplier designed as a one-dimensional organism dedicated to bit slice processors.
{"title":"Bio-inspired Self-Testing and Self-Organizing Bit Slice Processors","authors":"A. Stauffer, J. Rossier","doi":"10.1109/ReConFig.2009.10","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.10","url":null,"abstract":"Inspired by the basic processes of molecular biology, our previous studies resulted in defining self-testing and self-organizing mechanisms made up of simple processes. The goal of our paper is to introduce a configurable molecule able to implement these bio-inspired mechanisms as well as their underlying processes. The hardware description of the molecule leads to the simulation of a multiplier designed as a one-dimensional organism dedicated to bit slice processors.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114848408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.36
M. Arnold, Jung H. Cho
Field Programmable Robot Arrays (FPRAs) are micro-robots with onboard reconfigurable logic. We assume MEMS-based micro-robots like those developed by Donald et al. [2] as a foundation to build FPRAs. We present architecture of the FPRA which has the following components: MEMS Scratch-Drive- Actuator (SDA) micro-robot, LEDs with matching photo sensors, electrical docking ports and onboard programmable logic array of a new kind called Field Programmable One-Hot Arrays (FPOHAs). SDAs need an intermittent power supply. We present a hardware solution to powering the FPOHA (from the intermittent supply to the FPRA) and a parallax algorithm which is used to achieve docking of robot arrays, after which the FPOHA may be retasked.
{"title":"Parallax-Docking and Reconfiguration of Field Programmable Robot Arrays Using an Intermittently-Powered One-Hot Controller","authors":"M. Arnold, Jung H. Cho","doi":"10.1109/ReConFig.2009.36","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.36","url":null,"abstract":"Field Programmable Robot Arrays (FPRAs) are micro-robots with onboard reconfigurable logic. We assume MEMS-based micro-robots like those developed by Donald et al. [2] as a foundation to build FPRAs. We present architecture of the FPRA which has the following components: MEMS Scratch-Drive- Actuator (SDA) micro-robot, LEDs with matching photo sensors, electrical docking ports and onboard programmable logic array of a new kind called Field Programmable One-Hot Arrays (FPOHAs). SDAs need an intermittent power supply. We present a hardware solution to powering the FPOHA (from the intermittent supply to the FPRA) and a parallax algorithm which is used to achieve docking of robot arrays, after which the FPOHA may be retasked.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116551931","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.72
Alireza Rohani, H. Zarandi
this paper proposes a new reconfigurable architecture for Configuration Logic Block (CLB) in SRAM-based FPGAs. This architecture can correct Single Event Upset (SEU) by utilizing both Triple Modular Redundancy (TMR) and mapping technique. Since the proposed architecture can implement all the k-input Boolean functions, it can be used instead of Look-Up Table (LUT) in current-day SRAM-based FPGAs; moreover, the proposed architecture uses the same routing architecture which is presented in current-day FPGAs, so all CAD algorithms can be used in the employed design. Experimental results show that the proposed architecture can correct 100% SEU in the configuration memory of CLB without any user intervention or reconfiguration; moreover, the required area and the power consumption are respectively 136% and 195% more than the area and the power consumption that are required by the standard 16 ×1 LUT.
{"title":"A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs","authors":"Alireza Rohani, H. Zarandi","doi":"10.1109/ReConFig.2009.72","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.72","url":null,"abstract":"this paper proposes a new reconfigurable architecture for Configuration Logic Block (CLB) in SRAM-based FPGAs. This architecture can correct Single Event Upset (SEU) by utilizing both Triple Modular Redundancy (TMR) and mapping technique. Since the proposed architecture can implement all the k-input Boolean functions, it can be used instead of Look-Up Table (LUT) in current-day SRAM-based FPGAs; moreover, the proposed architecture uses the same routing architecture which is presented in current-day FPGAs, so all CAD algorithms can be used in the employed design. Experimental results show that the proposed architecture can correct 100% SEU in the configuration memory of CLB without any user intervention or reconfiguration; moreover, the required area and the power consumption are respectively 136% and 195% more than the area and the power consumption that are required by the standard 16 ×1 LUT.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128962810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.55
H. Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, N. Hiroi, H. Amano, Yuichiro Shibata, K. Oguri
Mathematical modeling and simulation of cellular systems are important processes in modern life science, to understand the behavior of life as a system. Kinetic model of a biochemical pathways is described as an ordinary differential system, consists of a variety of equations to represent velocity of corresponding chemical reactions. This paper describes a modular and automated approach to synthesize a custom HDL module for given biochemical model, that enables to build an optimal circuit to accelerate its simulation within a limited resource of an FPGA. As the result of evaluation, this method achieved reduction of logic usage by 10-60% while the overheads in frequency and pipeline depth is remaining about 10%.
{"title":"A Modular Approach to Heterogeneous Biochemical Model Simulation on an FPGA","authors":"H. Yamada, Yasunori Osana, Tomoya Ishimori, Tomonori Ooya, Masato Yoshimi, Yuri Nishikawa, Akira Funahashi, N. Hiroi, H. Amano, Yuichiro Shibata, K. Oguri","doi":"10.1109/ReConFig.2009.55","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.55","url":null,"abstract":"Mathematical modeling and simulation of cellular systems are important processes in modern life science, to understand the behavior of life as a system. Kinetic model of a biochemical pathways is described as an ordinary differential system, consists of a variety of equations to represent velocity of corresponding chemical reactions. This paper describes a modular and automated approach to synthesize a custom HDL module for given biochemical model, that enables to build an optimal circuit to accelerate its simulation within a limited resource of an FPGA. As the result of evaluation, this method achieved reduction of logic usage by 10-60% while the overheads in frequency and pipeline depth is remaining about 10%.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130495161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.15
T. Dorta, J. Jiménez, J. L. Martín, U. Bidarte, A. Astarloa
Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based design. Embedded systems have evolved from an uniprocessor to a multiprocessor approach, seeking better performance and less energy consumption. It is widely accepted that Multiprocessor Systems-on-Chip (MPSoC) will become the predominant class of embedded systems in future. In addition, advances in FPGA technology makes it possible to implement complete multiprocessor systems in a single FPGA. It allows fast design, implementation and testing of new devices. This paper presents an overview of FPGA-based multiprocessor systems. It describes the main characteristics, comments on several FPGA-based multiprocessor systems appearing in the research community in the last 5 years and discusses some of the challenges in this field.
{"title":"Overview of FPGA-Based Multiprocessor Systems","authors":"T. Dorta, J. Jiménez, J. L. Martín, U. Bidarte, A. Astarloa","doi":"10.1109/ReConFig.2009.15","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.15","url":null,"abstract":"Modern Systems-on-Chip (SoC) development is moving toward multiprocessor-based design. Embedded systems have evolved from an uniprocessor to a multiprocessor approach, seeking better performance and less energy consumption. It is widely accepted that Multiprocessor Systems-on-Chip (MPSoC) will become the predominant class of embedded systems in future. In addition, advances in FPGA technology makes it possible to implement complete multiprocessor systems in a single FPGA. It allows fast design, implementation and testing of new devices. This paper presents an overview of FPGA-based multiprocessor systems. It describes the main characteristics, comments on several FPGA-based multiprocessor systems appearing in the research community in the last 5 years and discusses some of the challenges in this field.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125973947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.34
Carlos Minchola, G. Sutter
This paper describes the design and implementation of a hardware module to calculate the decimal floating-point DFP) multiplication compliant with the current IEEE-754-2008 standard. The design proposed is made up of independent stages: IEEE-754 coder / decoder, decimal multiplier and rounding. The decimal multiplication is based on a previously designed BCD multiplier. The novelty is the design of a combinational and sequential architecture for rounding stage. Time performances and hardware requirements results are reported and evaluated. A decimal64 multiplication is able to be performed in 66 ns in a Virtex 4. The DFP multiplication presented supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To the best of author’s knowledge, this is the first publication to present an IEEE 754-2008 multiplier in FPGA.
{"title":"A FPGA IEEE-754-2008 Decimal64 Floating-Point Multiplier","authors":"Carlos Minchola, G. Sutter","doi":"10.1109/ReConFig.2009.34","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.34","url":null,"abstract":"This paper describes the design and implementation of a hardware module to calculate the decimal floating-point DFP) multiplication compliant with the current IEEE-754-2008 standard. The design proposed is made up of independent stages: IEEE-754 coder / decoder, decimal multiplier and rounding. The decimal multiplication is based on a previously designed BCD multiplier. The novelty is the design of a combinational and sequential architecture for rounding stage. Time performances and hardware requirements results are reported and evaluated. A decimal64 multiplication is able to be performed in 66 ns in a Virtex 4. The DFP multiplication presented supports operations on the decimal64 format and it is easily extendable for the decimal128 format. To the best of author’s knowledge, this is the first publication to present an IEEE 754-2008 multiplier in FPGA.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128436942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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