Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.31
Stephanie Drzevitzky, U. Kastens, M. Platzner
Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity, but at the same time poses new challenges for security and safety. In this paper, we present proof-carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes a key concept from software security, known as proof-carrying code, into the reconfigurable hardware domain. We outline the PCH concept and discuss runtime combinational equivalence checking as a first verification problem applying the concept. We present a tool flow and experimental results demonstrating the feasibility and potential of the PCH approach.
{"title":"Proof-Carrying Hardware: Towards Runtime Verification of Reconfigurable Modules","authors":"Stephanie Drzevitzky, U. Kastens, M. Platzner","doi":"10.1109/ReConFig.2009.31","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.31","url":null,"abstract":"Dynamically reconfigurable hardware combines hardware performance with software-like flexibility and finds increasing use in networked systems. The capability to load hardware modules at runtime provides these systems with an unparalleled degree of adaptivity, but at the same time poses new challenges for security and safety. In this paper, we present proof-carrying hardware (PCH) as a novel approach to reconfigurable system security. PCH takes a key concept from software security, known as proof-carrying code, into the reconfigurable hardware domain. We outline the PCH concept and discuss runtime combinational equivalence checking as a first verification problem applying the concept. We present a tool flow and experimental results demonstrating the feasibility and potential of the PCH approach.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127025978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.42
M. Dunham, Z. Baker, M. Stettler, M. Pigue, P. Graham, E. Schmierer, John Power
Los Alamos has recently completed the latest in a series of Reconfigurable Software Radios, which incorporates several key innovations in both hardware design and algorithms. Due to our focus on satellite applications, each design must extract the best size, weight, and power performance possible from the ensemble of Commodity Off-the-Shelf (COTS) parts available at the time of design. In this case we have achieved 1 TeraOps/second signal processing on a 1920 Megabit/second datastream, while using only 53 Watts mains power, 5.5 kg, and 3 liters. This processing capability enables very advanced algorithms such as our wideband RF compression scheme to operate remotely, allowing network bandwidth constrained applications to deliver previously unattainable performance.
{"title":"High Efficiency Space-Based Software Radio Architectures: A Minimum Size, Weight, and Power TeraOps Processor","authors":"M. Dunham, Z. Baker, M. Stettler, M. Pigue, P. Graham, E. Schmierer, John Power","doi":"10.1109/ReConFig.2009.42","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.42","url":null,"abstract":"Los Alamos has recently completed the latest in a series of Reconfigurable Software Radios, which incorporates several key innovations in both hardware design and algorithms. Due to our focus on satellite applications, each design must extract the best size, weight, and power performance possible from the ensemble of Commodity Off-the-Shelf (COTS) parts available at the time of design. In this case we have achieved 1 TeraOps/second signal processing on a 1920 Megabit/second datastream, while using only 53 Watts mains power, 5.5 kg, and 3 liters. This processing capability enables very advanced algorithms such as our wideband RF compression scheme to operate remotely, allowing network bandwidth constrained applications to deliver previously unattainable performance.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126157450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-09DOI: 10.1109/ReConFig.2009.74
N. Tanida, M. Inaba, K. Hiraki, Takeshi Yoshino
Efficient utilization of massive data, such as full-text search has become important in view of the growing needs for Web search and genome analysis. High-speed search and small storage space are required to handle massive amounts of data. For high-speed search, generally, a data structure such as index which needs additional storage space is required. Recently, compressed suffix array, which is a data structure with an indexable dictionary that can be used to compress data to its information-theoretic lower bound, has been proposed. The distinctive feature of this array is that it enables direct data retrieval without decompression from the compressed data. Further, theoretically, the computational complexity of data retrieval is the same for both compressed and uncompressed data when we assume that rank operation involving the bit vector can be executed in constant time; this rank operation returns the number of occurrences of smaller elements. Practically, rank operation involves many bit-manipulations and random access to the memory. Hence, this constant time is not negligible, and as a result, data retrieval using compressed suffix array is relatively slower than that using plain suffix array. Although compression to create an indexable dictionary is performed only once, data retrieval queries occur repeatedly. Hence, high speed rank operations involving bit vectors are essential for compressed suffix arrays. We propose a FPGA-based hardware accelerator for full-text search (HAFTS) with compressed suffix array. FPGA helps speedup rank operation for compressed suffix array by enabling many bit calculations performed simultaneously and controlling the order of memory accesses. We conduct performance simulations of HAFTS. We consider a development board on which FPGA is connected to DDR2-800 SDRAM by a 64-bit bus as our model. We evaluate the performance of HAFTS by comparing it with that of software implementation. As a result, we conclude that the search speed of FPGA-based HAFTS is seven times faster than that of software implementation.
{"title":"Hardware Accelerator for Full-Text Search (HAFTS) with Succinct Data Structure","authors":"N. Tanida, M. Inaba, K. Hiraki, Takeshi Yoshino","doi":"10.1109/ReConFig.2009.74","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.74","url":null,"abstract":"Efficient utilization of massive data, such as full-text search has become important in view of the growing needs for Web search and genome analysis. High-speed search and small storage space are required to handle massive amounts of data. For high-speed search, generally, a data structure such as index which needs additional storage space is required. Recently, compressed suffix array, which is a data structure with an indexable dictionary that can be used to compress data to its information-theoretic lower bound, has been proposed. The distinctive feature of this array is that it enables direct data retrieval without decompression from the compressed data. Further, theoretically, the computational complexity of data retrieval is the same for both compressed and uncompressed data when we assume that rank operation involving the bit vector can be executed in constant time; this rank operation returns the number of occurrences of smaller elements. Practically, rank operation involves many bit-manipulations and random access to the memory. Hence, this constant time is not negligible, and as a result, data retrieval using compressed suffix array is relatively slower than that using plain suffix array. Although compression to create an indexable dictionary is performed only once, data retrieval queries occur repeatedly. Hence, high speed rank operations involving bit vectors are essential for compressed suffix arrays. We propose a FPGA-based hardware accelerator for full-text search (HAFTS) with compressed suffix array. FPGA helps speedup rank operation for compressed suffix array by enabling many bit calculations performed simultaneously and controlling the order of memory accesses. We conduct performance simulations of HAFTS. We consider a development board on which FPGA is connected to DDR2-800 SDRAM by a 64-bit bus as our model. We evaluate the performance of HAFTS by comparing it with that of software implementation. As a result, we conclude that the search speed of FPGA-based HAFTS is seven times faster than that of software implementation.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115144561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ReConFig.2009.69
J. Delorme, A. Nafkha, P. Leray, C. Moy
We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (Network on Chip) structure inside a FPGA. In the context of a SDR (Software Defined Radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology for PR management regarding the timing performances obtained in a real implementation. PR timing is a key point to make SDR approach realistic. These results show that using PR, FPGAs combine the flexibility of SW (software) and the processing power of HW (hardware). This makes PR a tremendous enabling technology for SDR. These results are based on a new IP managing the ICAP component that allows a gain in time of a rate of 124 comparing to the provided OPBHWICAP. Moreover, we have integrated a methodology which can reduce significantly the bitstream size and consequently the reconfiguration duration. The results presented in this paper show that PR reconfiguration time can go downto a few tens of microseconds. This makes PR really attractive for SDR design or any other highly demanding real-time applications.
{"title":"New OPBHWICAP Interface for Realtime Partial Reconfiguration of FPGA","authors":"J. Delorme, A. Nafkha, P. Leray, C. Moy","doi":"10.1109/ReConFig.2009.69","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.69","url":null,"abstract":"We propose in this paper, a timing analysis of dynamic partial reconfiguration (PR) applied to a NoC (Network on Chip) structure inside a FPGA. In the context of a SDR (Software Defined Radio) example, PR is used to dynamically reconfigure a baseband processing block of a 4G telecommunication chain running in real-time (data rates up to 100 Mbps). The results presented show the validity of our methodology for PR management regarding the timing performances obtained in a real implementation. PR timing is a key point to make SDR approach realistic. These results show that using PR, FPGAs combine the flexibility of SW (software) and the processing power of HW (hardware). This makes PR a tremendous enabling technology for SDR. These results are based on a new IP managing the ICAP component that allows a gain in time of a rate of 124 comparing to the provided OPBHWICAP. Moreover, we have integrated a methodology which can reduce significantly the bitstream size and consequently the reconfiguration duration. The results presented in this paper show that PR reconfiguration time can go downto a few tens of microseconds. This makes PR really attractive for SDR design or any other highly demanding real-time applications.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130360432","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ReConFig.2009.56
Antoine Trouvé, L. Gauthier, Takayuki Kando, Benoit Ryder, S. Pouzols, P. Rao, N. Yoshimatsu, K. Murakami
In this paper we propose and evaluate our platform to accelerate applications using custom instruction set extensions. We use a dynamically reconfigurable functional unit (DRFU) to execute the application specific custom instructions generated by our compiler framework. We explore two architectures with different computational granularities for the DRFU (look-up table and ALU based) and evaluate this framework using security and cryptographic applications as a case study. Our results indicate that the use of application specific instruction set extensions reduce code size by 10% and achieve a maximum speedup of 165% (41% on average).
{"title":"Accelerating Cryptographic Applications Using Dynamically Reconfigurable Functional Units","authors":"Antoine Trouvé, L. Gauthier, Takayuki Kando, Benoit Ryder, S. Pouzols, P. Rao, N. Yoshimatsu, K. Murakami","doi":"10.1109/ReConFig.2009.56","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.56","url":null,"abstract":"In this paper we propose and evaluate our platform to accelerate applications using custom instruction set extensions. We use a dynamically reconfigurable functional unit (DRFU) to execute the application specific custom instructions generated by our compiler framework. We explore two architectures with different computational granularities for the DRFU (look-up table and ALU based) and evaluate this framework using security and cryptographic applications as a case study. Our results indicate that the use of application specific instruction set extensions reduce code size by 10% and achieve a maximum speedup of 165% (41% on average).","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116619059","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-12-01DOI: 10.1109/ReConFig.2009.59
A. Shahbahrami, M. Ahmadi, Stephan Wong, K. Bertels
The Discrete Wavelet Transform (DWT) is an important operation in applications of digital signal processing. In this paper, we review several traditional DWT implementation approaches, e.g., application-specific integrated circuits, field-programmable gate arrays, digital signal processors, general-purpose processors, and graphic processors, and discuss their limitations in terms of performance and flexibility. In order to provide both high-performance and flexibility, we propose a new approach, namely a parallel architecture exploiting the collaboration of reconfigurable processing elements in grid computing. Grid computing can exploit the task level parallelism to execute the 2D DWT. In addition, reconfigurable computing offers a flexible platform and can be used as hardware accelerators. We mapped the DWT in a grid. Our experimental results show that speedups of up to 4.1x can be achieved.
{"title":"A New Approach to Implement Discrete Wavelet Transform Using Collaboration of Reconfigurable Elements","authors":"A. Shahbahrami, M. Ahmadi, Stephan Wong, K. Bertels","doi":"10.1109/ReConFig.2009.59","DOIUrl":"https://doi.org/10.1109/ReConFig.2009.59","url":null,"abstract":"The Discrete Wavelet Transform (DWT) is an important operation in applications of digital signal processing. In this paper, we review several traditional DWT implementation approaches, e.g., application-specific integrated circuits, field-programmable gate arrays, digital signal processors, general-purpose processors, and graphic processors, and discuss their limitations in terms of performance and flexibility. In order to provide both high-performance and flexibility, we propose a new approach, namely a parallel architecture exploiting the collaboration of reconfigurable processing elements in grid computing. Grid computing can exploit the task level parallelism to execute the 2D DWT. In addition, reconfigurable computing offers a flexible platform and can be used as hardware accelerators. We mapped the DWT in a grid. Our experimental results show that speedups of up to 4.1x can be achieved.","PeriodicalId":325631,"journal":{"name":"2009 International Conference on Reconfigurable Computing and FPGAs","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130369393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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