Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115394
M. Verhappen, P. V. D. Putten, J. Voeten
We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an increasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a structured and confident transition from conceptual system-level models to hardware descriptions. It appears that the design gap is caused by differences between language primitives and underlying concepts of system-level design languages and hardware description languages. We substantiate the need for expressive system-level modeling concepts and show that the gap is actually caused by a fundamental interpretation mismatch between models and descriptions. Based on a comparison of existing system-level synthesis methods with the interpretation gap, we propose to decrease the gap by using modeling patterns.
{"title":"On the fundamental design gap in terabit per second packet switching","authors":"M. Verhappen, P. V. D. Putten, J. Voeten","doi":"10.1109/DSD.2002.1115394","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115394","url":null,"abstract":"We discuss the gap we experience in an industrial design path of high-speed packet switches. As bandwidth demand exceeds progress in CMOS technology, system architects are forced to abandon familiar design solutions and make fundamental changes to their architectures at an increasingly faster pace. We investigate design methods to decrease the risk of such changes and to provide a structured and confident transition from conceptual system-level models to hardware descriptions. It appears that the design gap is caused by differences between language primitives and underlying concepts of system-level design languages and hardware description languages. We substantiate the need for expressive system-level modeling concepts and show that the gap is actually caused by a fundamental interpretation mismatch between models and descriptions. Based on a comparison of existing system-level synthesis methods with the interpretation gap, we propose to decrease the gap by using modeling patterns.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"41 21","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114087980","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115393
Ronny Frevert, Steffen Rülke, Torsten Schäfer, F. Dresig
Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, compliance test and quality estimation of reusable components for the system design. This paper summarizes the related requirements on HDL code checkers derived from a concrete industrial environment. A proposed evaluation table will help to evaluate and select HDL code checkers for particular requirements.
{"title":"Use of HDL code checkers to support the IP entrance check - a requirement analysis","authors":"Ronny Frevert, Steffen Rülke, Torsten Schäfer, F. Dresig","doi":"10.1109/DSD.2002.1115393","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115393","url":null,"abstract":"Systems for coding style analysis, so called hardware description languages (HDL) code checkers, can accomplish an important contribution for the IP entrance check, that means selection, compliance test and quality estimation of reusable components for the system design. This paper summarizes the related requirements on HDL code checkers derived from a concrete industrial environment. A proposed evaluation table will help to evaluate and select HDL code checkers for particular requirements.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"118 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134516508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115389
Martin Feldhofer, T. Trathnigg, Bernd Schnitzer
This paper describes an efficient implementation of a crypto arithmetic unit, which computes the modular-operations of addition, multiplication, and inversion in prime fields. These calculations are important for an application in elliptic curve cryptography (ECC). The hardware is designed in a self-timed and low-power approach. The paper discusses the pros and cons of this approach compared to a synchronous implementation.
{"title":"A self-timed arithmetic unit for elliptic curve cryptography","authors":"Martin Feldhofer, T. Trathnigg, Bernd Schnitzer","doi":"10.1109/DSD.2002.1115389","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115389","url":null,"abstract":"This paper describes an efficient implementation of a crypto arithmetic unit, which computes the modular-operations of addition, multiplication, and inversion in prime fields. These calculations are important for an application in elliptic curve cryptography (ECC). The hardware is designed in a self-timed and low-power approach. The paper discusses the pros and cons of this approach compared to a synchronous implementation.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126960470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115358
L. Feijs, Paul Gorissen, J. Trescher
In this paper we report on the development of a language which is especially tailored to the specification and simulation of microprocessor operations and parallel instructions. The approach is rigorous, and it combines the naturalness and readability of the traditional pseudocode with the formality and rigour of instruction specifications in the programming language C (but without the disadvantages of the latter). The underlying semantic model has been formalized by the equations of an appropriate denotational semantic model. The specifications can be used for a variety of purposes, such as the generation of a data book and other on-line documentation, the generation of a simulator that allows functional testing of programs even before the hardware has been designed and implemented, and the generation of a test suite to perform functional tests of a given design or real chip.
{"title":"Specification and simulation of microprocessor operations and parallel instructions","authors":"L. Feijs, Paul Gorissen, J. Trescher","doi":"10.1109/DSD.2002.1115358","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115358","url":null,"abstract":"In this paper we report on the development of a language which is especially tailored to the specification and simulation of microprocessor operations and parallel instructions. The approach is rigorous, and it combines the naturalness and readability of the traditional pseudocode with the formality and rigour of instruction specifications in the programming language C (but without the disadvantages of the latter). The underlying semantic model has been formalized by the equations of an appropriate denotational semantic model. The specifications can be used for a variety of purposes, such as the generation of a data book and other on-line documentation, the generation of a simulator that allows functional testing of programs even before the hardware has been designed and implemented, and the generation of a test suite to perform functional tests of a given design or real chip.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129028009","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115357
P. Andersson, K. Kuchcinski, K. Nordberg, P. Doherty
Recently substantial research has been devoted to Unmanned Aerial Vehicles (UAVs). One of a UAV's most demanding subsystem is vision. The vision subsystem must dynamically combine different algorithms as the UAVs goal and surrounding change. To fully utilize the available hardware, a run time system must be able to vary the quality and the size of regions the algorithms are applied to, as the number of image processing tasks changes. To allow this the run time system and the underlying computational model must be integrated. In this paper we present a computational model suitable for integration with a run time system. The computational model is called Image Processing Data Flow Graph (IP-DFG). IP-DFG has been developed for modeling of complex image processing algorithms. IP-DFG is based on data flow graphs, but has been extended with hierarchy and new rules for token consumption, which makes the computational model more flexible and more suitable for human interaction. In this paper we also show that IP-DFGs are suitable for modelling expressions, including data dependent decisions and iterations, which are common in complex image processing algorithms.
{"title":"Integrating a computational model and a run time system for image processing on a UAV","authors":"P. Andersson, K. Kuchcinski, K. Nordberg, P. Doherty","doi":"10.1109/DSD.2002.1115357","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115357","url":null,"abstract":"Recently substantial research has been devoted to Unmanned Aerial Vehicles (UAVs). One of a UAV's most demanding subsystem is vision. The vision subsystem must dynamically combine different algorithms as the UAVs goal and surrounding change. To fully utilize the available hardware, a run time system must be able to vary the quality and the size of regions the algorithms are applied to, as the number of image processing tasks changes. To allow this the run time system and the underlying computational model must be integrated. In this paper we present a computational model suitable for integration with a run time system. The computational model is called Image Processing Data Flow Graph (IP-DFG). IP-DFG has been developed for modeling of complex image processing algorithms. IP-DFG is based on data flow graphs, but has been extended with hierarchy and new rules for token consumption, which makes the computational model more flexible and more suitable for human interaction. In this paper we also show that IP-DFGs are suitable for modelling expressions, including data dependent decisions and iterations, which are common in complex image processing algorithms.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"205 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117085724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115386
Željko Vujović
This paper presents algorithm based on A-mod of ultrasound signal for detection of borderlines and parameters of pictures for automated diagnostic, in pictures provided by the intravascular ultrasound system (IVUS) with 64 transducers. The subject of consideration was acoustic characteristics of blood and wall of blood vessel for propagation of ultrasound waves for solving the existing problem. Alternative ways of the problem were considered and enumerated. The advantages and limitations of the proposed solution were also considered. The method of spatial and temporal sampling of ultrasound signal was used. The results showed that the algorithm is suitable because it is adapted to the specifications of providing pictures by the intravascular ultrasound system.
{"title":"Work out of the algorithm based on A-mod for detection of borderlines in images provided by the intravascular ultrasound system (IVUS) with 64 transducers","authors":"Željko Vujović","doi":"10.1109/DSD.2002.1115386","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115386","url":null,"abstract":"This paper presents algorithm based on A-mod of ultrasound signal for detection of borderlines and parameters of pictures for automated diagnostic, in pictures provided by the intravascular ultrasound system (IVUS) with 64 transducers. The subject of consideration was acoustic characteristics of blood and wall of blood vessel for propagation of ultrasound waves for solving the existing problem. Alternative ways of the problem were considered and enumerated. The advantages and limitations of the proposed solution were also considered. The method of spatial and temporal sampling of ultrasound signal was used. The results showed that the algorithm is suitable because it is adapted to the specifications of providing pictures by the intravascular ultrasound system.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115818177","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115346
A. Habibi, S. Tahar, A. Ghazel
In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. We then prove for each unit that its hardware description implies its behavioral specification. Using the simplified (abstracted) description of the units we have been able to greatly reduce the cost of deducing the behavior of the processor instruction set from the hardware implementation of the processor units. The proposed methodology creates a new representation of the processor at each iteration such that its complexity can be handled by the theorem prover. This allowed us to make a proof of the full instruction set of this processor.
{"title":"Formal verification of a DSP chip using an iterative approach","authors":"A. Habibi, S. Tahar, A. Ghazel","doi":"10.1109/DSD.2002.1115346","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115346","url":null,"abstract":"In this paper we describe a methodology for the formal verification of a DSP chip using the HOL theorem prover. We used an iterative method to specify both the behavioral and structural descriptions of the processor. Our methodology consists of first simplifying the representations of the DSP units. We then prove for each unit that its hardware description implies its behavioral specification. Using the simplified (abstracted) description of the units we have been able to greatly reduce the cost of deducing the behavior of the processor instruction set from the hardware implementation of the processor units. The proposed methodology creates a new representation of the processor at each iteration such that its complexity can be handled by the theorem prover. This allowed us to make a proof of the full instruction set of this processor.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"31 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131508627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115381
E. Jamro, K. Wiatr
This paper reviews different architectural solutions for calculating constant coefficient convolution operation in FPGAs. At first, different architectures of multipliers are approached, as the multiplication is the most complex operation performed in the convolutions. Nevertheless, disregarding the multiplier entity allows for further circuit optimisations. Therefore look-up-table (LUT) based convolver (LC) versus the sum of the LUT-based Multipliers are described. Further, an alternative technique - (Parallel) distributed arithmetic convolver (DAC) is approached. The key issue of this paper is, however, a novel architectural solution: irregular distributed arithmetic convolver (IDAC) which, in comparison to the DAC, has an irregular form, and therefore allows for better circuit optimisation. All architectural solutions described hereby can be automatically generated by the automated tool for generation convolvers in FPGAs (AuToCon).
{"title":"Constant coefficient convolution implemented in FPGAs","authors":"E. Jamro, K. Wiatr","doi":"10.1109/DSD.2002.1115381","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115381","url":null,"abstract":"This paper reviews different architectural solutions for calculating constant coefficient convolution operation in FPGAs. At first, different architectures of multipliers are approached, as the multiplication is the most complex operation performed in the convolutions. Nevertheless, disregarding the multiplier entity allows for further circuit optimisations. Therefore look-up-table (LUT) based convolver (LC) versus the sum of the LUT-based Multipliers are described. Further, an alternative technique - (Parallel) distributed arithmetic convolver (DAC) is approached. The key issue of this paper is, however, a novel architectural solution: irregular distributed arithmetic convolver (IDAC) which, in comparison to the DAC, has an irregular form, and therefore allows for better circuit optimisation. All architectural solutions described hereby can be automatically generated by the automated tool for generation convolvers in FPGAs (AuToCon).","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132325717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115350
I. Milentijevic, V. Ciric, T. Tokic, O. Vojinovic
The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor onto the fixed size array is described in this paper. The transformation of original data flow graph (DFG) for bit-plane architecture that provides the successful application of the folding technique with changeable folding sets is presented. The involving of changeable folding sets in the synthesized folded architecture allows the reducing of folding factor according to the coefficient length increasing the throughput of the folded system.
{"title":"Folded bit-plane FIR filter architecture with changeable folding factor","authors":"I. Milentijevic, V. Ciric, T. Tokic, O. Vojinovic","doi":"10.1109/DSD.2002.1115350","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115350","url":null,"abstract":"The application of folding technique to the bit-plane systolic FIR filter architecture that enables the implementation of changeable folding factor onto the fixed size array is described in this paper. The transformation of original data flow graph (DFG) for bit-plane architecture that provides the successful application of the folding technique with changeable folding sets is presented. The involving of changeable folding sets in the synthesized folded architecture allows the reducing of folding factor according to the coefficient length increasing the throughput of the folded system.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121516867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115379
O. Cadenas, G. Megson
This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.
{"title":"Improving mW/MHz ratio in FPGAs pipelined designs","authors":"O. Cadenas, G. Megson","doi":"10.1109/DSD.2002.1115379","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115379","url":null,"abstract":"This paper presents a simple clocking technique to migrate classical synchronous pipelined designs to a synchronous functional-equivalent alternative system in the context of FPGAs. When the new pipelined design runs at the same throughput of the original design, around 30% better mW/MHz ratio was observed in Virtex-based FPGA circuits. The evaluation is done using a simple but representative and practical systolic design as an example. The technique in essence is a simple replacement of the clocking mechanism for the pipe-storage elements; however no extra design effort is needed. The results show that the proposed technique allows immediate power and area-time savings of existing designs rather than exploring potential benefits by a new logic design to the problem using the classic pipeline clocking mechanism.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114717494","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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