Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115367
P. Amblard, Fabienne Lagnier, Michel Lévy
We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. These complete and optimized representations help the designer to understand the accurate behaviour of the circuit. This deep understanding is a prerequisite for any verification or test process. An example is fully presented to illustrate our method. This simple pipelined processor comes from our experience in computer architecture and digital design education.
{"title":"Using formal tools to study complex circuits behaviour","authors":"P. Amblard, Fabienne Lagnier, Michel Lévy","doi":"10.1109/DSD.2002.1115367","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115367","url":null,"abstract":"We use a formal tool to extract Finite State Machines (FSM) based representations (lists of states and transitions) of sequential circuits described by flip-flops and gates. These complete and optimized representations help the designer to understand the accurate behaviour of the circuit. This deep understanding is a prerequisite for any verification or test process. An example is fully presented to illustrate our method. This simple pipelined processor comes from our experience in computer architecture and digital design education.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"11 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132933424","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115376
Aitor Ibarra, J. Mendias, J. Lanchares, J. Hidalgo, R. Hermida
One of the goals of a high level synthesis process is to minimize the circuit implementation cost. Since the minimization problem associated with those transformations is NP complete, in this work we present an evolutionary algorithm that optimize circuit specifications by means of a special type of genetic operator. We have named this operator algebraic mutation, carried out with the help of algebraic equations. This work can be classified within the algebraic optimization of equational specifications of circuits by using genetic techniques. We have applied this technique to a simple circuit equational specification and to a much more complex algebraic equation. In the first case our algorithm simplifies the equation until the optimum specification is found and in the second a solution improving the former is always obtained, and when we increase the population size, the optimum solution is also found.
{"title":"Optimization of equational specifications using genetic techniques","authors":"Aitor Ibarra, J. Mendias, J. Lanchares, J. Hidalgo, R. Hermida","doi":"10.1109/DSD.2002.1115376","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115376","url":null,"abstract":"One of the goals of a high level synthesis process is to minimize the circuit implementation cost. Since the minimization problem associated with those transformations is NP complete, in this work we present an evolutionary algorithm that optimize circuit specifications by means of a special type of genetic operator. We have named this operator algebraic mutation, carried out with the help of algebraic equations. This work can be classified within the algebraic optimization of equational specifications of circuits by using genetic techniques. We have applied this technique to a simple circuit equational specification and to a much more complex algebraic equation. In the first case our algorithm simplifies the equation until the optimum specification is found and in the second a solution improving the former is always obtained, and when we increase the population size, the optimum solution is also found.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132231102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115378
Domingo Benítez
This paper describes a performance evaluation of image-processing applications on FPGA-based coprocessors that are part of general-purpose computers. Our experiments show that the maximum speed-up depends on the amount of data processed by the coprocessor. Taking images with 256/spl times/256 pixels, a moderate FPGA capacity of 10E+5 CLBs provides two orders of magnitude of performance improvement over a Pentium III processor for most of our benchmarks. However, memory organization and host bus degrade these results. Those benchmarks that can exhibit high performance improvement would require about 200 memory banks of 256 bytes and a host bandwidth as high as 30 GB/s. Based on our quantitative approach, it can be explained why some currently available FPGA-based coprocessors do not provide the achievable level of performance for some image-processing applications.
{"title":"Performance of remote FPGA-based coprocessors for image-processing applications","authors":"Domingo Benítez","doi":"10.1109/DSD.2002.1115378","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115378","url":null,"abstract":"This paper describes a performance evaluation of image-processing applications on FPGA-based coprocessors that are part of general-purpose computers. Our experiments show that the maximum speed-up depends on the amount of data processed by the coprocessor. Taking images with 256/spl times/256 pixels, a moderate FPGA capacity of 10E+5 CLBs provides two orders of magnitude of performance improvement over a Pentium III processor for most of our benchmarks. However, memory organization and host bus degrade these results. Those benchmarks that can exhibit high performance improvement would require about 200 memory banks of 256 bytes and a host bandwidth as high as 30 GB/s. Based on our quantitative approach, it can be explained why some currently available FPGA-based coprocessors do not provide the achievable level of performance for some image-processing applications.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130360832","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115377
P. Kerntopf
Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose reversible gates are also shown.
{"title":"Synthesis of multipurpose reversible logic gates","authors":"P. Kerntopf","doi":"10.1109/DSD.2002.1115377","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115377","url":null,"abstract":"Regular reversible logic circuits, i.e. consisting of identical reversible gates, each of which is uniformly connected to its neighbors, have small garbage. Reversible gates realizing simultaneously some useful functions are very effective in synthesis of regular reversible logic circuits. In the paper we show how to create multipurpose reversible gates. Examples of efficient binary multipurpose reversible gates are also shown.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116296671","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115385
O. Peñalba, J. Mendias, R. Hermida
The computations of a system whose behavior varies depending on the value of some conditions may present a property called mutual exclusiveness. This property, responsible for the degree of conditional reuse achievable after a high-level synthesis (HLS) process, is intrinsic to the behavior. But sometimes it is only partially reflected in the actual description written by a designer, leading to worse implementations. Our algorithm explores in an efficient manner the real mutual exclusiveness of the behavior, independently of the description style. It performs a transformation of the input description that allows the HLS tools to obtain better circuits in terms of the area saving due to conditional reuse.
{"title":"Source code transformation to improve conditional hardware reuse","authors":"O. Peñalba, J. Mendias, R. Hermida","doi":"10.1109/DSD.2002.1115385","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115385","url":null,"abstract":"The computations of a system whose behavior varies depending on the value of some conditions may present a property called mutual exclusiveness. This property, responsible for the degree of conditional reuse achievable after a high-level synthesis (HLS) process, is intrinsic to the behavior. But sometimes it is only partially reflected in the actual description written by a designer, leading to worse implementations. Our algorithm explores in an efficient manner the real mutual exclusiveness of the behavior, independently of the description style. It performs a transformation of the input description that allows the HLS tools to obtain better circuits in terms of the area saving due to conditional reuse.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127968435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115390
Giuseppe Notarangelo, Marco Gibilaro, F. Pappalardo, A. Pennisi, G. Palumbo
In this paper a low power strategy for a TFT controller is described. The design is based on a general controller for high resolutions graphic display data. The main improvements introduced concerns not only an effective power reduction of about 65.42%, compared with the original module, but also the new feature that allows one to choose among six different functional configurations. The new TFT controller works also with the new display generation such as organic LED (OLED) type, in this case we introduce the possibility to power down the backlighting neon. Measures are made with design compiler (Synopsys) to compute the TFT controller power consumption and the total cell area before and after our modifications.
{"title":"Low power strategy for a TFT controller","authors":"Giuseppe Notarangelo, Marco Gibilaro, F. Pappalardo, A. Pennisi, G. Palumbo","doi":"10.1109/DSD.2002.1115390","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115390","url":null,"abstract":"In this paper a low power strategy for a TFT controller is described. The design is based on a general controller for high resolutions graphic display data. The main improvements introduced concerns not only an effective power reduction of about 65.42%, compared with the original module, but also the new feature that allows one to choose among six different functional configurations. The new TFT controller works also with the new display generation such as organic LED (OLED) type, in this case we introduce the possibility to power down the backlighting neon. Measures are made with design compiler (Synopsys) to compute the TFT controller power consumption and the total cell area before and after our modifications.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128373238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115366
R. Goot, I. Levin, S. Ostanin
In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the possible latency for an FSM, while the real latency relates to the certain implementation of the FSM A method for investigation of latencies for online checking FSMs is described This technique is based on selection of trajectories of the Markov chain, which describes behavior of the fault free FSM as well as the faulty FSM We also estimate the lowest bound for an average latency. This estimation may be useful at an initial stage of the design when information concerning requirements to the FSM and conditions of its functioning is limited.
{"title":"Fault latencies of concurrent checking FSMs","authors":"R. Goot, I. Levin, S. Ostanin","doi":"10.1109/DSD.2002.1115366","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115366","url":null,"abstract":"In this paper we introduce concepts of a potential fault latency and a real fault latency for Finite State Machines (FSMs). The potential latency defines a minimal value of the possible latency for an FSM, while the real latency relates to the certain implementation of the FSM A method for investigation of latencies for online checking FSMs is described This technique is based on selection of trajectories of the Markov chain, which describes behavior of the fault free FSM as well as the faulty FSM We also estimate the lowest bound for an average latency. This estimation may be useful at an initial stage of the design when information concerning requirements to the FSM and conditions of its functioning is limited.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"20 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114034216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115391
Khushwinder Jasrotia, Jianwen Zhu
It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent. This paper describes the implementation of a buddy system based soft IP core after a review of common memory allocation algorithms. The study also investigates the impact of different IP configuration and different synthesis strategies on the synthesis quality.
{"title":"Hardware implementation of a memory allocator","authors":"Khushwinder Jasrotia, Jianwen Zhu","doi":"10.1109/DSD.2002.1115391","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115391","url":null,"abstract":"It is generally felt that the complexity of system-on-chip (SOC) can only be addressed by intellectual-property (IP) based design. While IPs such as processor cores, memories, and bus controllers are being offered by many vendors, IP cores for dynamic memory management, an important task for any complex application, have been close to non-existent. This paper describes the implementation of a buddy system based soft IP core after a review of common memory allocation algorithms. The study also investigates the impact of different IP configuration and different synthesis strategies on the synthesis quality.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115343443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115361
B. Theelen, A. Verschueren
Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (M/spl mu/P). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper we explore the main design issues of the architecture platform on which the M/spl mu/P is based.
{"title":"Architecture design of a scalable single-chip multi-processor","authors":"B. Theelen, A. Verschueren","doi":"10.1109/DSD.2002.1115361","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115361","url":null,"abstract":"Now that system-on-chip technology is emerging, single-chip multi-processors are becoming feasible. A key problem of designing such systems is however the complexity of their interconnect and memory architecture. An example of a single-chip multi-processor for real-time (embedded) systems is the Multi Micro Processor (M/spl mu/P). Its architecture consists of a scalable number of identical master processors and a configurable set of shared co-processors. Additionally, an on-chip real-time operating system kernel is included to support transparent multi-tasking over the set of master processors. In this paper we explore the main design issues of the architecture platform on which the M/spl mu/P is based.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129964651","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2002-09-04DOI: 10.1109/DSD.2002.1115351
Yinshui Xia, A. Almaini
In this paper, polarity transform is introduced to identify low power XOR gate decompositions. It is pointed out that the previous solutions for XOR gate decomposition are not optimal. Based on searching best polarity for low power dissipation, a new algorithm is proposed and implemented in C. The experimental results show improved switching activities compared with previous publications.
{"title":"Best polarity for low power XOR gate decomposition","authors":"Yinshui Xia, A. Almaini","doi":"10.1109/DSD.2002.1115351","DOIUrl":"https://doi.org/10.1109/DSD.2002.1115351","url":null,"abstract":"In this paper, polarity transform is introduced to identify low power XOR gate decompositions. It is pointed out that the previous solutions for XOR gate decomposition are not optimal. Based on searching best polarity for low power dissipation, a new algorithm is proposed and implemented in C. The experimental results show improved switching activities compared with previous publications.","PeriodicalId":330609,"journal":{"name":"Proceedings Euromicro Symposium on Digital System Design. Architectures, Methods and Tools","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130919814","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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