The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing, forces a strategy to reduce the number of different configurations used for testing purposes. After finding the optimal solutions for the elementary structures of the Logic block, Multiplexers and Look-Up Tables, the problem of testing interconnected elementary structures is addressed. The method is illustrated using an elementary structure and then applied to a popular FPGA (XILINX 3000 family) where a reduced set of configurations (5) and their corresponding test sequences is found to cover all (100%) the Configurable Logic Block faults modelled.
{"title":"Test pattern and test configuration generation methodology for the logic of RAM-based FPGA","authors":"M. Renovell, J. Portal, J. Figueras, Y. Zorian","doi":"10.1109/ATS.1997.643967","DOIUrl":"https://doi.org/10.1109/ATS.1997.643967","url":null,"abstract":"The test of the Configurable Logic Blocks of RAM based FPGAs under a Stuck-At fault model has been studied. The high cost of changing the configuration, by reprogramming the FPGA during testing, forces a strategy to reduce the number of different configurations used for testing purposes. After finding the optimal solutions for the elementary structures of the Logic block, Multiplexers and Look-Up Tables, the problem of testing interconnected elementary structures is addressed. The method is illustrated using an elementary structure and then applied to a popular FPGA (XILINX 3000 family) where a reduced set of configurations (5) and their corresponding test sequences is found to cover all (100%) the Configurable Logic Block faults modelled.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116311446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As VLSI circuits become high-speed and high-density, a crosstalk fault becomes an important problem. In a synchronous sequential circuit, since the crosstalk fault between a data line and a clock line is important, we described an algorithmic test generation technique for the fault. Some simulation results of our method for the ISCAS bench mark circuits are reported.
{"title":"An algorithmic test generation method for crosstalk faults in synchronous sequential circuits","authors":"N. Itazaki, Yasutaka Idomoto, K. Kinoshita","doi":"10.1109/ATS.1997.643909","DOIUrl":"https://doi.org/10.1109/ATS.1997.643909","url":null,"abstract":"As VLSI circuits become high-speed and high-density, a crosstalk fault becomes an important problem. In a synchronous sequential circuit, since the crosstalk fault between a data line and a clock line is important, we described an algorithmic test generation technique for the fault. Some simulation results of our method for the ISCAS bench mark circuits are reported.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115458273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes the testability design features of the R10000 microprocessor. It has specific testability features for debug and manufacturing purposes. Observability registers are implemented to enhance high fault coverage and they partition the chip into three parts to run a fault simulation much faster. Plus a clock control mechanism for AC path analysis and a minimal impact embedded memory test feature are implemented.
{"title":"Testability features of R10000 microprocessor","authors":"J. Mori, B. Mathew, Dave Burns, Y. Mok","doi":"10.1109/ATS.1997.643930","DOIUrl":"https://doi.org/10.1109/ATS.1997.643930","url":null,"abstract":"This paper describes the testability design features of the R10000 microprocessor. It has specific testability features for debug and manufacturing purposes. Observability registers are implemented to enhance high fault coverage and they partition the chip into three parts to run a fault simulation much faster. Plus a clock control mechanism for AC path analysis and a minimal impact embedded memory test feature are implemented.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121838991","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.
{"title":"ATREX: Design for testability system for Mega Gate LSIs","authors":"Michiaki Emori, Junko Kumagai, Koichi Itaya, T. Aikyo, Tomoko Anan, Junichi Niimi","doi":"10.1109/ATS.1997.643947","DOIUrl":"https://doi.org/10.1109/ATS.1997.643947","url":null,"abstract":"We propose a Design for Testability System for Mega Gate LSIs. This system meets various demands of designers, because this system has high flexibility. We show the flexibility by introducing some examples of circuit insertion which is supported by the system.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116893272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we consider the design for testability of multipliers based on the modified Booth Algorithm. We introduce two basic array implementations of the multiplier and present a strategy to design for c-testability. Using the proposed strategy we present two designs. The first design, which requires two primary test inputs, is c-testable under the single stuck fault model (SSF) with 17 test vectors. Also under the cell fault model (CFM) we present a design derived from the second implementation. This design, which requires only one primary test input, is c-testable with 34 test vectors and each of its cells can be tested by exhaustively applying cell input patterns.
{"title":"Design of C-testable multipliers based on the modified Booth Algorithm","authors":"K. Boateng, Hiroshi Takahashi, Y. Takamatsu","doi":"10.1109/ATS.1997.643914","DOIUrl":"https://doi.org/10.1109/ATS.1997.643914","url":null,"abstract":"In this paper, we consider the design for testability of multipliers based on the modified Booth Algorithm. We introduce two basic array implementations of the multiplier and present a strategy to design for c-testability. Using the proposed strategy we present two designs. The first design, which requires two primary test inputs, is c-testable under the single stuck fault model (SSF) with 17 test vectors. Also under the cell fault model (CFM) we present a design derived from the second implementation. This design, which requires only one primary test input, is c-testable with 34 test vectors and each of its cells can be tested by exhaustively applying cell input patterns.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133623229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a new methodology for transistor leakage fault diagnosis using both I/sub DDQ/ and logic information. A method for handling intermediate faulty voltages in fault simulation is proposed. A scheme for generating diagnostic test vectors based on logic information in the presence of intermediate faulty voltages is also proposed. An example is used to demonstrate the new diagnosis methodology.
{"title":"Fault diagnosis for static CMOS circuits","authors":"W. Xiaoqing, H. Tamamoto, K. Saluja, K. Kinoshita","doi":"10.1109/ATS.1997.643971","DOIUrl":"https://doi.org/10.1109/ATS.1997.643971","url":null,"abstract":"This paper presents a new methodology for transistor leakage fault diagnosis using both I/sub DDQ/ and logic information. A method for handling intermediate faulty voltages in fault simulation is proposed. A scheme for generating diagnostic test vectors based on logic information in the presence of intermediate faulty voltages is also proposed. An example is used to demonstrate the new diagnosis methodology.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123314107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.
{"title":"Test generation for stuck-on faults in BDD-based pass-transistor logic SPL","authors":"T. Shinogi, T. Hayashi, K. Taki","doi":"10.1109/ATS.1997.643908","DOIUrl":"https://doi.org/10.1109/ATS.1997.643908","url":null,"abstract":"This paper presents a method of test generation for stuck-on faults in a pass-transistor logic SPL by logic testing. We describe how to create a discrepancy using a pre-computed table for voltage calculation. For solving a table explosion problem we present some techniques for extending the applicable scope of a restricted table in practical size. Then, we propose a simple DFT circuit. The experimental results show the effectiveness.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115764973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Jacomet, Roger Wälti, L. Winzenried, Jaime Perez, M. Gysel
The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low cast and easy to use computer-aided-test environment.
{"title":"ProTest: a low cost rapid prototyping and test system for ASICs and FPGAs","authors":"M. Jacomet, Roger Wälti, L. Winzenried, Jaime Perez, M. Gysel","doi":"10.1109/ATS.1997.643949","DOIUrl":"https://doi.org/10.1109/ATS.1997.643949","url":null,"abstract":"The test bench methodology helps the design engineer to structure the simulation of his circuit. As showed in this paper, the test bench methodology can further be developed in order to efficiently reuse simulation stimuli and response for the real device under test. As FPGAs are very often used to prototype an ASIC design, an easy switch between simulation and real hardware test is necessary to establish a rapid prototyping design and test environment. Our ProTest system closes the gap between the simulation and the test environment with a low cast and easy to use computer-aided-test environment.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"280 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115822466","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An application of new idea of designing circular self-test path (CSTP) for EDAC circuit is given in the paper. The new BIST scheme called in the paper as a condensed circular self-test path (CCSTP=C/sup 2/STP) makes possible to reduce significantly the number of CBIST cells to a smaller value. We focus on the analysis of the state transition graph (STG) as a key to understand the state coverage, fault coverage, and zero aliasing of condensed circular BIST (CBIST) schemes. There are given two examples of C/sup 2/BIST design. Particularly, the simple example of C/sup 2/STP design for 4-bit errors detection and errors correction (EDAC) circuit indicates advantages of such BIST technique. On the basis of this example it is shown that the time and complexity of simulation process for C/sup 2/STP is smaller than those for CSTP configuration and the seek time of a solution giving quasi optimal effectiveness for C/sup 2/STP is considerably shorter.
{"title":"Low cost BIST for EDAC circuits","authors":"D. Badura, A. Hlawiczka","doi":"10.1109/ATS.1997.643991","DOIUrl":"https://doi.org/10.1109/ATS.1997.643991","url":null,"abstract":"An application of new idea of designing circular self-test path (CSTP) for EDAC circuit is given in the paper. The new BIST scheme called in the paper as a condensed circular self-test path (CCSTP=C/sup 2/STP) makes possible to reduce significantly the number of CBIST cells to a smaller value. We focus on the analysis of the state transition graph (STG) as a key to understand the state coverage, fault coverage, and zero aliasing of condensed circular BIST (CBIST) schemes. There are given two examples of C/sup 2/BIST design. Particularly, the simple example of C/sup 2/STP design for 4-bit errors detection and errors correction (EDAC) circuit indicates advantages of such BIST technique. On the basis of this example it is shown that the time and complexity of simulation process for C/sup 2/STP is smaller than those for CSTP configuration and the seek time of a solution giving quasi optimal effectiveness for C/sup 2/STP is considerably shorter.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"130 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116357416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Almost all analog signal processing is being replaced by digital signal processing techniques in today's communication networks, as well as in other applications. This means that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), which serve as the interfaces between the analog and the digital worlds, will together share a growing influence on overall system performance. In this paper, we present a new method, based on wavelet transforms, for measuring ADC errors, namely nonlinearity, gain error, and offset error. Unlike the traditional DNL method, this new method, which we have called NSR, for noise-to-signal ratio estimated in amplitude-scale plane, can be used during circuit design, production testing, and in service testing of ADCs and DACs.
{"title":"Static testing of ADCs using wavelet transforms","authors":"Takahiro J. Yamaguchi","doi":"10.1109/ATS.1997.643957","DOIUrl":"https://doi.org/10.1109/ATS.1997.643957","url":null,"abstract":"Almost all analog signal processing is being replaced by digital signal processing techniques in today's communication networks, as well as in other applications. This means that analog-to-digital converters (ADCs) and digital-to-analog converters (DACs), which serve as the interfaces between the analog and the digital worlds, will together share a growing influence on overall system performance. In this paper, we present a new method, based on wavelet transforms, for measuring ADC errors, namely nonlinearity, gain error, and offset error. Unlike the traditional DNL method, this new method, which we have called NSR, for noise-to-signal ratio estimated in amplitude-scale plane, can be used during circuit design, production testing, and in service testing of ADCs and DACs.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114828273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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