This paper presents an accelerated test points selection method for circuits designed by a full-scan based BIST scheme. In order to speed up the test points selection method based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed method and evaluate its efficiency experimentally using large scale circuits (26 k-420 k gates).
{"title":"Accelerated test points selection method for scan-based BIST","authors":"M. Nakao, K. Hatayama, Isao Higashi","doi":"10.1109/ATS.1997.643983","DOIUrl":"https://doi.org/10.1109/ATS.1997.643983","url":null,"abstract":"This paper presents an accelerated test points selection method for circuits designed by a full-scan based BIST scheme. In order to speed up the test points selection method based on cost minimization, and reflecting random pattern testability, we introduce three techniques, the simultaneous selection of plural test points, the simplified selection of test points by the cost reduction factor, and the reduction of the number of test point candidates. We implement a program based on the proposed method and evaluate its efficiency experimentally using large scale circuits (26 k-420 k gates).","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124284411","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose an approach for locating logical faults in sequential circuits under the condition that all the internal nets are not observable. In this approach, candidates for the error sources are first deduced by an error propagation traceback starting from the failing primary outputs. Then, with the aid of probing, the possible error sources are found. Simulation results for ISCAS'89 benchmark circuits show that a reasonable diagnostic resolution can be achieved by our approach if more than 50% of the internal nets are observable.
{"title":"An approach to diagnose logical faults in partially observable sequential circuits","authors":"K. Yamazaki, Teruhiko Yamada","doi":"10.1109/ATS.1997.643954","DOIUrl":"https://doi.org/10.1109/ATS.1997.643954","url":null,"abstract":"We propose an approach for locating logical faults in sequential circuits under the condition that all the internal nets are not observable. In this approach, candidates for the error sources are first deduced by an error propagation traceback starting from the failing primary outputs. Then, with the aid of probing, the possible error sources are found. Simulation results for ISCAS'89 benchmark circuits show that a reasonable diagnostic resolution can be achieved by our approach if more than 50% of the internal nets are observable.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115402549","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper investigates detection and location for single faults in odd-even sorting networks. In the work, we have found that three tests are enough to locate single link fault and four tests are sufficient to detect single sorting element fault in an odd-even sorting network. For location tests for sorting element faults, the numbers of tests depend on the type of faults occurring at the sorting element. For most types of sorting element faults, the numbers are less than four specific tests. For the other types of faults, we have presented the test generation procedure and binary search procedures to generate the tests. The numbers of location tests are less than (n+log/sub 2/n), where n=log/sub 2/N and N is the number of inputs of the sorting network.
{"title":"Fault diagnosis of odd-even sorting networks","authors":"C. Hu, Chung-Len Lee, Wen Ching Wu, Jwu-E Chen","doi":"10.1109/ATS.1997.643972","DOIUrl":"https://doi.org/10.1109/ATS.1997.643972","url":null,"abstract":"This paper investigates detection and location for single faults in odd-even sorting networks. In the work, we have found that three tests are enough to locate single link fault and four tests are sufficient to detect single sorting element fault in an odd-even sorting network. For location tests for sorting element faults, the numbers of tests depend on the type of faults occurring at the sorting element. For most types of sorting element faults, the numbers are less than four specific tests. For the other types of faults, we have presented the test generation procedure and binary search procedures to generate the tests. The numbers of location tests are less than (n+log/sub 2/n), where n=log/sub 2/N and N is the number of inputs of the sorting network.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127447849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda, Giovanni Squillero
Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process.
{"title":"A genetic algorithm for the computation of initialization sequences for synchronous sequential circuits","authors":"Fulvio Corno, P. Prinetto, M. Rebaudengo, M. Reorda, Giovanni Squillero","doi":"10.1109/ATS.1997.643917","DOIUrl":"https://doi.org/10.1109/ATS.1997.643917","url":null,"abstract":"Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate initialization sequences. This paper follows the latter approach, and presents a new method to the automated generation of an initialization sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and sequence length. Finally, this paper shows how the initialization sequences can be fruitfully exploited by simplifying the ATPG process.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121822113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a new variable ordering algorithm, distributed reordering algorithm that allows more faster solution than existing ones, is presented. Since this method can accomplish fast optimization of BDD in less memory and computation time, the proposed algorithm is more efficient for dynamic variable ordering. Also, the proposed algorithm can achieve more optimized results in combining with other variable ordering method.
{"title":"A variable reordering method for fast optimization of binary decision diagrams","authors":"MoonBae Song, Hoon Chang","doi":"10.1109/ATS.1997.643963","DOIUrl":"https://doi.org/10.1109/ATS.1997.643963","url":null,"abstract":"In this paper, a new variable ordering algorithm, distributed reordering algorithm that allows more faster solution than existing ones, is presented. Since this method can accomplish fast optimization of BDD in less memory and computation time, the proposed algorithm is more efficient for dynamic variable ordering. Also, the proposed algorithm can achieve more optimized results in combining with other variable ordering method.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133945537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we introduce universal fault diagnosis such that when applied to an unprogrammed FPGA, it locates a fault in any faulty programmed FPGA corresponding to the unprogrammed FPGA. If a faulty part in an FPGA can be identified prior to programming it, we can implement a required logic function on the fault-free part by isolating the faulty part. Then, we propose a universal fault diagnosis procedure that locates a faulty CLB in a look-up table FPGA. The complexity of the universal diagnosis procedure for FPGAs with block-sliced loading is independent of its array size, i.e., C-diagnosable.
{"title":"On the complexity of universal fault diagnosis for look-up table FPGAs","authors":"Tomoo Inoue, Satoshi Miyazaki, H. Fujiwara","doi":"10.1109/ATS.1997.643970","DOIUrl":"https://doi.org/10.1109/ATS.1997.643970","url":null,"abstract":"In this paper, we introduce universal fault diagnosis such that when applied to an unprogrammed FPGA, it locates a fault in any faulty programmed FPGA corresponding to the unprogrammed FPGA. If a faulty part in an FPGA can be identified prior to programming it, we can implement a required logic function on the fault-free part by isolating the faulty part. Then, we propose a universal fault diagnosis procedure that locates a faulty CLB in a look-up table FPGA. The complexity of the universal diagnosis procedure for FPGAs with block-sliced loading is independent of its array size, i.e., C-diagnosable.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"40 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121173649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-in/out operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.
{"title":"Test compaction in a parallel access scan environment","authors":"S. Bhatia, P. Varma","doi":"10.1109/ATS.1997.643974","DOIUrl":"https://doi.org/10.1109/ATS.1997.643974","url":null,"abstract":"In this paper test compaction techniques suitable for circuits designed using a novel parallel access scan methodology are proposed. In this methodology, groups of scan elements are addressed in parallel and the scan-in and scan-out operations are performed separately. The compaction techniques presented reduce the number of scan-in/out operations required by skipping scan operations that do not have an affect on fault coverage. The techniques allow the number of test cycles required to be reduced by up to 45% of that achieved using regular dynamic compaction techniques alone, and by up to 98% over that achieved using a single serial scan chain methodology. In addition, the techniques are suitable for both synchronous and asynchronous circuits.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"122 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122749702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An automatic electron beam (EB) fault tracing system is described which enables us to trace faults automatically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit independently of circuit functions. Only VLSI CAD layout data is required.
{"title":"Automatic EB fault tracing system by successive circuit extraction from VLSI CAD layout data","authors":"K. Miura, Kohei Nakata, K. Nakamae, H. Fujioka","doi":"10.1109/ATS.1997.643953","DOIUrl":"https://doi.org/10.1109/ATS.1997.643953","url":null,"abstract":"An automatic electron beam (EB) fault tracing system is described which enables us to trace faults automatically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit independently of circuit functions. Only VLSI CAD layout data is required.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131640138","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida
This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and complicated. Various test methods, such as test bus, internal and boundary scan, and BIST are selectively employed according to the target devices. The structures of those DFT methods being used for actual cell-based ASIC designs are described with their overhead in sample chips. How they are effectively integrated and automated is also explained.
{"title":"Integrated and automated design-for-testability implementation for cell-based ICs","authors":"Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida","doi":"10.1109/ATS.1997.643946","DOIUrl":"https://doi.org/10.1109/ATS.1997.643946","url":null,"abstract":"This paper presents several design-for-testability (DFT) techniques for cell-based ICs. In the design of cell-based ICs, embedded cores are often used along with the user defined random logic. The existence of embedded cores makes chip level testing more difficult and complicated. Various test methods, such as test bus, internal and boundary scan, and BIST are selectively employed according to the target devices. The structures of those DFT methods being used for actual cell-based ASIC designs are described with their overhead in sample chips. How they are effectively integrated and automated is also explained.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130813679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hiroshi Takahashi, K. Boateng, Y. Takamatsu, Toshiyuki Matsunaga
In this paper, we propose an algorithmic method for generating a test for marginal delays and gate delay faults, called an MD test. The time at which the MD test activates the latest transition at the primary output changes linearly with the size of the target delay. (1) The MD tests determine at a given clock rate (observation time) whether a circuit tender test is marginal chip or not. (2) The MD tests determine the maximum circuit clock speeds. (3) The MD test detects the target gate delay fault regardless of the size of the fault by comparing the latest transition time at the primary output of the fault-free circuit and that of the faulty circuit. In order to determine the detectable size of gate delay faults the proposed method introduces a new extended timed calculus which calculates both the latest transition time at the line in the fault-free circuit and the transition time at the same line affected by a gate delay fault of maximum fault size. We also demonstrate experimental results for gate delay faults on ISCAS benchmark circuits to show the performance of our method.
{"title":"A method of generating tests for marginal delays and delay faults in combinational circuits","authors":"Hiroshi Takahashi, K. Boateng, Y. Takamatsu, Toshiyuki Matsunaga","doi":"10.1109/ATS.1997.643977","DOIUrl":"https://doi.org/10.1109/ATS.1997.643977","url":null,"abstract":"In this paper, we propose an algorithmic method for generating a test for marginal delays and gate delay faults, called an MD test. The time at which the MD test activates the latest transition at the primary output changes linearly with the size of the target delay. (1) The MD tests determine at a given clock rate (observation time) whether a circuit tender test is marginal chip or not. (2) The MD tests determine the maximum circuit clock speeds. (3) The MD test detects the target gate delay fault regardless of the size of the fault by comparing the latest transition time at the primary output of the fault-free circuit and that of the faulty circuit. In order to determine the detectable size of gate delay faults the proposed method introduces a new extended timed calculus which calculates both the latest transition time at the line in the fault-free circuit and the transition time at the same line affected by a gate delay fault of maximum fault size. We also demonstrate experimental results for gate delay faults on ISCAS benchmark circuits to show the performance of our method.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124133156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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