The areas of analog circuit fault simulation and test generation have not witnessed the same degree of success as their digital counterparts. This is due mainly to the complexity of analog behavior and the lack of a fault mode. We present a new functional fault modeling technique called the perturbation fault model. The perturbation fault model is based on an estimation of the distance between the responses of the faulty and fault-free circuit and their distributions. The model allows fault abstraction of physical defects through structural fault modeling and perturbation estimation. The fault simulation technique uses a linear estimation of the faulty and fault-free output circuits. Techniques for fault observation and propagation are presented in order to build a hierarchical analog fault simulator.
{"title":"A perturbation based fault modeling and simulation for mixed-signal circuits","authors":"Naim Ben-Hamida, K. Saab, D. Marche, B. Kaminska","doi":"10.1109/ATS.1997.643956","DOIUrl":"https://doi.org/10.1109/ATS.1997.643956","url":null,"abstract":"The areas of analog circuit fault simulation and test generation have not witnessed the same degree of success as their digital counterparts. This is due mainly to the complexity of analog behavior and the lack of a fault mode. We present a new functional fault modeling technique called the perturbation fault model. The perturbation fault model is based on an estimation of the distance between the responses of the faulty and fault-free circuit and their distributions. The model allows fault abstraction of physical defects through structural fault modeling and perturbation estimation. The fault simulation technique uses a linear estimation of the faulty and fault-free output circuits. Techniques for fault observation and propagation are presented in order to build a hierarchical analog fault simulator.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115227965","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Correct operation of logic circuits requires not only the functional correctness, but also the correctness of temporal behavior. This paper deals with the problem of delay testability of two-level circuits through adding extra inputs. A design of delay-verifiable combinational logic by adding extra inputs is proposed, and a synthesis procedure is given. Experimental results show that the hardware overhead is about 1/3 of that of the methods proposed previously (1987, 1991), which aim at robust testable or VNR testable circuits. In fact, it is good enough to guarantee delay verifiability to satisfy the requirement of temporal correctness.
{"title":"Design of delay-verifiable combinational logic by adding extra inputs","authors":"X. Yu, Y. Min","doi":"10.1109/ATS.1997.643979","DOIUrl":"https://doi.org/10.1109/ATS.1997.643979","url":null,"abstract":"Correct operation of logic circuits requires not only the functional correctness, but also the correctness of temporal behavior. This paper deals with the problem of delay testability of two-level circuits through adding extra inputs. A design of delay-verifiable combinational logic by adding extra inputs is proposed, and a synthesis procedure is given. Experimental results show that the hardware overhead is about 1/3 of that of the methods proposed previously (1987, 1991), which aim at robust testable or VNR testable circuits. In fact, it is good enough to guarantee delay verifiability to satisfy the requirement of temporal correctness.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114389282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The industry has accepted I/sub DDQ/ testing to detect CMOS IC defects. While I/sub DDT/ testing needs more research to be applicable in practice. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage. This paper presents a formal procedure to identify I/sub DDT/ testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by I/sub DDQ/ or other test methods, which shows the significance of I/sub DDT/ testing.
{"title":"I/sub DDT/ testing","authors":"Yinghua Min, Z. Zhao, Zhongcheng Li","doi":"10.1109/ATS.1997.643986","DOIUrl":"https://doi.org/10.1109/ATS.1997.643986","url":null,"abstract":"The industry has accepted I/sub DDQ/ testing to detect CMOS IC defects. While I/sub DDT/ testing needs more research to be applicable in practice. However, it is noticed that observing the average transient current can lead to improvements in real defect coverage. This paper presents a formal procedure to identify I/sub DDT/ testable faults, and to generate input vector pairs to detect the faults based on Boolean process. It is interesting to note that those faults may not be detected by I/sub DDQ/ or other test methods, which shows the significance of I/sub DDT/ testing.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124679325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Ozaki, Hidenori Sekiguchi, S. Wakana, Y. Goto, Yasutoshi Umehara, J. Matsumoto
An e-beam tester is widely used for the internal analysis of LSI circuits. However, its low waveform acquisition speed is a significant drawback for LSI circuits featuring high integration and high speed. We have introduced a novel optical probing system applicable to quarter-/spl mu/m VLSI circuits. Based on an electro-optic sampling technique, this probing system achieved a sub-/spl mu/m spatial resolution by utilizing the scanning force microscope technique. This system can measure internal signal waveforms of VLSI circuits much faster than e-beam testers, and can measure the DC voltage level, which is not possible with e-beam testers.
电子束测试仪广泛用于大规模集成电路的内部分析。然而，对于高集成度、高速度的大规模集成电路来说，其波形采集速度低是一个明显的缺点。介绍了一种适用于四分之一/spl μ m VLSI电路的新型光学探测系统。该探测系统基于电光采样技术，利用扫描力显微镜技术实现了亚/spl μ m /m的空间分辨率。该系统能够以比电子束测试仪更快的速度测量VLSI电路的内部信号波形，并且能够测量直流电压电平，这是电子束测试仪无法实现的。
{"title":"Novel optical probing system for quarter-/spl mu/m VLSI circuits","authors":"K. Ozaki, Hidenori Sekiguchi, S. Wakana, Y. Goto, Yasutoshi Umehara, J. Matsumoto","doi":"10.1109/ATS.1997.643960","DOIUrl":"https://doi.org/10.1109/ATS.1997.643960","url":null,"abstract":"An e-beam tester is widely used for the internal analysis of LSI circuits. However, its low waveform acquisition speed is a significant drawback for LSI circuits featuring high integration and high speed. We have introduced a novel optical probing system applicable to quarter-/spl mu/m VLSI circuits. Based on an electro-optic sampling technique, this probing system achieved a sub-/spl mu/m spatial resolution by utilizing the scanning force microscope technique. This system can measure internal signal waveforms of VLSI circuits much faster than e-beam testers, and can measure the DC voltage level, which is not possible with e-beam testers.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125347115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Temperature can be used as a test observable: some failures when activated produce an increase in local power dissipation, changing the surface thermal map of the IC, being detectable with built-in thermal sensors. In this work, both the feasibility of this testing technique and the generation of the specific test pattern are discussed.
{"title":"Analysis of the feasibility of dynamic thermal testing in digital circuits","authors":"J. Altet, A. Rubio, H. Tamamoto","doi":"10.1109/ATS.1997.643951","DOIUrl":"https://doi.org/10.1109/ATS.1997.643951","url":null,"abstract":"Temperature can be used as a test observable: some failures when activated produce an increase in local power dissipation, changing the surface thermal map of the IC, being detectable with built-in thermal sensors. In this work, both the feasibility of this testing technique and the generation of the specific test pattern are discussed.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126596867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Wangning Long, Shiyuan Yang, Zhongcheng Li, Y. Min
A memory efficient test pattern generator for path delay faults, DTPG, is presented in this paper, which uses the efficient path identifier to represent a path. A compact bit table, path information table, is proposed to store test information efficiently. Furthermore, DTPG is capable of identifying functional sensitizable paths, which account for large percent of paths in many circuits. The experimental results show that DTPG is memory efficient. It generates tests for C3540 with 57 million paths and preserves the testability information for all paths. Experimental results show the influence of stepwise mandatory sensitization, multiple backtrace, and backtracking limits on the cpu time consumed by delay test generation process.
{"title":"Memory efficient ATPG for path delay faults","authors":"Wangning Long, Shiyuan Yang, Zhongcheng Li, Y. Min","doi":"10.1109/ATS.1997.643978","DOIUrl":"https://doi.org/10.1109/ATS.1997.643978","url":null,"abstract":"A memory efficient test pattern generator for path delay faults, DTPG, is presented in this paper, which uses the efficient path identifier to represent a path. A compact bit table, path information table, is proposed to store test information efficiently. Furthermore, DTPG is capable of identifying functional sensitizable paths, which account for large percent of paths in many circuits. The experimental results show that DTPG is memory efficient. It generates tests for C3540 with 57 million paths and preserves the testability information for all paths. Experimental results show the influence of stepwise mandatory sensitization, multiple backtrace, and backtracking limits on the cpu time consumed by delay test generation process.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122188013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel guided-probe diagnostic method for macro cells has been developed. Since macro cells have no netlist corresponding to layout, CAD-navigation data and the logic-simulation netlist are derived from the macro-cell layout by extracting a transistor-level or leaf-cell-level netlist. A memory-macro cell, in which logic simulation was very difficult because of the cell's internal analog behavior has been converted into logically equivalent circuits for logic simulation. Here, analog-behavior leaf cells, such as sense amplifiers and pull-up transistors, were replaced with the corresponding logic-behavior models. The proposed method has been successfully applied to actual macro-cell-designed LSI data, and it has been verified that the logic models give a good timing resolution in the logic simulation. Using the proposed method, all kinds of macro-cell-designed LSIs will be able to be diagnosed, without the need for a "golden" device by an electron-beam guided probe.
{"title":"Guided-probe diagnosis of macro-cell-designed LSI circuits","authors":"N. Kuji","doi":"10.1109/ATS.1997.643955","DOIUrl":"https://doi.org/10.1109/ATS.1997.643955","url":null,"abstract":"A novel guided-probe diagnostic method for macro cells has been developed. Since macro cells have no netlist corresponding to layout, CAD-navigation data and the logic-simulation netlist are derived from the macro-cell layout by extracting a transistor-level or leaf-cell-level netlist. A memory-macro cell, in which logic simulation was very difficult because of the cell's internal analog behavior has been converted into logically equivalent circuits for logic simulation. Here, analog-behavior leaf cells, such as sense amplifiers and pull-up transistors, were replaced with the corresponding logic-behavior models. The proposed method has been successfully applied to actual macro-cell-designed LSI data, and it has been verified that the logic models give a good timing resolution in the logic simulation. Using the proposed method, all kinds of macro-cell-designed LSIs will be able to be diagnosed, without the need for a \"golden\" device by an electron-beam guided probe.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"1634 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We develop the basic definitions and procedures for a test generation concept referred to as templates that magnifies the effectiveness of test generation by taking advantage of the fact that many faults have "similar" test sequences. Once a template is generated, several test sequences to detect different faults are derived from it at a reduced complexity compared to the complexity of test generation.
{"title":"TEMPLATES: a test generation procedure for synchronous sequential circuits","authors":"I. Pomeranz, S. Reddy","doi":"10.1109/ATS.1997.643923","DOIUrl":"https://doi.org/10.1109/ATS.1997.643923","url":null,"abstract":"We develop the basic definitions and procedures for a test generation concept referred to as templates that magnifies the effectiveness of test generation by taking advantage of the fact that many faults have \"similar\" test sequences. Once a template is generated, several test sequences to detect different faults are derived from it at a reduced complexity compared to the complexity of test generation.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128997600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Test generation algorithms are being developed with the continuous creation of incredibly sophisticated computer systems. Although dozens of algorithms have been proposed to cope with these issues, there still remains much to be desired in solving such problems as to determine: which of the existing test generation algorithms could be the most efficient for some particular sequential circuits because different algorithms will be better in different circuits; which testability parameters will have the most or the least influences on test generations so that the designers of circuits can have a global understanding during the designing stage. Testability predicting methodology for sequential circuits using a neural network model has been presented, which a user usually needs for analyzing his/her own circuits and selecting the most suitable test generation algorithm from all the possible algorithms they have, and which a designer for VLSI circuits always needs for making his/her circuits being designed more testable.
{"title":"Testability prediction for sequential circuits using neural networks","authors":"Shiyi Xu, Peter Waignjo, Percy G. Dias, Baile Shi","doi":"10.1109/ATS.1997.643916","DOIUrl":"https://doi.org/10.1109/ATS.1997.643916","url":null,"abstract":"Test generation algorithms are being developed with the continuous creation of incredibly sophisticated computer systems. Although dozens of algorithms have been proposed to cope with these issues, there still remains much to be desired in solving such problems as to determine: which of the existing test generation algorithms could be the most efficient for some particular sequential circuits because different algorithms will be better in different circuits; which testability parameters will have the most or the least influences on test generations so that the designers of circuits can have a global understanding during the designing stage. Testability predicting methodology for sequential circuits using a neural network model has been presented, which a user usually needs for analyzing his/her own circuits and selecting the most suitable test generation algorithm from all the possible algorithms they have, and which a designer for VLSI circuits always needs for making his/her circuits being designed more testable.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115779183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Most multi-port memory BIST algorithms treat the memory as multiple individual single-port memories and test each independently using the algorithms developed for single-port RAMs. A major problem with this approach is the lack of coverage for multi-port specific defects, such as inter-port interferences due to shorts across ports. This paper proposes a novel BIST algorithm for multi-port RAMs that detects both The conventional single-port faults as well as inter-port shorts. The proposed algorithm performs a conventional single-port test such as MARCH (1991) or SMARCH (1990) on one port of the memory and simultaneously performs an inter-port test on all other ports. The algorithm does not impose any extra test time and requires the addition of only a few gates to a conventional single-port BIST controller, independently of the size of the memory.
{"title":"Built-in self-test for multi-port RAMs","authors":"Yuejian Wu, Sanjay Gupta","doi":"10.1109/ATS.1997.643989","DOIUrl":"https://doi.org/10.1109/ATS.1997.643989","url":null,"abstract":"Most multi-port memory BIST algorithms treat the memory as multiple individual single-port memories and test each independently using the algorithms developed for single-port RAMs. A major problem with this approach is the lack of coverage for multi-port specific defects, such as inter-port interferences due to shorts across ports. This paper proposes a novel BIST algorithm for multi-port RAMs that detects both The conventional single-port faults as well as inter-port shorts. The proposed algorithm performs a conventional single-port test such as MARCH (1991) or SMARCH (1990) on one port of the memory and simultaneously performs an inter-port test on all other ports. The algorithm does not impose any extra test time and requires the addition of only a few gates to a conventional single-port BIST controller, independently of the size of the memory.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114296061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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