Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268808
L. Stok, J. Koehl
The tutorial presents an introduction into “DfY/DfM Design for Yield and Manufacturability” covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment.
{"title":"Structured CAD: technology closure for modern ASICs [Tutorial]","authors":"L. Stok, J. Koehl","doi":"10.1109/DATE.2004.1268808","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268808","url":null,"abstract":"The tutorial presents an introduction into “DfY/DfM Design for Yield and Manufacturability” covering basics of analogue circuit simulation, statistical analysis and design centering from both methodology/implementation as well as from the industrial application side. The tutorial presents the following six topics: introduction into DfY/DfM, basics of analogue circuit simulation, methodology for statistical circuit analysis and yield optimisation, software solutions and design flow integration, design flow specific industrial applications and use cases closing with an outlook on actual and future challenges in the DfY/DfM area regarding a global design environment.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129982149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268805
L. Lavagno, S. Moore
This tutorial addresses state-of-the-art methods used to verify properties of sequential digital systems. The focus is on providing an overview of the main technologies and their applicability to complex designs. We cover the core algorithms involved in model checking, symbolic simulation and theorem proving methods, their application for specific aspects of formal verification and their deployment in verification software currently available both from industry and from academia.
{"title":"Breaking the synchronous barrier for systems-on-chip communication and synchronisation [Tutorial]","authors":"L. Lavagno, S. Moore","doi":"10.1109/DATE.2004.1268805","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268805","url":null,"abstract":"This tutorial addresses state-of-the-art methods used to verify properties of sequential digital systems. The focus is on providing an overview of the main technologies and their applicability to complex designs. We cover the core algorithms involved in model checking, symbolic simulation and theorem proving methods, their application for specific aspects of formal verification and their deployment in verification software currently available both from industry and from academia.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122486665","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268816
M. Poncino, P. Sithambaram, R. Zafalon
The purpose of this master class is to present to the Digital System Design community a set of effective techniques for solving large scale combinatorial optimisation problems related to hardware and software co-design. In general, these problems are faced by modelling and solving them via Integer Programming (IP) techniques. Recently, Constraint Programming (CP) has emerged as a powerful programming paradigm that can be used in alternative or in conjunction with Integer Programming. Constraint Programming integrated concepts from different areas such as Artificial Intelligence, Mathematical Programming, Networks and Computational Logic. Its main strength concerns its efficiency, simplicity and flexibility. In particular flexibility is fundamental for changing the problem model adding or removing constraints without changing the solver. In the master class we 1) focus on finite domain Constraint Programming and its integration with Integer Programming, 2) describe system level design applications modelled via Constraint Programming 3) present ILOG, a leading edge, commercial tool embedding both Linear and Constraint Programming solvers. The objective of this master class is that of describing how emerging design methodologies for RTL power optimisation have found their way into commercial EDA tools, and how such tools have been successfully exploited in industry-strength designs. The course is organised into three main sections. The first one provides a review of the most effective RTL power optimisation techniques currently available. The second part is dedicated to the presentation and demonstration of innovative commercial EDA tools that implement the surveyed estimation and optimisation techniques. The third part reports on industrial experience on the usage of the methodologies and tools introduced in the previous sections. Intended audience for this class includes designers and design team managers from semiconductor companies and system houses, R&D engineers from EDA companies, and academic researchers and Ph.D. students in the field of IC/system design.
{"title":"RTL power optimisation: concepts, tools and design experiences [Tutorial]","authors":"M. Poncino, P. Sithambaram, R. Zafalon","doi":"10.1109/DATE.2004.1268816","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268816","url":null,"abstract":"The purpose of this master class is to present to the Digital System Design community a set of effective techniques for solving large scale combinatorial optimisation problems related to hardware and software co-design. In general, these problems are faced by modelling and solving them via Integer Programming (IP) techniques. Recently, Constraint Programming (CP) has emerged as a powerful programming paradigm that can be used in alternative or in conjunction with Integer Programming. Constraint Programming integrated concepts from different areas such as Artificial Intelligence, Mathematical Programming, Networks and Computational Logic. Its main strength concerns its efficiency, simplicity and flexibility. In particular flexibility is fundamental for changing the problem model adding or removing constraints without changing the solver. In the master class we 1) focus on finite domain Constraint Programming and its integration with Integer Programming, 2) describe system level design applications modelled via Constraint Programming 3) present ILOG, a leading edge, commercial tool embedding both Linear and Constraint Programming solvers. The objective of this master class is that of describing how emerging design methodologies for RTL power optimisation have found their way into commercial EDA tools, and how such tools have been successfully exploited in industry-strength designs. The course is organised into three main sections. The first one provides a review of the most effective RTL power optimisation techniques currently available. The second part is dedicated to the presentation and demonstration of innovative commercial EDA tools that implement the surveyed estimation and optimisation techniques. The third part reports on industrial experience on the usage of the methodologies and tools introduced in the previous sections. Intended audience for this class includes designers and design team managers from semiconductor companies and system houses, R&D engineers from EDA companies, and academic researchers and Ph.D. students in the field of IC/system design.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114567427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268889
Xiaoling Huang, H. Mantooth
This paper presents a new approach for identifying nonlinear dynamic behaviour in analogue circuits. The approach facilitates the creation of models that more accurately reflect the dynamic behaviour of a circuit. It has been used in a fully automated, behavioural modelling tool, Ascend, that starts from the netlist description of the circuit and generates differential algebraic equation (DAE) based behavioural models. The underlying modelling approach is overviewed to provide a context for this research. Some demonstrative test results illustrate the effectiveness of the new method.
{"title":"Identification and modelling of nonlinear dynamic behaviour in analogue circuits","authors":"Xiaoling Huang, H. Mantooth","doi":"10.1109/DATE.2004.1268889","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268889","url":null,"abstract":"This paper presents a new approach for identifying nonlinear dynamic behaviour in analogue circuits. The approach facilitates the creation of models that more accurately reflect the dynamic behaviour of a circuit. It has been used in a fully automated, behavioural modelling tool, Ascend, that starts from the netlist description of the circuit and generates differential algebraic equation (DAE) based behavioural models. The underlying modelling approach is overviewed to provide a context for this research. Some demonstrative test results illustrate the effectiveness of the new method.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131316676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-03-08DOI: 10.1109/DATE.2004.1268815
M. Milano, K. Kuchkinski, J. Puget
The purpose of this master class is to present to the Digital System Design community a set of effective techniques for solving large scale combinatorial optimisation problems related to hardware and software co-design. In general, these problems are faced by modelling and solving them via Integer Programming (IP) techniques. Recently, Constraint Programming (CP) has emerged as a powerful programming paradigm that can be used in alternative or in conjunction with Integer Programming. Constraint Programming integrated concepts from different areas such as Artificial Intelligence, Mathematical Programming, Networks and Computational Logic. Its main strength concerns its efficiency, simplicity and flexibility. In particular flexibility is fundamental for changing the problem model adding or removing constraints without changing the solver. In the master class we 1) focus on finite domain Constraint Programming and its integration with Integer Programming, 2) describe system level design applications modelled via Constraint Programming 3) present ILOG, a leading edge, commercial tool embedding both Linear and Constraint Programming solvers. The objective of this master class is that of describing how emerging design methodologies for RTL power optimisation have found their way into commercial EDA tools, and how such tools have been successfully exploited in industry-strength designs. The course is organised into three main sections. The first one provides a review of the most effective RTL power optimisation techniques currently available. The second part is dedicated to the presentation and demonstration of innovative commercial EDA tools that implement the surveyed estimation and optimisation techniques. The third part reports on industrial experience on the usage of the methodologies and tools introduced in the previous sections. Intended audience for this class includes designers and design team managers from semiconductor companies and system houses, R&D engineers from EDA companies, and academic researchers and Ph.D. students in the field of IC/system design.
{"title":"Constraint and integer programming techniques and tools for digital system design [Tutorial]","authors":"M. Milano, K. Kuchkinski, J. Puget","doi":"10.1109/DATE.2004.1268815","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268815","url":null,"abstract":"The purpose of this master class is to present to the Digital System Design community a set of effective techniques for solving large scale combinatorial optimisation problems related to hardware and software co-design. In general, these problems are faced by modelling and solving them via Integer Programming (IP) techniques. Recently, Constraint Programming (CP) has emerged as a powerful programming paradigm that can be used in alternative or in conjunction with Integer Programming. Constraint Programming integrated concepts from different areas such as Artificial Intelligence, Mathematical Programming, Networks and Computational Logic. Its main strength concerns its efficiency, simplicity and flexibility. In particular flexibility is fundamental for changing the problem model adding or removing constraints without changing the solver. In the master class we 1) focus on finite domain Constraint Programming and its integration with Integer Programming, 2) describe system level design applications modelled via Constraint Programming 3) present ILOG, a leading edge, commercial tool embedding both Linear and Constraint Programming solvers. The objective of this master class is that of describing how emerging design methodologies for RTL power optimisation have found their way into commercial EDA tools, and how such tools have been successfully exploited in industry-strength designs. The course is organised into three main sections. The first one provides a review of the most effective RTL power optimisation techniques currently available. The second part is dedicated to the presentation and demonstration of innovative commercial EDA tools that implement the surveyed estimation and optimisation techniques. The third part reports on industrial experience on the usage of the methodologies and tools introduced in the previous sections. Intended audience for this class includes designers and design team managers from semiconductor companies and system houses, R&D engineers from EDA companies, and academic researchers and Ph.D. students in the field of IC/system design.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-03-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128487724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269034
Jennifer Dworak, Brad Cobb, James Wingfield, M. R. Mercer
Dynamic defects are less likely to be fortuitously detected than static defects because they have more stringent detection requirements. We show that (in addition to more site observations) balanced excitation is essential for detection of these defects, and we present a metric for estimating this degree of balance. We also show that excitation balance correlates with the parameter /spl tau/ in the MPG-D defective part level model.
{"title":"Balanced excitation and its effect on the fortuitous detection of dynamic defects","authors":"Jennifer Dworak, Brad Cobb, James Wingfield, M. R. Mercer","doi":"10.1109/DATE.2004.1269034","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269034","url":null,"abstract":"Dynamic defects are less likely to be fortuitously detected than static defects because they have more stringent detection requirements. We show that (in addition to more site observations) balanced excitation is essential for detection of these defects, and we present a metric for estimating this degree of balance. We also show that excitation balance correlates with the parameter /spl tau/ in the MPG-D defective part level model.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115645849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1268952
J. Lapalme, E. Aboulhamid, G. Nicolescu, L. Charest, F. Boyer, J. David, G. Bois
Nowadays, the use of system level description languages is mandatory for the efficient design of complex systems. These description languages are exemplified by SystemC and SystemVerilog. In this paper, we propose a new .NET framework based system level modeling and simulation environment called Esys.NET (embedded systems design with .NET). It allows (1) cooperation - by enabling Web-based design and multi-language features, (2) easy systems specification task - by enabling integration of software components running application and operating systems and by alleviating memory management, (3) link to automatic refinement tools - by enabling translation of specification models into a standard intermediate format and annotation of specification models, and (4) comparative performances with existing environments.
{"title":".NET framework - a solution for the next generation tools for system-level modeling and simulation","authors":"J. Lapalme, E. Aboulhamid, G. Nicolescu, L. Charest, F. Boyer, J. David, G. Bois","doi":"10.1109/DATE.2004.1268952","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268952","url":null,"abstract":"Nowadays, the use of system level description languages is mandatory for the efficient design of complex systems. These description languages are exemplified by SystemC and SystemVerilog. In this paper, we propose a new .NET framework based system level modeling and simulation environment called Esys.NET (embedded systems design with .NET). It allows (1) cooperation - by enabling Web-based design and multi-language features, (2) easy systems specification task - by enabling integration of software components running application and operating systems and by alleviating memory management, (3) link to automatic refinement tools - by enabling translation of specification models into a standard intermediate format and annotation of specification models, and (4) comparative performances with existing environments.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"157 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123099052","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269212
M. Cocco, J. Dielissen, M. Heijligers, A. Hekstra, J. Huisken
Low density parity check (LDPC) codes offer excellent error correcting performance. However, current implementations are not capable of achieving the performance required by next generation storage and telecom applications. Extrapolation of many of those designs is not possible because of routing congestions. This article proposes a new architecture, based on a redefinition of a lesser-known LDPC decoding algorithm. As random LDPC codes are the most powerful, we abstain from making simplifying assumptions about the LDPC code which could ease the routing problem. We avoid the routing congestion problem by going for multiple independent sequential decoding machines, each decoding separate received codewords. In this serial approach the required amount of memory must be multiplied by the large number of machines. Our key contribution is a check node centric reformulation of the algorithm which gives huge memory reduction and which thus makes the serial approach possible.
{"title":"A scalable architecture for LDPC decoding","authors":"M. Cocco, J. Dielissen, M. Heijligers, A. Hekstra, J. Huisken","doi":"10.1109/DATE.2004.1269212","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269212","url":null,"abstract":"Low density parity check (LDPC) codes offer excellent error correcting performance. However, current implementations are not capable of achieving the performance required by next generation storage and telecom applications. Extrapolation of many of those designs is not possible because of routing congestions. This article proposes a new architecture, based on a redefinition of a lesser-known LDPC decoding algorithm. As random LDPC codes are the most powerful, we abstain from making simplifying assumptions about the LDPC code which could ease the routing problem. We avoid the routing congestion problem by going for multiple independent sequential decoding machines, each decoding separate received codewords. In this serial approach the required amount of memory must be multiplied by the large number of machines. Our key contribution is a check node centric reformulation of the algorithm which gives huge memory reduction and which thus makes the serial approach possible.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127075732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1268897
C. Kretzschmar, A. Nieuwland, D. Müller
Encoding techniques which minimize the self- or coupling activity of buses are often proposed to reduce power dissipation on system buses. In this paper, we investigate the efficiency of several coding schemes for on-chip buses with respect to overall power dissipation. The power of the codec systems was estimated by power simulations with the lay-outs and related to the savings on the bus. We derived an expression for the energy efficiency of the codecs as a function of bus length (capacitive load). Despite the fact that adaptive schemes could obtain up to 40% savings, the bus lengths required to reduce the overall power consumption are not realistic for on-chip buses.
{"title":"Why transition coding for power minimization of on-chip buses does not work","authors":"C. Kretzschmar, A. Nieuwland, D. Müller","doi":"10.1109/DATE.2004.1268897","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268897","url":null,"abstract":"Encoding techniques which minimize the self- or coupling activity of buses are often proposed to reduce power dissipation on system buses. In this paper, we investigate the efficiency of several coding schemes for on-chip buses with respect to overall power dissipation. The power of the codec systems was estimated by power simulations with the lay-outs and related to the savings on the bus. We derived an expression for the energy efficiency of the codecs as a function of bus length (capacitive load). Despite the fact that adaptive schemes could obtain up to 40% savings, the bus lengths required to reduce the overall power consumption are not realistic for on-chip buses.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127536710","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1268953
Pablo Viana, E. Barros, S. Rigo, R. Azevedo, G. Araújo
This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to capture the processor description as well as the memory subsystem configuration, this environment offers support for system-level specification, intended for platform-based design. As a case study, it is presented the memory architecture exploration for a simple image processing application, yet a more robust environment evaluation is performed through the execution of some real-world benchmarks.
{"title":"Modeling and simulating memory hierarchies in a platform-based design methodology","authors":"Pablo Viana, E. Barros, S. Rigo, R. Azevedo, G. Araújo","doi":"10.1109/DATE.2004.1268953","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268953","url":null,"abstract":"This paper presents an environment based on SystemC for architecture specification of programmable systems. Making use of the new architecture description language ArchC, able to capture the processor description as well as the memory subsystem configuration, this environment offers support for system-level specification, intended for platform-based design. As a case study, it is presented the memory architecture exploration for a simple image processing application, yet a more robust environment evaluation is performed through the execution of some real-world benchmarks.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124967294","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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