Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269229
F. Berens, G. Kreiselmaier, N. Wehn
Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In third-generation (3G) wireless systems channel coding techniques must serve both voice and data users whose requirements considerably vary. Thus the third generation partnership project (3GPP) standard offers two coding techniques, convolutional-coding for voice and turbo-coding for data services. In this paper we present a combined channel decoding architecture for 3G terminal applications. It outperforms a solution based on two separate decoders due to an efficient reuse of computational hardware and memory resources for both decoders. Moreover it supports blind transport format detection. Special emphasis is put on low energy consumption.
{"title":"Channel decoder architecture for 3G mobile wireless terminals","authors":"F. Berens, G. Kreiselmaier, N. Wehn","doi":"10.1109/DATE.2004.1269229","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269229","url":null,"abstract":"Channel coding is a key element of any digital wireless communication system since it minimizes the effects of noise and interference on the transmitted signal. In third-generation (3G) wireless systems channel coding techniques must serve both voice and data users whose requirements considerably vary. Thus the third generation partnership project (3GPP) standard offers two coding techniques, convolutional-coding for voice and turbo-coding for data services. In this paper we present a combined channel decoding architecture for 3G terminal applications. It outperforms a solution based on two separate decoders due to an efficient reuse of computational hardware and memory resources for both decoders. Moreover it supports blind transport format detection. Special emphasis is put on low energy consumption.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125639263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269100
M. Ziegler, M. Stan
We consider sparsity, fanout, and radix as three dimensions in the design space of regular parallel prefix adders and present a unified formalism to describe such structures.
{"title":"A unified design space for regular parallel prefix adders","authors":"M. Ziegler, M. Stan","doi":"10.1109/DATE.2004.1269100","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269100","url":null,"abstract":"We consider sparsity, fanout, and radix as three dimensions in the design space of regular parallel prefix adders and present a unified formalism to describe such structures.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115818879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1268887
T. Kiely, G. Gielen
This paper describes the application of least-squares support vector machine (LS-SVM) training to analog circuit performance modeling as needed for accelerated or hierarchical analog circuit synthesis. The training is a type of regression, where a function of a special form is fit to experimental performance data derived from analog circuit simulations. The method is contrasted with a feasibility model approach based on the more traditional use of SVMs, namely classification. A design of experiments (DOE) strategy is reviewed which forms the basis of an efficient simulation sampling scheme. The results of our functional regression are then compared to two other DOE-based fitting schemes: a simple linear least-squares regression and a regression using posynomial models. The LS-SVM fitting has advantages over these approaches in terms of accuracy of fit to measured data, prediction of intermediate data points and reduction of free model tuning parameters.
{"title":"Performance modeling of analog integrated circuits using least-squares support vector machines","authors":"T. Kiely, G. Gielen","doi":"10.1109/DATE.2004.1268887","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268887","url":null,"abstract":"This paper describes the application of least-squares support vector machine (LS-SVM) training to analog circuit performance modeling as needed for accelerated or hierarchical analog circuit synthesis. The training is a type of regression, where a function of a special form is fit to experimental performance data derived from analog circuit simulations. The method is contrasted with a feasibility model approach based on the more traditional use of SVMs, namely classification. A design of experiments (DOE) strategy is reviewed which forms the basis of an efficient simulation sampling scheme. The results of our functional regression are then compared to two other DOE-based fitting schemes: a simple linear least-squares regression and a regression using posynomial models. The LS-SVM fitting has advantages over these approaches in terms of accuracy of fit to measured data, prediction of intermediate data points and reduction of free model tuning parameters.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127995206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1268975
A. Glebov, S. Gavrilov, V. Zolotov, C. Oh, R. Panda, M. Becer
High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, producing the worst-case noise. However, due to logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Some techniques for computing logic correlations have been designed targeting static CMOS circuits. However high performance microprocessors commonly use domino logic for their ALU. The domino circuits have lower noise margins than static CMOS circuits and are more sensitive to coupled noise. Any unnecessary pessimism of the noise analysis tool results in large number of false noise violations and either requires additional extensive SPICE simulations or circuit over-design. Unfortunately false noise analysis developed for static CMOS circuits fails to compute many logic correlations in domino circuits. In this paper we propose a novel technique of computing logic correlations in domino circuits. It takes into account the fact that both pull up and pull down networks of a domino gate can be in non conducting state. The proposed technique generates additional logic correlations for such states of domino gates. In order to improve the capability of logic correlation derivation technique we combine the resolution method with recursive learning algorithm. The proposed technique is implemented in an industrial noise analysis tool and tested on high performance ALU blocks.
{"title":"False-noise analysis for domino circuits","authors":"A. Glebov, S. Gavrilov, V. Zolotov, C. Oh, R. Panda, M. Becer","doi":"10.1109/DATE.2004.1268975","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268975","url":null,"abstract":"High-performance digital circuits are facing increasingly severe noise problems due to cross-coupled noise injection. Traditionally, noise analysis tools use the conservative assumption that all neighbors of a net can switch simultaneously, producing the worst-case noise. However, due to logic correlations in the circuit, this worst-case noise may not be realizable, resulting in a so-called false noise failure. Some techniques for computing logic correlations have been designed targeting static CMOS circuits. However high performance microprocessors commonly use domino logic for their ALU. The domino circuits have lower noise margins than static CMOS circuits and are more sensitive to coupled noise. Any unnecessary pessimism of the noise analysis tool results in large number of false noise violations and either requires additional extensive SPICE simulations or circuit over-design. Unfortunately false noise analysis developed for static CMOS circuits fails to compute many logic correlations in domino circuits. In this paper we propose a novel technique of computing logic correlations in domino circuits. It takes into account the fact that both pull up and pull down networks of a domino gate can be in non conducting state. The proposed technique generates additional logic correlations for such states of domino gates. In order to improve the capability of logic correlation derivation technique we combine the resolution method with recursive learning algorithm. The proposed technique is implemented in an industrial noise analysis tool and tested on high performance ALU blocks.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269099
Abhinav Agrawal, N. Jha
A function is reversible if each input vector produces a unique output vector. Reversible functions find applications in low power design, quantum computing, and nanotechnology. Logic synthesis for reversible circuits differs substantially from traditional logic synthesis. In this paper, we present the first practical synthesis algorithm and tool for reversible functions with a large number of inputs. It uses positive-polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. The heuristic uses a priority queue based search tree and explores candidate factors at each stage in order of attractiveness. The algorithm produces near-optimal results for the examples discussed in the literature. The key contribution of the work is that the heuristic finds very good solutions for reversible functions with a large number of inputs.
{"title":"Synthesis of reversible logic","authors":"Abhinav Agrawal, N. Jha","doi":"10.1109/DATE.2004.1269099","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269099","url":null,"abstract":"A function is reversible if each input vector produces a unique output vector. Reversible functions find applications in low power design, quantum computing, and nanotechnology. Logic synthesis for reversible circuits differs substantially from traditional logic synthesis. In this paper, we present the first practical synthesis algorithm and tool for reversible functions with a large number of inputs. It uses positive-polarity Reed-Muller decomposition at each stage to synthesize the function as a network of Toffoli gates. The heuristic uses a priority queue based search tree and explores candidate factors at each stage in order of attractiveness. The algorithm produces near-optimal results for the examples discussed in the literature. The key contribution of the work is that the heuristic finds very good solutions for reversible functions with a large number of inputs.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131809208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269049
C. Pinello, L. Carloni, A. Sangiovanni-Vincentelli
Designing cost-sensitive real-time control systems for safety-critical applications requires a careful analysis of the cost/coverage trade-offs of fault-tolerant solutions. This further complicates the difficult task of deploying the embedded software that implements the control algorithms on the execution platform that is often distributed around the plant (as it is typical, for instance, in automotive applications). We propose a synthesis-based design methodology that relieves the designers from the burden of specifying detailed mechanisms for addressing platform faults, while involving them in the definition of the overall fault-tolerance strategy. Thus, they can focus on addressing plant faults within their control algorithms, selecting the best components for the execution platform, and defining an accurate fault model. Our approach is centered on a new model of computation, fault tolerant data flows (FTDF), that enables the integration of formal validation techniques.
{"title":"Fault-tolerant deployment of embedded software for cost-sensitive real-time feedback-control applications","authors":"C. Pinello, L. Carloni, A. Sangiovanni-Vincentelli","doi":"10.1109/DATE.2004.1269049","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269049","url":null,"abstract":"Designing cost-sensitive real-time control systems for safety-critical applications requires a careful analysis of the cost/coverage trade-offs of fault-tolerant solutions. This further complicates the difficult task of deploying the embedded software that implements the control algorithms on the execution platform that is often distributed around the plant (as it is typical, for instance, in automotive applications). We propose a synthesis-based design methodology that relieves the designers from the burden of specifying detailed mechanisms for addressing platform faults, while involving them in the definition of the overall fault-tolerance strategy. Thus, they can focus on addressing plant faults within their control algorithms, selecting the best components for the execution platform, and defining an accurate fault model. Our approach is centered on a new model of computation, fault tolerant data flows (FTDF), that enables the integration of formal validation techniques.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131855384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, C. Chiang
In this paper, we propose a novel time-domain based method, discrete singular convolution algorithm, for computing steady-state response in nonlinear circuit. Properties and advantages of discrete singular convolution method are discussed, compared with some other approaches. The accuracy and efficiency of this method are tested by the numerical experiments.
{"title":"Steady-state analysis of nonlinear circuits using discrete singular convolution method","authors":"Xin Zhou, Dian Zhou, Jin Liu, Ruiming Li, Xuan Zeng, C. Chiang","doi":"10.5555/968879.969169","DOIUrl":"https://doi.org/10.5555/968879.969169","url":null,"abstract":"In this paper, we propose a novel time-domain based method, discrete singular convolution algorithm, for computing steady-state response in nonlinear circuit. Properties and advantages of discrete singular convolution method are discussed, compared with some other approaches. The accuracy and efficiency of this method are tested by the numerical experiments.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134339595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269071
M. Hohenauer, H. Scharwächter, K. Karuri, Oliver Wahlen, Tim Kogel, R. Leupers, G. Ascheid, H. Meyr, G. Braun, Hans van Someren
Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an industrial processor modeling language for efficient ASIP design. In order to circumvent the well-known trade-off between flexibility and code quality in retargetable compilation, we propose a user-guided, semiautomatic methodology that in turn builds on a powerful existing C compiler design platform. Our approach allows to include generated C compilers into the ASIP architecture exploration loop at an early stage, thereby allowing for a more efficient design process and avoiding application/architecture mismatches. We present the corresponding methodology and tool suite and provide experimental data for two real-life embedded processors that prove the feasibility of the approach.
{"title":"A methodology and tool suite for C compiler generation from ADL processor models","authors":"M. Hohenauer, H. Scharwächter, K. Karuri, Oliver Wahlen, Tim Kogel, R. Leupers, G. Ascheid, H. Meyr, G. Braun, Hans van Someren","doi":"10.1109/DATE.2004.1269071","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269071","url":null,"abstract":"Retargetable C compilers are key tools for efficient architecture exploration for embedded processors. In this paper we describe a novel approach to retargetable compilation based on LISA, an industrial processor modeling language for efficient ASIP design. In order to circumvent the well-known trade-off between flexibility and code quality in retargetable compilation, we propose a user-guided, semiautomatic methodology that in turn builds on a powerful existing C compiler design platform. Our approach allows to include generated C compilers into the ASIP architecture exploration loop at an early stage, thereby allowing for a more efficient design process and avoiding application/architecture mismatches. We present the corresponding methodology and tool suite and provide experimental data for two real-life embedded processors that prove the feasibility of the approach.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134559697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1269216
Tobias Thiel
At sign-off everybody is wondering about how good the accuracy of the static timing analysis timing reports generated with primetime/sup /spl reg// really is. Errors can be introduced by STA setup, interconnect modeling, library characterization etc. The claims that path timing calculated by primetime usually is within a few percent of spice don't help to ease your uncertainty. When the signal integrity features were introduced to primetime there was also a feature added that was hardly announced: primetime can write out timing paths for simulation with spice that can be used to validate the timing numbers calculated by primetime. By comparing the numbers calculated by primetime to a simulation with spice for selected paths the designers can verify the timing and build up confidence or identify errors. This paper will describe a validation flow for primetime timing reports that is based on extraction of the spice paths, starting the spice simulation, parsing the simulation results, and creating a report comparing primetime and spice timing. All these steps are done inside the TCL environment of primetime. It will describe this flow, what is needed for the spice simulation, how it can be set up, what can go wrong, and what kind of problems in the STA can be identified.
{"title":"Have I really met timing? - validating primetime timing reports with SPICE","authors":"Tobias Thiel","doi":"10.1109/DATE.2004.1269216","DOIUrl":"https://doi.org/10.1109/DATE.2004.1269216","url":null,"abstract":"At sign-off everybody is wondering about how good the accuracy of the static timing analysis timing reports generated with primetime/sup /spl reg// really is. Errors can be introduced by STA setup, interconnect modeling, library characterization etc. The claims that path timing calculated by primetime usually is within a few percent of spice don't help to ease your uncertainty. When the signal integrity features were introduced to primetime there was also a feature added that was hardly announced: primetime can write out timing paths for simulation with spice that can be used to validate the timing numbers calculated by primetime. By comparing the numbers calculated by primetime to a simulation with spice for selected paths the designers can verify the timing and build up confidence or identify errors. This paper will describe a validation flow for primetime timing reports that is based on extraction of the spice paths, starting the spice simulation, parsing the simulation results, and creating a report comparing primetime and spice timing. All these steps are done inside the TCL environment of primetime. It will describe this flow, what is needed for the spice simulation, how it can be set up, what can go wrong, and what kind of problems in the STA can be identified.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130365013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-02-16DOI: 10.1109/DATE.2004.1268903
D. G. Pérez, Gilles Mouchard, O. Temam
SystemC is rapidly gaining wide acceptance as a simulation framework for SoC and embedded processors. While its main assets are modularity and the very fact it is becoming a de facto standard, the evolution of the SystemC framework (from version 0.9 to version 2.0.1) suggests the environment is particularly geared toward increasing the framework functionalities rather than improving simulation speed. For cycle-level simulation, speed is a critical factor as simulation can be extremely slow, affecting the extent of design space exploration. In this article, we present a fast SystemC engine that, in our experience, can speed up simulations by a factor of 1.93 to 3.56 over SystemC 2.0.1. This SystemC engine is designed for cycle-level simulators and for the moment, it only supports the subset of the SystemC syntax (signals, methods) that is most often used for such simulators. We achieved greater speed (1) by completely rewriting the SystemC engine and improving the implementation software engineering, and (2) by proposing a new scheduling technique, intermediate between SystemC dynamic scheduling technique and existing static scheduling schemes. Unlike SystemC dynamic scheduling, our technique removes many if not all useless process wake-ups, while using a simpler scheduling algorithm than in existing static scheduling techniques.
{"title":"A new optimized implementation of the SystemC engine using acyclic scheduling","authors":"D. G. Pérez, Gilles Mouchard, O. Temam","doi":"10.1109/DATE.2004.1268903","DOIUrl":"https://doi.org/10.1109/DATE.2004.1268903","url":null,"abstract":"SystemC is rapidly gaining wide acceptance as a simulation framework for SoC and embedded processors. While its main assets are modularity and the very fact it is becoming a de facto standard, the evolution of the SystemC framework (from version 0.9 to version 2.0.1) suggests the environment is particularly geared toward increasing the framework functionalities rather than improving simulation speed. For cycle-level simulation, speed is a critical factor as simulation can be extremely slow, affecting the extent of design space exploration. In this article, we present a fast SystemC engine that, in our experience, can speed up simulations by a factor of 1.93 to 3.56 over SystemC 2.0.1. This SystemC engine is designed for cycle-level simulators and for the moment, it only supports the subset of the SystemC syntax (signals, methods) that is most often used for such simulators. We achieved greater speed (1) by completely rewriting the SystemC engine and improving the implementation software engineering, and (2) by proposing a new scheduling technique, intermediate between SystemC dynamic scheduling technique and existing static scheduling schemes. Unlike SystemC dynamic scheduling, our technique removes many if not all useless process wake-ups, while using a simpler scheduling algorithm than in existing static scheduling techniques.","PeriodicalId":335658,"journal":{"name":"Proceedings Design, Automation and Test in Europe Conference and Exhibition","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-02-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115074123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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