Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.739819
J. M. Rankin, P. Mattson
Controller-Pilot communications at NASA's Low Visibility Landing and Surface Operations (LVLASO) flight test (Atlanta, GA 1997) used a Mode-S datalink to reinforce normal VHF radio communications. The Controller-Pilot Datalink Communications (CPDLC) channel followed a modified version of the RTCA DO-219 standard to uplink taxi routes and hold clearances to NASA's 757 research aircraft. A Controller Interface (CI) workstation encoded the air traffic controllers' instructions into the DO-219 format. The CI also used electronic flight strips and a graphical map to increase the controllers' situational awareness. This paper investigates the statistical success of the CPDLC channel. "Lost" messages that did not appear on the display are analyzed for the fault source. Round trip time between the CI and the 757 displays are presented. Finally, the voice recognition accuracy statistics are examined.
{"title":"Controller-pilot data link statistics from NASA's 1997 Atlanta Flight Test","authors":"J. M. Rankin, P. Mattson","doi":"10.1109/DASC.1998.739819","DOIUrl":"https://doi.org/10.1109/DASC.1998.739819","url":null,"abstract":"Controller-Pilot communications at NASA's Low Visibility Landing and Surface Operations (LVLASO) flight test (Atlanta, GA 1997) used a Mode-S datalink to reinforce normal VHF radio communications. The Controller-Pilot Datalink Communications (CPDLC) channel followed a modified version of the RTCA DO-219 standard to uplink taxi routes and hold clearances to NASA's 757 research aircraft. A Controller Interface (CI) workstation encoded the air traffic controllers' instructions into the DO-219 format. The CI also used electronic flight strips and a graphical map to increase the controllers' situational awareness. This paper investigates the statistical success of the CPDLC channel. \"Lost\" messages that did not appear on the display are analyzed for the fault source. Round trip time between the CI and the 757 displays are presented. Finally, the voice recognition accuracy statistics are examined.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132018268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.741470
G. Walters, E. King, R. Kessinger, R. Fryer
As more complex devices with higher levels of integration are inserted into real-time systems, traditional testing methods are becoming obsolete. The most difficult obstacle to thorough testing of real time embedded systems is the lack of visibility into the operations of processing elements while application software is executing. It is now possible to design and implement processors for embedded applications that are binary compatible with commercial instruction sets and have specific features for visibility to facilitate the test, debug, and maintenance of real-time processing systems. These features include Real Time Non-intrusive Instrumentation (RTNI) and Behavioral Verification Technology/sup TM/ (BVT/sup TM/) and do not interfere in any way in the operation of the system. RTNI increases developer productivity by enabling direct observation of processor operation during system development, support and maintenance. BVT is used to automatically test the correct functional behavior of the integrated hardware and software against the system specification. The combination of RTNI and BVT significantly reduces system validation time, risk and cost, while increasing the coverage and assurance level. These features can be implemented in processors that are very high performance, low power, commercial grade, or radiation-hardened. Application of this approach is underway in the development of processors for military and commercial applications.
{"title":"Processor design and implementation for real-time testing of embedded systems","authors":"G. Walters, E. King, R. Kessinger, R. Fryer","doi":"10.1109/DASC.1998.741470","DOIUrl":"https://doi.org/10.1109/DASC.1998.741470","url":null,"abstract":"As more complex devices with higher levels of integration are inserted into real-time systems, traditional testing methods are becoming obsolete. The most difficult obstacle to thorough testing of real time embedded systems is the lack of visibility into the operations of processing elements while application software is executing. It is now possible to design and implement processors for embedded applications that are binary compatible with commercial instruction sets and have specific features for visibility to facilitate the test, debug, and maintenance of real-time processing systems. These features include Real Time Non-intrusive Instrumentation (RTNI) and Behavioral Verification Technology/sup TM/ (BVT/sup TM/) and do not interfere in any way in the operation of the system. RTNI increases developer productivity by enabling direct observation of processor operation during system development, support and maintenance. BVT is used to automatically test the correct functional behavior of the integrated hardware and software against the system specification. The combination of RTNI and BVT significantly reduces system validation time, risk and cost, while increasing the coverage and assurance level. These features can be implemented in processors that are very high performance, low power, commercial grade, or radiation-hardened. Application of this approach is underway in the development of processors for military and commercial applications.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132334287","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.741554
K. Goldsmith, P. A. Johnson
The Defence Science and Technology Organisation has conducted a research program to investigate the performance of reverberation chambers in establishing military aircraft electromagnetic vulnerability (EMV). The construction of an aircraft-sized chamber for research purposes offers special challenges, mostly financial. The most critical design parameters are the chamber dimensions, mode tuner size and wall material.
{"title":"Design, construction, computational EM modelling, and characterisation of an aircraft sized reverberation chamber and stirrer","authors":"K. Goldsmith, P. A. Johnson","doi":"10.1109/DASC.1998.741554","DOIUrl":"https://doi.org/10.1109/DASC.1998.741554","url":null,"abstract":"The Defence Science and Technology Organisation has conducted a research program to investigate the performance of reverberation chambers in establishing military aircraft electromagnetic vulnerability (EMV). The construction of an aircraft-sized chamber for research purposes offers special challenges, mostly financial. The most critical design parameters are the chamber dimensions, mode tuner size and wall material.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131817593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.741514
M. Glass
The Advanced Communications Engine (ACE) family of integrated dual redundant MIL-STD-1553 RT (Remote Terminal) and BC/RT/MT (Bus Controller/Remote Terminal/Bus Monitor) terminals with enhanced functions has been upgraded. The Mini-ACE Plus series addresses many of the key issues in today's market; specifically, the demand for COTS/MOTS, reduced cost and size, and requirements for MIL-STD-1760 stores applications. This paper reviews the features and the technology that were used to achieve the cost and functional improvements, and size reduction. The MINI-ACE Plus is a functional equivalent to the initial generation ACE family, but in a package that is half the size. This paper will discuss the processes and the technology used in the development of the MINI-ACE Plus MCM. This includes the issues and advantages of migrating to co-fired ceramic packaging, along with the evolution of the analog transceiver and digital protocol monolithic chips used in the Mini-ACE Plus terminals. This includes a functional overview of the ACE terminals. In addition, the paper discusses new features, involving an option for 64 K/spl times/16 RAM, an RT boot-up option, and additional clock frequencies. Finally, there is a discussion of software-related issues, including compatibility to previous generation terminals, and the availability of libraries that are portable to different hardware and software platforms.
集成双冗余MIL-STD-1553 RT(远程终端)和BC/RT/MT(总线控制器/远程终端/总线监视器)终端的高级通信引擎(ACE)系列已升级，功能增强。Mini-ACE Plus系列解决了当今市场上的许多关键问题;具体来说，对COTS/MOTS的需求，降低成本和尺寸，以及对MIL-STD-1760存储应用的要求。本文综述了用于实现成本和功能改进以及尺寸减小的特点和技术。MINI-ACE Plus的功能相当于第一代ACE系列，但封装尺寸只有原来的一半。本文将讨论MINI-ACE Plus MCM的开发过程和技术。这包括迁移到共烧陶瓷封装的问题和优势，以及Mini-ACE Plus终端中使用的模拟收发器和数字协议单片芯片的发展。其中包括对ACE终端的功能概述。此外，本文还讨论了新功能，包括64 K/spl次/16 RAM选项，RT启动选项和额外的时钟频率。最后，还讨论了与软件相关的问题，包括与上一代终端的兼容性，以及可移植到不同硬件和软件平台的库的可用性。
{"title":"The MINI-ACE plus family of MIL-STD-1553 terminals","authors":"M. Glass","doi":"10.1109/DASC.1998.741514","DOIUrl":"https://doi.org/10.1109/DASC.1998.741514","url":null,"abstract":"The Advanced Communications Engine (ACE) family of integrated dual redundant MIL-STD-1553 RT (Remote Terminal) and BC/RT/MT (Bus Controller/Remote Terminal/Bus Monitor) terminals with enhanced functions has been upgraded. The Mini-ACE Plus series addresses many of the key issues in today's market; specifically, the demand for COTS/MOTS, reduced cost and size, and requirements for MIL-STD-1760 stores applications. This paper reviews the features and the technology that were used to achieve the cost and functional improvements, and size reduction. The MINI-ACE Plus is a functional equivalent to the initial generation ACE family, but in a package that is half the size. This paper will discuss the processes and the technology used in the development of the MINI-ACE Plus MCM. This includes the issues and advantages of migrating to co-fired ceramic packaging, along with the evolution of the analog transceiver and digital protocol monolithic chips used in the Mini-ACE Plus terminals. This includes a functional overview of the ACE terminals. In addition, the paper discusses new features, involving an option for 64 K/spl times/16 RAM, an RT boot-up option, and additional clock frequencies. Finally, there is a discussion of software-related issues, including compatibility to previous generation terminals, and the availability of libraries that are portable to different hardware and software platforms.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130868207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.741464
D. E. Barber
As the world marketplace continues to demand "better, faster and cheaper", organizations are searching for new tools to assist them in meeting this need. Systems Engineering is at the heart of product development and improving the performance of this discipline is key to organizational success. The Systems Engineering Capability Model (SECM) is a tool that organizations can use to evaluate the capability of their current Systems Engineering process. The SECM also provides a framework that can be used as a guide for developing or improving a structured Systems Engineering process.
{"title":"An overview of the Systems Engineering Capability Model EIA/IS 731","authors":"D. E. Barber","doi":"10.1109/DASC.1998.741464","DOIUrl":"https://doi.org/10.1109/DASC.1998.741464","url":null,"abstract":"As the world marketplace continues to demand \"better, faster and cheaper\", organizations are searching for new tools to assist them in meeting this need. Systems Engineering is at the heart of product development and improving the performance of this discipline is key to organizational success. The Systems Engineering Capability Model (SECM) is a tool that organizations can use to evaluate the capability of their current Systems Engineering process. The SECM also provides a framework that can be used as a guide for developing or improving a structured Systems Engineering process.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131163260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.739856
T. Clay, C.R. Auletti
Direct Chip Attach (DCA) is the next logical progression for the electronics industry. DCA, by definition, is the process of attaching the microelectronic die directly to the substrate rather than installing the die inside an electronic package. The benefits are miniaturization, weight reduction, elimination of packaged parts screening, and better electrical performance. Depending on the package configuration and the required I/O, area reductions can range between four and eight times smaller than standard SMT packages and the weight reductions are even better in most cases. DCA also provides the user with greater design flexibility and eliminates the layer of NRE costs associated with multichip module (MCM) and chip scale (CSP) packaging. DCA can be categorized into two approaches: chip-on-board (wire bonding) and flip chip.
{"title":"Litton Amecom direct chip attach project","authors":"T. Clay, C.R. Auletti","doi":"10.1109/DASC.1998.739856","DOIUrl":"https://doi.org/10.1109/DASC.1998.739856","url":null,"abstract":"Direct Chip Attach (DCA) is the next logical progression for the electronics industry. DCA, by definition, is the process of attaching the microelectronic die directly to the substrate rather than installing the die inside an electronic package. The benefits are miniaturization, weight reduction, elimination of packaged parts screening, and better electrical performance. Depending on the package configuration and the required I/O, area reductions can range between four and eight times smaller than standard SMT packages and the weight reductions are even better in most cases. DCA also provides the user with greater design flexibility and eliminates the layer of NRE costs associated with multichip module (MCM) and chip scale (CSP) packaging. DCA can be categorized into two approaches: chip-on-board (wire bonding) and flip chip.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130843514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.739883
J. Hodgson, W. Hamel, C. Rutherford, J. Armfield
There is considerable interest within the military in improving the fuel efficiency of its vehicles. Hybrid powertrains for military applications offer the potential for improved fuel economy, enhanced stealth (silent operation) capability, and auxiliary field power generation. While recent hybrid electric HMMWV conversions have shown impressive performance, the likely estimated production cost is high. In cooperation with the National Automotive Center (part of the United States Army Tank-automotive and Armaments Command, TECOM), Oak Ridge National Laboratory (ORNL) and The University of Tennessee (UT) have conducted a conceptual design for a low production cost hybrid electric powertrain for the HMMWV. The design takes maximum advantage of commercial off-the-shelf (COTS) technology. The parallel, electric assist configuration offers hybrid performance equivalent to the conventional base vehicle for limited time periods, silent electric operation, and limp-home capability in the event of electric drive system failure. The design goals for the hybrid electric powertrain, the overall system design, and design decisions necessary to meet performance goals are reviewed. Performance simulation results show that the proposed powertrain design should meet or exceed the stated design goals.
{"title":"Design of a low production cost hybrid HMMWV","authors":"J. Hodgson, W. Hamel, C. Rutherford, J. Armfield","doi":"10.1109/DASC.1998.739883","DOIUrl":"https://doi.org/10.1109/DASC.1998.739883","url":null,"abstract":"There is considerable interest within the military in improving the fuel efficiency of its vehicles. Hybrid powertrains for military applications offer the potential for improved fuel economy, enhanced stealth (silent operation) capability, and auxiliary field power generation. While recent hybrid electric HMMWV conversions have shown impressive performance, the likely estimated production cost is high. In cooperation with the National Automotive Center (part of the United States Army Tank-automotive and Armaments Command, TECOM), Oak Ridge National Laboratory (ORNL) and The University of Tennessee (UT) have conducted a conceptual design for a low production cost hybrid electric powertrain for the HMMWV. The design takes maximum advantage of commercial off-the-shelf (COTS) technology. The parallel, electric assist configuration offers hybrid performance equivalent to the conventional base vehicle for limited time periods, silent electric operation, and limp-home capability in the event of electric drive system failure. The design goals for the hybrid electric powertrain, the overall system design, and design decisions necessary to meet performance goals are reviewed. Performance simulation results show that the proposed powertrain design should meet or exceed the stated design goals.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133498003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.739871
J.C. Reed
Recently, a "Side Zone" automotive radar, also known as the Side Detection System (SDS), has been introduced. The radar has a significant amount of signal processing aimed at tracking targets, estimating ground speed, and rejecting clutter. Introductory papers give an overview of the radar including performance requirements, requirements analysis, architecture design, signal processing, block diagrams, and test result summaries. This paper is primarily concerned with, and expands on, the signal processing techniques used in the SDS radar. Also, the method of waveform generation is described in detail, as it is intricately related to the radar signal processing.
{"title":"Signal processing and waveform generation in the side zone automotive radar","authors":"J.C. Reed","doi":"10.1109/DASC.1998.739871","DOIUrl":"https://doi.org/10.1109/DASC.1998.739871","url":null,"abstract":"Recently, a \"Side Zone\" automotive radar, also known as the Side Detection System (SDS), has been introduced. The radar has a significant amount of signal processing aimed at tracking targets, estimating ground speed, and rejecting clutter. Introductory papers give an overview of the radar including performance requirements, requirements analysis, architecture design, signal processing, block diagrams, and test result summaries. This paper is primarily concerned with, and expands on, the signal processing techniques used in the SDS radar. Also, the method of waveform generation is described in detail, as it is intricately related to the radar signal processing.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115336355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.739855
S. Nystrom, T.R. Smith, W. Peterson, D. L. LeFevre, D. Butcher, L. Gipson, M.M. Spanish
We have achieved a breakthrough in analog-to-digital converter (ADC) technology by demonstrating a robust, self-correcting 12-bit ADC ASIC architecture with about six times lower power dissipation than existing devices. The prototype ADC has noise and average differential nonlinearities so low that we believe it has the resolution required for 14 bits. The measured ADC power dissipation is 100 mW at 6 megasamples per second (MSPS)-six times lower than that of the best commercially available radiation-hardened ADC, which has only 11 effective bits of resolution. Four sample ADCs fabricated in a commercial, non-radiation-hardened process worked perfectly at total dose levels up to 50 krad(Si), a level sufficient for many space programs. The productized ADC is expected to be extremely radiation hardened: >300 krad(Si).
{"title":"Ultra-low-power, radiation-hardened 12-bit analog-to-digital converter for space-based electro-optical sensors","authors":"S. Nystrom, T.R. Smith, W. Peterson, D. L. LeFevre, D. Butcher, L. Gipson, M.M. Spanish","doi":"10.1109/DASC.1998.739855","DOIUrl":"https://doi.org/10.1109/DASC.1998.739855","url":null,"abstract":"We have achieved a breakthrough in analog-to-digital converter (ADC) technology by demonstrating a robust, self-correcting 12-bit ADC ASIC architecture with about six times lower power dissipation than existing devices. The prototype ADC has noise and average differential nonlinearities so low that we believe it has the resolution required for 14 bits. The measured ADC power dissipation is 100 mW at 6 megasamples per second (MSPS)-six times lower than that of the best commercially available radiation-hardened ADC, which has only 11 effective bits of resolution. Four sample ADCs fabricated in a commercial, non-radiation-hardened process worked perfectly at total dose levels up to 50 krad(Si), a level sufficient for many space programs. The productized ADC is expected to be extremely radiation hardened: >300 krad(Si).","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115817803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-10-31DOI: 10.1109/DASC.1998.741519
D. L. Swanson
Typical avionics systems today are structured in a federated architecture. Upgrading such systems has proven unwieldy and expensive, even as the advance of technology and increased functional requirements have made upgrades more imperative. Of particular concern is the systemic integration required for information superiority through multi-source data fusion. To improve this situation, the Maritime Avionics Subsystems and Technology Scalable Open Architecture Project (MAST SOAP) has designed a distributed avionics architecture. It is characterized by general-purpose hardware resources linked by an extensible communications network, an Object Request Broker infrastructure, and commercially available components with open interface standards. This paper outlines our approach to legacy system upgrades in the context of an open distributed architecture, presents the lessons we have learned that are applicable to such a system evolution, and discusses the performance implications involved in the use of such an architecture for an avionics system.
{"title":"Evolving avionics systems from federated to distributed architectures","authors":"D. L. Swanson","doi":"10.1109/DASC.1998.741519","DOIUrl":"https://doi.org/10.1109/DASC.1998.741519","url":null,"abstract":"Typical avionics systems today are structured in a federated architecture. Upgrading such systems has proven unwieldy and expensive, even as the advance of technology and increased functional requirements have made upgrades more imperative. Of particular concern is the systemic integration required for information superiority through multi-source data fusion. To improve this situation, the Maritime Avionics Subsystems and Technology Scalable Open Architecture Project (MAST SOAP) has designed a distributed avionics architecture. It is characterized by general-purpose hardware resources linked by an extensible communications network, an Object Request Broker infrastructure, and commercially available components with open interface standards. This paper outlines our approach to legacy system upgrades in the context of an open distributed architecture, presents the lessons we have learned that are applicable to such a system evolution, and discusses the performance implications involved in the use of such an architecture for an avionics system.","PeriodicalId":335827,"journal":{"name":"17th DASC. AIAA/IEEE/SAE. Digital Avionics Systems Conference. Proceedings (Cat. No.98CH36267)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115923163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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