Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.222970
Reinhard Lüling, B. Monien
The authors present a new load balancing strategy and its application to distributed branch & bound algorithms and demonstrate its efficiency by solving some NP-complete problems on a network of up to 256 transputers. The parallelization of their branch & bound algorithm is fully distributed. Every processor performs the same algorithm but each on a different part of the solution tree. In this case it is necessary to distribute subproblems among the processors to achieve a well balanced workload. Their load balancing method overcomes the problem of search overhead and idle times by an appropriate load model and avoids trashing effects by a feedback control method. Using this strategy they were able to achieve a speedup of up to 237.32 on a 256 processor network for very short parallel computation times, compared to an efficient sequential algorithm.<>
{"title":"Load balancing for distributed branch & bound algorithms","authors":"Reinhard Lüling, B. Monien","doi":"10.1109/IPPS.1992.222970","DOIUrl":"https://doi.org/10.1109/IPPS.1992.222970","url":null,"abstract":"The authors present a new load balancing strategy and its application to distributed branch & bound algorithms and demonstrate its efficiency by solving some NP-complete problems on a network of up to 256 transputers. The parallelization of their branch & bound algorithm is fully distributed. Every processor performs the same algorithm but each on a different part of the solution tree. In this case it is necessary to distribute subproblems among the processors to achieve a well balanced workload. Their load balancing method overcomes the problem of search overhead and idle times by an appropriate load model and avoids trashing effects by a feedback control method. Using this strategy they were able to achieve a speedup of up to 237.32 on a 256 processor network for very short parallel computation times, compared to an efficient sequential algorithm.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130617344","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.223034
T. K. Callaway, E. Swartzlander
The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. The paper examines two strategies for use at the macrocell level in implementing parallel processors. The two basic types of pooled macrocell redundancy are: 1 from N, and many from N. The use of either of these two strategies results in a premium being placed on the interconnect, which is often taken for granted. The paper demonstrates that the interconnect is a vital part of any macrocell pooled redundancy scheme.<>
{"title":"Implementation of parallel processors with wafer scale integration","authors":"T. K. Callaway, E. Swartzlander","doi":"10.1109/IPPS.1992.223034","DOIUrl":"https://doi.org/10.1109/IPPS.1992.223034","url":null,"abstract":"The use of a design strategy employing a hierarchy of structures, each with its own fault circumvention strategy can greatly improve the yield of WSI. The paper examines two strategies for use at the macrocell level in implementing parallel processors. The two basic types of pooled macrocell redundancy are: 1 from N, and many from N. The use of either of these two strategies results in a premium being placed on the interconnect, which is often taken for granted. The paper demonstrates that the interconnect is a vital part of any macrocell pooled redundancy scheme.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114621242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.222982
Manish Gupta, P. Banerjee
An important problem facing numerous research projects on parallelizing compilers for distributed memory machines is that of automatically determining a suitable data partitioning scheme for a program. Any strategy for automatic data partitioning needs a mechanism for estimating the performance of a program under a given partitioning scheme, the most crucial part of which involves determining the communication costs incurred by the program. The authors describe a methodology for statically estimating the communication times as certain functions of the array sizes and the numbers of processors over which various arrays used are distributed. This work also lays down a framework for effective synthesis of communication on multicomputers from sequential program references.<>
{"title":"Compile-time estimation of communication costs on multicomputers","authors":"Manish Gupta, P. Banerjee","doi":"10.1109/IPPS.1992.222982","DOIUrl":"https://doi.org/10.1109/IPPS.1992.222982","url":null,"abstract":"An important problem facing numerous research projects on parallelizing compilers for distributed memory machines is that of automatically determining a suitable data partitioning scheme for a program. Any strategy for automatic data partitioning needs a mechanism for estimating the performance of a program under a given partitioning scheme, the most crucial part of which involves determining the communication costs incurred by the program. The authors describe a methodology for statically estimating the communication times as certain functions of the array sizes and the numbers of processors over which various arrays used are distributed. This work also lays down a framework for effective synthesis of communication on multicomputers from sequential program references.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126369063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.223072
S. Fineberg, T. Casavant, B. H. Pease
With recent improvements in single CPU performance, several issues become more important in multiprocessor design. Two of these are interprocessor communication and locality. In parallel systems with fast CPUs, locality is vital to performance. However, traditional parallel programming models such as shared memory or message passing do not naturally lead to programs that exhibit locality. In the paper, the Seamless model for interprocessor communication is presented which is based on locality and that allows the programmer to explicitly manipulate a program's locality to optimize performance. Additionally, this model can support latency tolerance with proper hardware support. Extensions to the C programming language that support this model are also presented. Finally, a parallel program utilizing this model is provided to illustrate the paradigm.<>
{"title":"The seamless approach to reconciling communication and locality in distributed memory parallel systems","authors":"S. Fineberg, T. Casavant, B. H. Pease","doi":"10.1109/IPPS.1992.223072","DOIUrl":"https://doi.org/10.1109/IPPS.1992.223072","url":null,"abstract":"With recent improvements in single CPU performance, several issues become more important in multiprocessor design. Two of these are interprocessor communication and locality. In parallel systems with fast CPUs, locality is vital to performance. However, traditional parallel programming models such as shared memory or message passing do not naturally lead to programs that exhibit locality. In the paper, the Seamless model for interprocessor communication is presented which is based on locality and that allows the programmer to explicitly manipulate a program's locality to optimize performance. Additionally, this model can support latency tolerance with proper hardware support. Extensions to the C programming language that support this model are also presented. Finally, a parallel program utilizing this model is provided to illustrate the paradigm.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128056925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.222979
S. Koriem, L. Patnaik
The authors propose a novel technique to study composite reliability and performance (performability) measures of hypercube systems using generalized stochastic Petri nets (GSPNs). This technique essentially consists of the following: (i) a GSPN reliability model; (ii) a GSPN performance model; and (iii) a way of combining the results from these two models. Models and performability results for an iPSC/2 hypercube system under the workload of concurrent matrix multiplication algorithm are presented.<>
{"title":"Performability studies of hypercube architectures","authors":"S. Koriem, L. Patnaik","doi":"10.1109/IPPS.1992.222979","DOIUrl":"https://doi.org/10.1109/IPPS.1992.222979","url":null,"abstract":"The authors propose a novel technique to study composite reliability and performance (performability) measures of hypercube systems using generalized stochastic Petri nets (GSPNs). This technique essentially consists of the following: (i) a GSPN reliability model; (ii) a GSPN performance model; and (iii) a way of combining the results from these two models. Models and performability results for an iPSC/2 hypercube system under the workload of concurrent matrix multiplication algorithm are presented.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132211456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.223018
K. Schwan, A. Gheith, Hongyi Zhou
The authors have developed a portable family of object-based multiprocessor operating system kernels that address extensibility, customizability and efficiency for medium to large-grain parallelism, based on a single set of kernel-provided abstractions. The family is extensible in that new abstractions and functionalities can be added easily and efficiently. It is customizable in that existing kernel abstractions and functions can be modified easily. Efficiency within the family is obtained by reliance on the language level for enforcement of protection boundaries.<>
{"title":"Building families of object-based multiprocessor kernels","authors":"K. Schwan, A. Gheith, Hongyi Zhou","doi":"10.1109/IPPS.1992.223018","DOIUrl":"https://doi.org/10.1109/IPPS.1992.223018","url":null,"abstract":"The authors have developed a portable family of object-based multiprocessor operating system kernels that address extensibility, customizability and efficiency for medium to large-grain parallelism, based on a single set of kernel-provided abstractions. The family is extensible in that new abstractions and functionalities can be added easily and efficiently. It is customizable in that existing kernel abstractions and functions can be modified easily. Efficiency within the family is obtained by reliance on the language level for enforcement of protection boundaries.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130695545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.223009
G. Blelloch, S. Chatterjee, Marco Zagha
The article presents a variation of the partition method for solving m/sup th/-order linear recurrences that is well-suited to vector multiprocessors. The algorithm fully utilizes both vector and multiprocessor capabilities, and reduces the number of memory accesses as compared to the more commonly used version of the partition method. The variation uses a general loop restructuring technique called loop raking. The article describes an implementation of this technique on the CRAY Y-MP and presents performance results on first- and second-order linear recurrences, as well as on Livermore loops, 5, 11 and 19, which are based on linear recurrences.<>
{"title":"Solving linear recurrences with loop raking","authors":"G. Blelloch, S. Chatterjee, Marco Zagha","doi":"10.1109/IPPS.1992.223009","DOIUrl":"https://doi.org/10.1109/IPPS.1992.223009","url":null,"abstract":"The article presents a variation of the partition method for solving m/sup th/-order linear recurrences that is well-suited to vector multiprocessors. The algorithm fully utilizes both vector and multiprocessor capabilities, and reduces the number of memory accesses as compared to the more commonly used version of the partition method. The variation uses a general loop restructuring technique called loop raking. The article describes an implementation of this technique on the CRAY Y-MP and presents performance results on first- and second-order linear recurrences, as well as on Livermore loops, 5, 11 and 19, which are based on linear recurrences.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130999161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.222983
H. Nishikawa, P. Steenkiste
Aroma simplifies the task of parallelizing large applications in multicomputers by providing applications with a shared object space. Aroma supports both traditional monolithic objects and aggregate objects that can be partitioned across multiple nodes. Aggregate objects support data parallelism efficiently. An Aroma program consists of tasks that operate on shared objects. Tasks typically execute on the node on which their input data is located, thus minimizing communication. Shared data objects have synchronization properties associated with them, making it possible to parallelize a large class of applications without using explicit, locks and condition variables. The authors present and justify the Aroma language features, and give examples of Aroma programs. Aroma has been implemented on the Nectar multicomputer. The authors give performance results for several applications.<>
{"title":"Aroma: language support for distributed objects","authors":"H. Nishikawa, P. Steenkiste","doi":"10.1109/IPPS.1992.222983","DOIUrl":"https://doi.org/10.1109/IPPS.1992.222983","url":null,"abstract":"Aroma simplifies the task of parallelizing large applications in multicomputers by providing applications with a shared object space. Aroma supports both traditional monolithic objects and aggregate objects that can be partitioned across multiple nodes. Aggregate objects support data parallelism efficiently. An Aroma program consists of tasks that operate on shared objects. Tasks typically execute on the node on which their input data is located, thus minimizing communication. Shared data objects have synchronization properties associated with them, making it possible to parallelize a large class of applications without using explicit, locks and condition variables. The authors present and justify the Aroma language features, and give examples of Aroma programs. Aroma has been implemented on the Nectar multicomputer. The authors give performance results for several applications.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115350879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.222981
P. Mills, L. Nyland, J. Prins, J. Reif
This paper explores the use of Proteus, an architecture-independent language suitable for prototyping parallel and distributed programs. Proteus is a high-level imperative notation based on sets and sequences with a single construct for the parallel composition of processes communicating through shared memory. Several different parallel algorithms for N-body simulation are presented in Proteus, illustrating how Proteus provides a common foundation for expressing the various parallel programming models. This common foundation allows prototype parallel programs to be tested and evolved without the use of machine-specific languages. To transform prototypes to implementations on specific architectures, program refinement techniques are utilized. Refinement strategies are illustrated that target broad-spectrum parallel intermediate languages, and their viability is demonstrated by refining an N-body algorithm to data-parallel CVL code.<>
{"title":"Prototyping N-body simulation in Proteus","authors":"P. Mills, L. Nyland, J. Prins, J. Reif","doi":"10.1109/IPPS.1992.222981","DOIUrl":"https://doi.org/10.1109/IPPS.1992.222981","url":null,"abstract":"This paper explores the use of Proteus, an architecture-independent language suitable for prototyping parallel and distributed programs. Proteus is a high-level imperative notation based on sets and sequences with a single construct for the parallel composition of processes communicating through shared memory. Several different parallel algorithms for N-body simulation are presented in Proteus, illustrating how Proteus provides a common foundation for expressing the various parallel programming models. This common foundation allows prototype parallel programs to be tested and evolved without the use of machine-specific languages. To transform prototypes to implementations on specific architectures, program refinement techniques are utilized. Refinement strategies are illustrated that target broad-spectrum parallel intermediate languages, and their viability is demonstrated by refining an N-body algorithm to data-parallel CVL code.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124407988","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1992-03-01DOI: 10.1109/IPPS.1992.223068
Ashok Khemka, R. Shyamasundar
Preemptive scheduling a set of periodic tasks on multiprocessors is studied from the point of view of meeting their service requirements before given deadlines. Sufficient conditions permitting full utilization of the multiprocessor using the given scheduling algorithm are derived. Complexity of the scheduling algorithms including upper bounds on the number of preemptions are derived. Schemes (with little run-time cost) for on-line handling of tasks' arrival and exit are given.<>
{"title":"Multiprocessor scheduling of periodic tasks in a hard real-time environment","authors":"Ashok Khemka, R. Shyamasundar","doi":"10.1109/IPPS.1992.223068","DOIUrl":"https://doi.org/10.1109/IPPS.1992.223068","url":null,"abstract":"Preemptive scheduling a set of periodic tasks on multiprocessors is studied from the point of view of meeting their service requirements before given deadlines. Sufficient conditions permitting full utilization of the multiprocessor using the given scheduling algorithm are derived. Complexity of the scheduling algorithms including upper bounds on the number of preemptions are derived. Schemes (with little run-time cost) for on-line handling of tasks' arrival and exit are given.<<ETX>>","PeriodicalId":340070,"journal":{"name":"Proceedings Sixth International Parallel Processing Symposium","volume":"156 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123706974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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