Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250856
Junchao Chen, T. Lange, M. Andjelković, A. Simevski, M. Krstic
The intensity of cosmic radiation can differ over five orders of magnitude within a few hours or days during Solar Particle Events (SPEs), thus increasing the probability of Single-Event Upsets (SEUs) in space applications for several orders of magnitude. Therefore, it is vital to employ the early detection of the SEU rate changes in order to ensure timely activation of the radiation hardening measures. In this paper, a hardware accelerator for forecasting the SPEs by the prediction of in-flight SEU variation is proposed. An embedded on-chip SRAM is used as the real-time particle detector. The dedicated hardware accelerator implements a supervised machine learning model to forecast the SRAM SEUs one hour in advance with fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions. The whole design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications. Therefore, the target system can drive the appropriate radiation hardening mechanisms before the onset of high radiation levels.
{"title":"Hardware Accelerator Design with Supervised Machine Learning for Solar Particle Event Prediction","authors":"Junchao Chen, T. Lange, M. Andjelković, A. Simevski, M. Krstic","doi":"10.1109/DFT50435.2020.9250856","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250856","url":null,"abstract":"The intensity of cosmic radiation can differ over five orders of magnitude within a few hours or days during Solar Particle Events (SPEs), thus increasing the probability of Single-Event Upsets (SEUs) in space applications for several orders of magnitude. Therefore, it is vital to employ the early detection of the SEU rate changes in order to ensure timely activation of the radiation hardening measures. In this paper, a hardware accelerator for forecasting the SPEs by the prediction of in-flight SEU variation is proposed. An embedded on-chip SRAM is used as the real-time particle detector. The dedicated hardware accelerator implements a supervised machine learning model to forecast the SRAM SEUs one hour in advance with fine-grained hourly tracking of SEU variations during SPEs as well as under normal conditions. The whole design is intended for a highly dependable and self-adaptive multiprocessing system employed in space applications. Therefore, the target system can drive the appropriate radiation hardening mechanisms before the onset of high radiation levels.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"2675 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114837440","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250893
D. Theodoropoulos, N. Kranitis, A. Tsigkanos, A. Paschalis
Low-Density Parity-Check (LDPC) codes are widely considered an advantageous option for forward error correction (FEC) on magnetic recording (MR) media. The vast majority of related research, however, has so far been focused on the analytical optimization of code design and algorithms. Although high-speed encoding and decoding with low hardware footprint are important for MR media, hardware implementations for such encoding schemes have so far been scarce. Among the proposed LDPC code variants, protograph-based codes are a promising option, because of their excellent performance characteristics and efficient implementation. In this work, we leverage the architecture of our previous work on LDPC encoders for space applications and we propose efficient encoder designs for the protograph-based LDPC codes proposed so far for MR media. The proposed designs are implemented in hardware as Field Programmable Gate Array (FPGA) accelerators. The efficiency of the introduced architectures is demonstrated on an FPGA development board, achieving multi-Gbps throughput, adequate for modern MR application standards.
{"title":"Efficient LDPC Encoder Designs for Magnetic Recording Media","authors":"D. Theodoropoulos, N. Kranitis, A. Tsigkanos, A. Paschalis","doi":"10.1109/DFT50435.2020.9250893","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250893","url":null,"abstract":"Low-Density Parity-Check (LDPC) codes are widely considered an advantageous option for forward error correction (FEC) on magnetic recording (MR) media. The vast majority of related research, however, has so far been focused on the analytical optimization of code design and algorithms. Although high-speed encoding and decoding with low hardware footprint are important for MR media, hardware implementations for such encoding schemes have so far been scarce. Among the proposed LDPC code variants, protograph-based codes are a promising option, because of their excellent performance characteristics and efficient implementation. In this work, we leverage the architecture of our previous work on LDPC encoders for space applications and we propose efficient encoder designs for the protograph-based LDPC codes proposed so far for MR media. The proposed designs are implemented in hardware as Field Programmable Gate Array (FPGA) accelerators. The efficiency of the introduced architectures is demonstrated on an FPGA development board, achieving multi-Gbps throughput, adequate for modern MR application standards.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123891630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250922
Alexander Sprenger, Somayeh Sadeghi Kohan, Jan Dennis Reimer, S. Hellebrand
In today’s system-on-chips, interconnects increasingly affect the reliability of the system. Crosstalk defects can result in delay and glitch faults and also aggravate aging mechanisms such as electro-migration. Furthermore, fab-induced deviations of the interconnect layout may lead to a reduced line spacing and enlarged crosstalk defects. While crosstalk testing at the system level directly measures the behavior of the interconnect section under test, at the logic level crosstalk effects may interfere with delay faults or parameter variations in the logic components. In particular, detecting gate-level crosstalk defects in the presence of parameter variations is a very challenging, yet very important task. In this work a method to distinguish between crosstalk-induced delays and parameter variations is presented. It is based on delay maps obtained from testing at multiple operating points. These delays maps can be classified into crosstalk-induced and variation-induced delay maps using an artificial neural network with a high success rate. Furthermore, it is shown how the basic classification scheme can be tuned to the practical constraints of interconnect testing.
{"title":"Variation-Aware Test for Logic Interconnects using Neural Networks – A Case Study","authors":"Alexander Sprenger, Somayeh Sadeghi Kohan, Jan Dennis Reimer, S. Hellebrand","doi":"10.1109/DFT50435.2020.9250922","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250922","url":null,"abstract":"In today’s system-on-chips, interconnects increasingly affect the reliability of the system. Crosstalk defects can result in delay and glitch faults and also aggravate aging mechanisms such as electro-migration. Furthermore, fab-induced deviations of the interconnect layout may lead to a reduced line spacing and enlarged crosstalk defects. While crosstalk testing at the system level directly measures the behavior of the interconnect section under test, at the logic level crosstalk effects may interfere with delay faults or parameter variations in the logic components. In particular, detecting gate-level crosstalk defects in the presence of parameter variations is a very challenging, yet very important task. In this work a method to distinguish between crosstalk-induced delays and parameter variations is presented. It is based on delay maps obtained from testing at multiple operating points. These delays maps can be classified into crosstalk-induced and variation-induced delay maps using an artificial neural network with a high success rate. Furthermore, it is shown how the basic classification scheme can be tuned to the practical constraints of interconnect testing.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"24 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113972148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is reported that many cell-internal defects remain undetected when VLSI testing is performed using test sets generated for only traditional fault models like stuck-at faults and transition faults. Therefore, test generation methods for cell-aware, defect-aware, and gate-exhaustive fault models have been proposed to resolve the problem. In all the cases, since the numbers of faults and test patterns can be large, test compaction is very important. In this paper, we propose a multiple target test generation method for gate-exhaustive faults to reduce the number of test patterns using Partial MaxSAT. We aim to generate a test pattern which can detect as many target faults as possible simultaneously by Partial MaxSAT. We also propose a multiple target fault selection method for the test generation using independent fault sets and justification technique. Experimental results on ISCAS’89 benchmark circuits show that the number of test patterns was reduced by 35.39% compared with a conventional method on average.
{"title":"A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT","authors":"Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai","doi":"10.1109/DFT50435.2020.9250810","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250810","url":null,"abstract":"It is reported that many cell-internal defects remain undetected when VLSI testing is performed using test sets generated for only traditional fault models like stuck-at faults and transition faults. Therefore, test generation methods for cell-aware, defect-aware, and gate-exhaustive fault models have been proposed to resolve the problem. In all the cases, since the numbers of faults and test patterns can be large, test compaction is very important. In this paper, we propose a multiple target test generation method for gate-exhaustive faults to reduce the number of test patterns using Partial MaxSAT. We aim to generate a test pattern which can detect as many target faults as possible simultaneously by Partial MaxSAT. We also propose a multiple target fault selection method for the test generation using independent fault sets and justification technique. Experimental results on ISCAS’89 benchmark circuits show that the number of test patterns was reduced by 35.39% compared with a conventional method on average.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"131 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130781089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250871
Marcello Barbirotta, A. Mastrandrea, F. Menichelli, F. Vigli, L. Blasi, Abdallah Cheikh, Stefano Sordillo, F. D. Gennaro, M. Olivieri
Fault tolerance is a key requirement in several application domains of embedded processors cores. In a wide variety of applications, however, a full protection against faults occurring in any bit of the core may be oversized, and it has been demonstrated that the system level impact of local faults in the microprocessor chips also depends on the program being executed. As a result, it is relevant to study the fault injection resilience of a processor hardware design with an application-oriented methodology. Previous studies addressed either physical fault injection on FPGA prototypes, or RTL analysis and mixed-level approaches involving UVM, SystemC and DSL libraries. These methods are based on massive random error injection requiring impractical amounts of time, often limited to specific architecture sub-parts. In this work we present the advantages of an RTL, deterministic bit-level cycle-accurate fault injection analysis implemented in a pure UVM Environment. The approach allows characterizing the fault resilience of each bit of the microarchitecture at application level, paving the way to a subsequent customized protection based on the upper bound of error probability. Also, the characterization detects the time intervals corresponding to critical section of the program execution for each bit of the microarchitecture, sometimes leading to unexpected results. We discuss the advantages of a hierarchical time frame span of the execution time with injected faults rather than a uniform timing distribution of faults, and we set up the error classification methodology according to how each faulty bit can damage the system in different execution time sections. We carry out our experiments targeting the Klessydra T03 RISC-V open-source processor core, covering all of the 5561 register bits and characterizing two benchmark program executions, in less than 100 hours’ simulation.
{"title":"Fault resilience analysis of a RISC-V microprocessor design through a dedicated UVM environment","authors":"Marcello Barbirotta, A. Mastrandrea, F. Menichelli, F. Vigli, L. Blasi, Abdallah Cheikh, Stefano Sordillo, F. D. Gennaro, M. Olivieri","doi":"10.1109/DFT50435.2020.9250871","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250871","url":null,"abstract":"Fault tolerance is a key requirement in several application domains of embedded processors cores. In a wide variety of applications, however, a full protection against faults occurring in any bit of the core may be oversized, and it has been demonstrated that the system level impact of local faults in the microprocessor chips also depends on the program being executed. As a result, it is relevant to study the fault injection resilience of a processor hardware design with an application-oriented methodology. Previous studies addressed either physical fault injection on FPGA prototypes, or RTL analysis and mixed-level approaches involving UVM, SystemC and DSL libraries. These methods are based on massive random error injection requiring impractical amounts of time, often limited to specific architecture sub-parts. In this work we present the advantages of an RTL, deterministic bit-level cycle-accurate fault injection analysis implemented in a pure UVM Environment. The approach allows characterizing the fault resilience of each bit of the microarchitecture at application level, paving the way to a subsequent customized protection based on the upper bound of error probability. Also, the characterization detects the time intervals corresponding to critical section of the program execution for each bit of the microarchitecture, sometimes leading to unexpected results. We discuss the advantages of a hierarchical time frame span of the execution time with injected faults rather than a uniform timing distribution of faults, and we set up the error classification methodology according to how each faulty bit can damage the system in different execution time sections. We carry out our experiments targeting the Klessydra T03 RISC-V open-source processor core, covering all of the 5561 register bits and characterizing two benchmark program executions, in less than 100 hours’ simulation.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128760064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250900
T. Vayssade, F. Azaïs, L. Latorre, F. Lefèvre
This paper targets the challenging issue of production test cost reduction for RF circuits. More specifically, it proposes a low-cost solution to perform EVM measurement of ZigBee transceivers using only a standard digital test equipment. The approach is based on 1-bit under-sampled acquisition of the RF modulated-signal by a digital tester channel associated with a specifically-tailored processing algorithm. The different steps of the post-processing algorithm are detailed in the paper. Hardware experimental results obtained on both a Universal Software Radio Peripheral (USRP) that emulates the circuit-under-test and on an actual ZigBee transceiver IC are presented.
{"title":"EVM measurement of RF ZigBee transceivers using standard digital ATE","authors":"T. Vayssade, F. Azaïs, L. Latorre, F. Lefèvre","doi":"10.1109/DFT50435.2020.9250900","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250900","url":null,"abstract":"This paper targets the challenging issue of production test cost reduction for RF circuits. More specifically, it proposes a low-cost solution to perform EVM measurement of ZigBee transceivers using only a standard digital test equipment. The approach is based on 1-bit under-sampled acquisition of the RF modulated-signal by a digital tester channel associated with a specifically-tailored processing algorithm. The different steps of the post-processing algorithm are detailed in the paper. Hardware experimental results obtained on both a Universal Software Radio Peripheral (USRP) that emulates the circuit-under-test and on an actual ZigBee transceiver IC are presented.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134636011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250870
Athanasios Papadimitriou, Konstantinos Nomikos, M. Psarakis, Ehsan Aerabi, D. Hély
Cryptographic implementations are prune to Side Channel Analysis (SCA) attacks and Fault Injection (FI) attacks at the same time. Therefore, countermeasures protecting an implementation need to be evaluated against both attacks. The main contribution of this work is twofold. First, we propose an evaluation platform capable to perform emulated fault injection campaigns against modern MCUs and at the same time able to acquire experimental electromagnetic EM emissions and power traces of cryptographic computations to be used for SCA attacks. Second, we perform experimental evaluations of countermeasures protecting against both SCA and FI attacks which show that the injections of faults can dramatically reduce the effectiveness of SCA countermeasures. We evaluate two cryptographic algorithms, an AES and a PRESENT-Sbox implementation, which are protected employing different countermeasures protecting in parallel against FI and SCA attacks. The AES secure implementation is protected by hiding-based SCA countermeasures, while it uses a redundancy-based technique against FI attacks. On the other hand, the PRESENT Sbox is protected by a software implementation of a Dual-rail with Precharge Logic (DPL) countermeasure including fault detection capabilities. We present extensive experimental evaluations for the AES implementation and first results for PRESENT-Sbox showing that for both implementations the fault injections increase the efficiency of the SCA attacks and lead to very fast recoveries of the secret keys.
{"title":"You can detect but you cannot hide: Fault Assisted Side Channel Analysis on Protected Software-based Block Ciphers","authors":"Athanasios Papadimitriou, Konstantinos Nomikos, M. Psarakis, Ehsan Aerabi, D. Hély","doi":"10.1109/DFT50435.2020.9250870","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250870","url":null,"abstract":"Cryptographic implementations are prune to Side Channel Analysis (SCA) attacks and Fault Injection (FI) attacks at the same time. Therefore, countermeasures protecting an implementation need to be evaluated against both attacks. The main contribution of this work is twofold. First, we propose an evaluation platform capable to perform emulated fault injection campaigns against modern MCUs and at the same time able to acquire experimental electromagnetic EM emissions and power traces of cryptographic computations to be used for SCA attacks. Second, we perform experimental evaluations of countermeasures protecting against both SCA and FI attacks which show that the injections of faults can dramatically reduce the effectiveness of SCA countermeasures. We evaluate two cryptographic algorithms, an AES and a PRESENT-Sbox implementation, which are protected employing different countermeasures protecting in parallel against FI and SCA attacks. The AES secure implementation is protected by hiding-based SCA countermeasures, while it uses a redundancy-based technique against FI attacks. On the other hand, the PRESENT Sbox is protected by a software implementation of a Dual-rail with Precharge Logic (DPL) countermeasure including fault detection capabilities. We present extensive experimental evaluations for the AES implementation and first results for PRESENT-Sbox showing that for both implementations the fault injections increase the efficiency of the SCA attacks and lead to very fast recoveries of the secret keys.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132024038","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250796
Danilo Cappellone, Stefano Di Mascio, G. Furano, A. Menicucci, M. Ottavi
The aim of this paper is to assess the feasibility and on-board hardware performance requirements for on-board telemetry forecasting by implementing a Recurrent Neural Network (RNN) on low-cost multicore RISC-V microprocessor. Gravity field and steady-state Ocean Circulation Explorer (GOCE) public telemetry data was used for training RNNs with different hyperparameters and architectures. The prediction accuracy of these models was evaluated using mean error and R-squared score on the same test dataset. The implementation of the RNN on a RISC-V embedded device, representative of future space-grade hardware, required some adaptations and modifications due to the computational requirements and the large memory footprint. The algorithm was implemented to run in parallel on the 8 cores of the microprocessor and tiling was employed for the weight matrices. Further considerations have also been made for the approximation of sigmoid and hyperbolic tangent as activation functions.
{"title":"On-Board Satellite Telemetry Forecasting with RNN on RISC-V Based Multicore Processor","authors":"Danilo Cappellone, Stefano Di Mascio, G. Furano, A. Menicucci, M. Ottavi","doi":"10.1109/DFT50435.2020.9250796","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250796","url":null,"abstract":"The aim of this paper is to assess the feasibility and on-board hardware performance requirements for on-board telemetry forecasting by implementing a Recurrent Neural Network (RNN) on low-cost multicore RISC-V microprocessor. Gravity field and steady-state Ocean Circulation Explorer (GOCE) public telemetry data was used for training RNNs with different hyperparameters and architectures. The prediction accuracy of these models was evaluated using mean error and R-squared score on the same test dataset. The implementation of the RNN on a RISC-V embedded device, representative of future space-grade hardware, required some adaptations and modifications due to the computational requirements and the large memory footprint. The algorithm was implemented to run in parallel on the 8 cores of the microprocessor and tiling was employed for the weight matrices. Further considerations have also been made for the approximation of sigmoid and hyperbolic tangent as activation functions.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121562661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：