Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250762
Xiaohan Yang, S. Khandelwal, Aiqi Jiang, A. Jabir
Memristors are finding applications in memory, logic, neuromorphic systems, and data security. To this end, we leverage the non-linear behaviour of memristors to devise a low overhead physical unclonable function using a memristive chaos circuit in conjunction with a non-linear memristive encoder. We demonstrate the effectiveness of this architecture in Challenge-Response-Pair based authentication, and for its physical uncloneability. This architecture is highly versatile and can be implemented with a single encoder or a number of encoders running in parallel, each one with its own merit, for extending the sizes of CRPs. To demonstrate its effectiveness, we subject the architecture to machine learning based modelling attacks e.g. Logistic Regression, Support Vector Machines, Random Forest, as well as Artificial Neural Network classifiers. We found out that the proposed PUF architecture provides better resistance to such attacks, even for smaller bit sizes and at reduced overheads.
{"title":"A Modelling Attack Resistant Low Overhead Memristive Physical Unclonable Function","authors":"Xiaohan Yang, S. Khandelwal, Aiqi Jiang, A. Jabir","doi":"10.1109/DFT50435.2020.9250762","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250762","url":null,"abstract":"Memristors are finding applications in memory, logic, neuromorphic systems, and data security. To this end, we leverage the non-linear behaviour of memristors to devise a low overhead physical unclonable function using a memristive chaos circuit in conjunction with a non-linear memristive encoder. We demonstrate the effectiveness of this architecture in Challenge-Response-Pair based authentication, and for its physical uncloneability. This architecture is highly versatile and can be implemented with a single encoder or a number of encoders running in parallel, each one with its own merit, for extending the sizes of CRPs. To demonstrate its effectiveness, we subject the architecture to machine learning based modelling attacks e.g. Logistic Regression, Support Vector Machines, Random Forest, as well as Artificial Neural Network classifiers. We found out that the proposed PUF architecture provides better resistance to such attacks, even for smaller bit sizes and at reduced overheads.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122565552","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250874
P. Habiby, S. Huhn, R. Drechsler
New test access methodologies are required to cope with the ever-increasing complexity of latest system-on-a-chip designs. The IEEE 1687 standard defines an access methodology to embedded instruments through a reconfigurable scan infrastructure. This technique allows implementing even large networks while keeping the individual access time low since only relevant parts of the scan chain are included in the scan path. However, the reconfiguration introduces a timing overhead, which can be mitigated by accessing instruments concurrently. The concurrent activation of instruments forms a critical aspect from the power management perspective since latest designs consist of multiple power domains with individual power constraints. To avoid any test failures, it must be avoided that the total power consumption of the concurrently activated instruments exceeds the domain’s power limit. Particularly when considering highly complex IEEE 1687 networks, which reveal the full potential of the standard by introducing hierarchical and optimized networks, the power-aware test scheduling is a non-trivial task.This paper proposes a test scheduling scheme for complex IEEE 1687 networks, which heavily orchestrates graph-based methods. In the end, an optimized test plan is determined, which ensures, on the one hand, a minimized overall test access time and, on the other hand, full compliance with the given power constraints. The approach’s efficacy is demonstrated on state-of-the-art benchmark sets involving complex networks with various power domains.
{"title":"Power-aware Test Scheduling for IEEE 1687 Networks with Multiple Power Domains","authors":"P. Habiby, S. Huhn, R. Drechsler","doi":"10.1109/DFT50435.2020.9250874","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250874","url":null,"abstract":"New test access methodologies are required to cope with the ever-increasing complexity of latest system-on-a-chip designs. The IEEE 1687 standard defines an access methodology to embedded instruments through a reconfigurable scan infrastructure. This technique allows implementing even large networks while keeping the individual access time low since only relevant parts of the scan chain are included in the scan path. However, the reconfiguration introduces a timing overhead, which can be mitigated by accessing instruments concurrently. The concurrent activation of instruments forms a critical aspect from the power management perspective since latest designs consist of multiple power domains with individual power constraints. To avoid any test failures, it must be avoided that the total power consumption of the concurrently activated instruments exceeds the domain’s power limit. Particularly when considering highly complex IEEE 1687 networks, which reveal the full potential of the standard by introducing hierarchical and optimized networks, the power-aware test scheduling is a non-trivial task.This paper proposes a test scheduling scheme for complex IEEE 1687 networks, which heavily orchestrates graph-based methods. In the end, an optimized test plan is determined, which ensures, on the one hand, a minimized overall test access time and, on the other hand, full compliance with the given power constraints. The approach’s efficacy is demonstrated on state-of-the-art benchmark sets involving complex networks with various power domains.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121641086","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250763
Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Z. Navabi
Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.
{"title":"Reducing DFT hardware overhead by use of a test microprogram in a microprogrammed hardware accelerator","authors":"Maryam Rajabalipanah, Seyedeh Maryam Ghasemi, Nooshin Nosrati, Katayoon Basharkhah, Saba Yousefzadeh, Z. Navabi","doi":"10.1109/DFT50435.2020.9250763","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250763","url":null,"abstract":"Because of heavy repeated computations and concurrency in the execution of many machine learning applications, embedded hardware architectures based on reconfigurable accelerators have emerged as a convenient and efficient means of hardware implementation. The reloadable microinstructions in a microprogrammed architecture provide an opportunity for self-testing of the accelerator by a test microprogram. This paper describes a mechanism of testing microprogrammed accelerators of an embedded system. We utilize the accelerator microinstructions to test the datapath and controller of our existing home-grown accelerator, called iMPAC. For prototyping, this architecture is implemented on an FPGA and its testing is compared with a hard-wired controller utilizing scan and other standard test techniques.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124364813","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250869
R. Cantoro, N. I. Deligiannis, M. Reorda, Marcello Traiola, E. Valea
Nowadays, many electronic systems store valuable Intellectual Property (IP) information inside Non-Volatile Memories (NVMs). Therefore, encryption mechanisms are widely used in order to protect such information from being stolen or modified by human attacks. Encryption techniques can be used for protecting the application code, or sensitive sets of data in the NVM. In particular, in machine-learning applications, the weights of an Artificial Neural Network (ANN) represent a highly valuable IP stemming from long time invested in training the system along the development phase. On the other side, systems implementing ANN applications are increasingly used in safety-critical domains (e.g., autonomous driving), where a high reliability level is required. In a previous paper, we have shown that encryption techniques, applied to the application code of generic systems, provide a significantly higher error detection rate. In this paper, we focus on an ANN application and we evaluate the detection rate induced by encryption mechanisms for transient faults possibly impacting the ANN weights. We performed experiments on a pre-trained ANN, whose weights represent the sensitive IP of our system. We executed fault injection campaigns to evaluate the ANN resilience when different encryption methods are used. Experimental results showed that the presence of specific encryption mechanisms alone induces high fault detection rates in such applications. This may allow the designer to consider security and safety mechanisms together, achieving the same results with lower costs.
{"title":"Evaluating Data Encryption Effects on the Resilience of an Artificial Neural Network","authors":"R. Cantoro, N. I. Deligiannis, M. Reorda, Marcello Traiola, E. Valea","doi":"10.1109/DFT50435.2020.9250869","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250869","url":null,"abstract":"Nowadays, many electronic systems store valuable Intellectual Property (IP) information inside Non-Volatile Memories (NVMs). Therefore, encryption mechanisms are widely used in order to protect such information from being stolen or modified by human attacks. Encryption techniques can be used for protecting the application code, or sensitive sets of data in the NVM. In particular, in machine-learning applications, the weights of an Artificial Neural Network (ANN) represent a highly valuable IP stemming from long time invested in training the system along the development phase. On the other side, systems implementing ANN applications are increasingly used in safety-critical domains (e.g., autonomous driving), where a high reliability level is required. In a previous paper, we have shown that encryption techniques, applied to the application code of generic systems, provide a significantly higher error detection rate. In this paper, we focus on an ANN application and we evaluate the detection rate induced by encryption mechanisms for transient faults possibly impacting the ANN weights. We performed experiments on a pre-trained ANN, whose weights represent the sensitive IP of our system. We executed fault injection campaigns to evaluate the ANN resilience when different encryption methods are used. Experimental results showed that the presence of specific encryption mechanisms alone induces high fault detection rates in such applications. This may allow the designer to consider security and safety mechanisms together, achieving the same results with lower costs.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131604829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250866
A. Ruospo, Angelo Balaara, A. Bosio, Ernesto Sánchez
Applications leveraging on new computing paradigms, such as brain-inspired computing, are currently being exploited in many fields thanks to their outstanding performance in solving complex tasks. Among them, Deep Neural Networks (DNNs) are gaining growing interest in different research areas spanning from playing complex games to safety-critical applications such as automotive. In the latter case, reliability assumes a dominant role and efficient reliability assessment approaches are thus required. Several works evaluate the DNN reliability by running fault injection campaigns. However, due to the excessive time required to run a single DNN execution (i.e., inference) at Hardware Description Level (HDL), the injections are typically performed at software level. This is clearly important to provide an overall estimation of the DNN behavior in faulty scenarios, however, it might be not accurate enough if the reliability of the target HW architecture must be determined. In that case, you need to run the fault injections directly at a hardware description level. The intent of the paper is to present a pipelined multi-layer fault injector for Deep Neural Networks that is able to drastically reduce the fault simulation time at HDL. Mimicking the behavior of the pipeline of a processor core, it allows to drastically reduce the complete fault injection time to be run at hardware level, thereby reducing the required time by about 60%.
{"title":"A Pipelined Multi-Level Fault Injector for Deep Neural Networks","authors":"A. Ruospo, Angelo Balaara, A. Bosio, Ernesto Sánchez","doi":"10.1109/DFT50435.2020.9250866","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250866","url":null,"abstract":"Applications leveraging on new computing paradigms, such as brain-inspired computing, are currently being exploited in many fields thanks to their outstanding performance in solving complex tasks. Among them, Deep Neural Networks (DNNs) are gaining growing interest in different research areas spanning from playing complex games to safety-critical applications such as automotive. In the latter case, reliability assumes a dominant role and efficient reliability assessment approaches are thus required. Several works evaluate the DNN reliability by running fault injection campaigns. However, due to the excessive time required to run a single DNN execution (i.e., inference) at Hardware Description Level (HDL), the injections are typically performed at software level. This is clearly important to provide an overall estimation of the DNN behavior in faulty scenarios, however, it might be not accurate enough if the reliability of the target HW architecture must be determined. In that case, you need to run the fault injections directly at a hardware description level. The intent of the paper is to present a pipelined multi-layer fault injector for Deep Neural Networks that is able to drastically reduce the fault simulation time at HDL. Mimicking the behavior of the pipeline of a processor core, it allows to drastically reduce the complete fault injection time to be run at hardware level, thereby reducing the required time by about 60%.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"46 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113974104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250861
Dario Mamone, A. Bosio, A. Savino, S. Hamdioui, M. Rebaudengo
Nowadays, the reliability has become one of the main issues for safety-critical embedded systems, like automotive, aerospace and avionic. In an embedded system, the full system stack usually includes, between the hardware layer and the software/application layer, a middle layer composed by the Operating System (OS) and the middleware. Most of the time, in the literature only the application-layer is considered during the reliability analysis. This is due to the fact that middle layer short execution time makes the probability of a fault affecting it much lower compared to the application-level. Nevertheless, middle layer data structures lifespan is equivalent to the application layer ones. Moreover, all the times a hardware fault propagates to the middle-layer as an error, and especially to the OS, its impact can be expected to be potentially catastrophic. The aim of this work is to study the reliability of a Real-Time Operating System (RTOS) affected by Single Event Upset (SEU) faults. The methodology targets the most relevant variables and data structures of FreeRTOS analyzed through a software-based fault injection. Results show the ability to highlight the criticality in the OS fault tolerance, in terms of system integrity, data integrity and the overall inherent resiliency to faults, potentially leading to selective hardening of the OS.
{"title":"On the Analysis of Real-time Operating System Reliability in Embedded Systems","authors":"Dario Mamone, A. Bosio, A. Savino, S. Hamdioui, M. Rebaudengo","doi":"10.1109/DFT50435.2020.9250861","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250861","url":null,"abstract":"Nowadays, the reliability has become one of the main issues for safety-critical embedded systems, like automotive, aerospace and avionic. In an embedded system, the full system stack usually includes, between the hardware layer and the software/application layer, a middle layer composed by the Operating System (OS) and the middleware. Most of the time, in the literature only the application-layer is considered during the reliability analysis. This is due to the fact that middle layer short execution time makes the probability of a fault affecting it much lower compared to the application-level. Nevertheless, middle layer data structures lifespan is equivalent to the application layer ones. Moreover, all the times a hardware fault propagates to the middle-layer as an error, and especially to the OS, its impact can be expected to be potentially catastrophic. The aim of this work is to study the reliability of a Real-Time Operating System (RTOS) affected by Single Event Upset (SEU) faults. The methodology targets the most relevant variables and data structures of FreeRTOS analyzed through a software-based fault injection. Results show the ability to highlight the criticality in the OS fault tolerance, in terms of system integrity, data integrity and the overall inherent resiliency to faults, potentially leading to selective hardening of the OS.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250821
R. L. R. Junior, P. Rech
In this paper, we evaluate the impact on reliability and performance of the selective approximation of Convolutional Neural Networks (CNNs) layers on NVIDIA mixed-precision architectures. We found that, even without affecting accuracy, the approximation from single to half precision of each layer has a different impact on both performance and output error.
{"title":"Impact of Layers Selective Approximation on CNNs Reliability and Performance","authors":"R. L. R. Junior, P. Rech","doi":"10.1109/DFT50435.2020.9250821","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250821","url":null,"abstract":"In this paper, we evaluate the impact on reliability and performance of the selective approximation of Convolutional Neural Networks (CNNs) layers on NVIDIA mixed-precision architectures. We found that, even without affecting accuracy, the approximation from single to half precision of each layer has a different impact on both performance and output error.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125782509","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250908
G. Furano, A. Tavoularis, M. Rovatti
While AI is being successfully applied in space (e.g. in the areas of enhanced monitoring and diagnostics, in prediction, image analysis etc.), it is still not applied on-board.Many potential applications could benefit from AI on-board capabilities at different levels. Probably the most straightforward approach is the use of AI for remote sensing missions at payload processing level to perform image processing tasks. Nevertheless, other applications at instrument, satellite or system levels could also represent important breakthroughs in the way we use and operate satellites for any kind of mission.A possible way forward would be to train machine learning models on-ground, up-link the trained models and use them on-board. This would enable an increased level of autonomy (e.g. opportunistic science) and added-value on-board, for a little extra computational cost. Even the most computational intensive AI models (e.g. deep learning) have now versions that allow trained models to be run on smartphones (“on the edge”).
{"title":"AI in space: applications examples and challenges","authors":"G. Furano, A. Tavoularis, M. Rovatti","doi":"10.1109/DFT50435.2020.9250908","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250908","url":null,"abstract":"While AI is being successfully applied in space (e.g. in the areas of enhanced monitoring and diagnostics, in prediction, image analysis etc.), it is still not applied on-board.Many potential applications could benefit from AI on-board capabilities at different levels. Probably the most straightforward approach is the use of AI for remote sensing missions at payload processing level to perform image processing tasks. Nevertheless, other applications at instrument, satellite or system levels could also represent important breakthroughs in the way we use and operate satellites for any kind of mission.A possible way forward would be to train machine learning models on-ground, up-link the trained models and use them on-board. This would enable an increased level of autonomy (e.g. opportunistic science) and added-value on-board, for a little extra computational cost. Even the most computational intensive AI models (e.g. deep learning) have now versions that allow trained models to be run on smartphones (“on the edge”).","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"224 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130738527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250842
Nagabhushan Reddy, S. Menon, Prashant D. Joshi
Modern PC power management has evolved to provide Always On, Always Connected, and Instant Resume kind of experiences to the user, along with longer battery life. It enhances productivity and greatly improves the user experience and brings in a Mobile-like experience to the PC user. The connectivity to the system is maintained even during the standby, which keeps the data up-to-date and readily available, when the user resumes the system from standby. This modern behavior needs to be supported at both the Operating System and at the SoC level. On Windows, this is supported through the ‘Modern Standby’ feature followed by the ‘Active Idle’ feature supported by the SoC.Legacy Standby (S3) validation involved mostly checking the power, software and hardware status and the corresponding wake capabilities. Validating Modern Standby involves a lot of new methodologies and techniques such as Sleep Residency during standby, seamless transition between various Power Management states (avoiding system crashes and hangs), Instant Resume time and seamless connectivity during Modern Standby.This paper discusses the new validation methodologies established to accelerate the failure detection during these complex and error-prone use cases, and defines effective debug methodologies, thus enabling early fixing of these issues. The new validation methodologies include residency measurement techniques, verifying system stability during state transitions and measuring resume time from standby.
{"title":"Validation Challenges in Recent Trends of Power Management in Microprocessors","authors":"Nagabhushan Reddy, S. Menon, Prashant D. Joshi","doi":"10.1109/DFT50435.2020.9250842","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250842","url":null,"abstract":"Modern PC power management has evolved to provide Always On, Always Connected, and Instant Resume kind of experiences to the user, along with longer battery life. It enhances productivity and greatly improves the user experience and brings in a Mobile-like experience to the PC user. The connectivity to the system is maintained even during the standby, which keeps the data up-to-date and readily available, when the user resumes the system from standby. This modern behavior needs to be supported at both the Operating System and at the SoC level. On Windows, this is supported through the ‘Modern Standby’ feature followed by the ‘Active Idle’ feature supported by the SoC.Legacy Standby (S3) validation involved mostly checking the power, software and hardware status and the corresponding wake capabilities. Validating Modern Standby involves a lot of new methodologies and techniques such as Sleep Residency during standby, seamless transition between various Power Management states (avoiding system crashes and hangs), Instant Resume time and seamless connectivity during Modern Standby.This paper discusses the new validation methodologies established to accelerate the failure detection during these complex and error-prone use cases, and defines effective debug methodologies, thus enabling early fixing of these issues. The new validation methodologies include residency measurement techniques, verifying system stability during state transitions and measuring resume time from standby.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121391351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-10-19DOI: 10.1109/DFT50435.2020.9250878
Yiannakis Sazeides, A. Bramnik, Ron Gabor, C. Nicopoulos, R. Canal, Dimitris Konstantinou, G. Dimitrakopoulos
This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use in-line error-detection and correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper presents how to build RTD into an array with flip-flops to track in real-time the column-parity and introduces a two-dimensional RTD based error-correction scheme. As compared to SECDED, the evaluated scheme has comparable error-detection and correction strength and, depending on the array dimensions, the access time is reduced by 8–24% at an area and power overhead between 12–53% and 21–42% respectively.
{"title":"2D Error Correction for F/F based Arrays using In-Situ Real-Time Error Detection (RTD)","authors":"Yiannakis Sazeides, A. Bramnik, Ron Gabor, C. Nicopoulos, R. Canal, Dimitris Konstantinou, G. Dimitrakopoulos","doi":"10.1109/DFT50435.2020.9250878","DOIUrl":"https://doi.org/10.1109/DFT50435.2020.9250878","url":null,"abstract":"This work proposes in-situ Real-Time Error Detection (RTD): embedding hardware in a memory array for detecting a fault in the array when it occurs, rather than when it is read. RTD breaks the serialization between data access and error detection and, thus, it can speed-up the access-time of arrays that use in-line error-detection and correction. The approach can also reduce the time needed to root-cause array related bugs during post-silicon validation and product testing. The paper presents how to build RTD into an array with flip-flops to track in real-time the column-parity and introduces a two-dimensional RTD based error-correction scheme. As compared to SECDED, the evaluated scheme has comparable error-detection and correction strength and, depending on the array dimensions, the access time is reduced by 8–24% at an area and power overhead between 12–53% and 21–42% respectively.","PeriodicalId":340119,"journal":{"name":"2020 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-10-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128113485","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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