Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653959
Haris Javaid, A. Ignjatović, S. Parameswaran
Estimation models play a vital role in many aspects of day to day life. Extremely complex estimation models are employed in the design space exploration of SoCs, and the efficacy of these estimation models is usually measured by the absolute error of the models compared to known actual results. Such absolute error based metrics can often result in over-designed estimation models, with a number of researchers suggesting that fidelity of an estimation model (correlation between the ordering of the estimated points and the ordering of the actual points) should be examined instead of, or in addition to, the absolute error. In this paper, for the first time, we propose four metrics to measure the fidelity of an estimation model, in particular for use in design space exploration. The first two are based on two well known rank correlation coefficients. The other two are weighted versions of the first two metrics, to give importance to points nearer the Pareto front. The proposed fidelity metrics range from −1 to 1, where a value of 1 reflects a perfect positive correlation while a value of −1 reflects a perfect negative correlation. The proposed fidelity metrics were calculated for a single processor estimation model and a multiprocessor estimation model to observe their behavior, and were compared against the models' absolute error. For the multiprocessor estimation model, even though the worst average and maximum absolute error of 6.40% and 16.61% respectively can be considered reasonable in design automation, the worst fidelity of 0.753 suggests that the multiprocessor estimation model may not be as good a model (compared to an estimation model with same or higher absolute errors but a fidelity of 0.95) as depicted by its absolute accuracy, leading to an over-designed estimation model.
{"title":"Fidelity metrics for estimation models","authors":"Haris Javaid, A. Ignjatović, S. Parameswaran","doi":"10.1109/ICCAD.2010.5653959","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653959","url":null,"abstract":"Estimation models play a vital role in many aspects of day to day life. Extremely complex estimation models are employed in the design space exploration of SoCs, and the efficacy of these estimation models is usually measured by the absolute error of the models compared to known actual results. Such absolute error based metrics can often result in over-designed estimation models, with a number of researchers suggesting that fidelity of an estimation model (correlation between the ordering of the estimated points and the ordering of the actual points) should be examined instead of, or in addition to, the absolute error. In this paper, for the first time, we propose four metrics to measure the fidelity of an estimation model, in particular for use in design space exploration. The first two are based on two well known rank correlation coefficients. The other two are weighted versions of the first two metrics, to give importance to points nearer the Pareto front. The proposed fidelity metrics range from −1 to 1, where a value of 1 reflects a perfect positive correlation while a value of −1 reflects a perfect negative correlation. The proposed fidelity metrics were calculated for a single processor estimation model and a multiprocessor estimation model to observe their behavior, and were compared against the models' absolute error. For the multiprocessor estimation model, even though the worst average and maximum absolute error of 6.40% and 16.61% respectively can be considered reasonable in design automation, the worst fidelity of 0.753 suggests that the multiprocessor estimation model may not be as good a model (compared to an estimation model with same or higher absolute errors but a fidelity of 0.95) as depicted by its absolute accuracy, leading to an over-designed estimation model.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126983679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653852
Lu Wan, Deming Chen
Modern logic optimization tools tend to optimize circuits in a balanced way so that all primary outputs (POs) have similar delay close to the cycle time. However, certain POs will be exercised more frequently than the rest. Among these critical primary outputs, some may be stabilized very quickly by input vectors, even if their topological delays from primary inputs are very long. Knowing the dynamic behavior of a circuit can help optimize the most commonly activated paths and help engineers understand how resilient a PO is against dynamic environmental variations such as voltage fluctuations. In this paper, we describe a tool to analyze the dynamic behavior of a circuit utilizing probabilistic information. The techniques exploit the use of timed ternary decision diagrams (tTDD) to encode stabilization conditions for POs. To compute probabilities based on a tTDD, we propose false assignment pruning and random variable compaction to preserve probability calculation accuracy. To deal with the scalability issue, this paper proposes a new circuit partitioning heuristic to reduce the inaccuracy introduced by partitioning. Compared to the timed simulation results, our tool has a mean absolute error of 2.5% and a root mean square error of 5.3% on average for ISCAS-85 benchmarks. Compared to a state-of-the-art dynamic behavior analysis tool, our tool is on average 40x faster and can handle circuits that the previous tool cannot.
{"title":"Analysis of circuit dynamic behavior with timed ternary decision diagram","authors":"Lu Wan, Deming Chen","doi":"10.1109/ICCAD.2010.5653852","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653852","url":null,"abstract":"Modern logic optimization tools tend to optimize circuits in a balanced way so that all primary outputs (POs) have similar delay close to the cycle time. However, certain POs will be exercised more frequently than the rest. Among these critical primary outputs, some may be stabilized very quickly by input vectors, even if their topological delays from primary inputs are very long. Knowing the dynamic behavior of a circuit can help optimize the most commonly activated paths and help engineers understand how resilient a PO is against dynamic environmental variations such as voltage fluctuations. In this paper, we describe a tool to analyze the dynamic behavior of a circuit utilizing probabilistic information. The techniques exploit the use of timed ternary decision diagrams (tTDD) to encode stabilization conditions for POs. To compute probabilities based on a tTDD, we propose false assignment pruning and random variable compaction to preserve probability calculation accuracy. To deal with the scalability issue, this paper proposes a new circuit partitioning heuristic to reduce the inaccuracy introduced by partitioning. Compared to the timed simulation results, our tool has a mean absolute error of 2.5% and a root mean square error of 5.3% on average for ISCAS-85 benchmarks. Compared to a state-of-the-art dynamic behavior analysis tool, our tool is on average 40x faster and can handle circuits that the previous tool cannot.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126529941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654234
Yi-Lin Chuang, Gi-Joon Nam, C. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan
Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy information as a novel fence force in an analytical placement framework. Unlike a state-of-the-art routability-driven placer that simply removes net bounding boxes during placement, this paper utilizes two different optimization forces, the global fence force and the local spreading force, to determine the positions of both standard cells and macros. We utilize design-hierarchy information to determine block distributions globally, and locally we add additional spreading forces to preserve sufficient free space among blocks by a net-topology estimation. With the interactions between these two forces, our placer can well balance routability and wirelength. Experimental results show that our placer can achieve the best routability and routing time among all published works.
{"title":"Design-hierarchy aware mixed-size placement for routability optimization","authors":"Yi-Lin Chuang, Gi-Joon Nam, C. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan","doi":"10.1109/ICCAD.2010.5654234","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654234","url":null,"abstract":"Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy information as a novel fence force in an analytical placement framework. Unlike a state-of-the-art routability-driven placer that simply removes net bounding boxes during placement, this paper utilizes two different optimization forces, the global fence force and the local spreading force, to determine the positions of both standard cells and macros. We utilize design-hierarchy information to determine block distributions globally, and locally we add additional spreading forces to preserve sufficient free space among blocks by a net-topology estimation. With the interactions between these two forces, our placer can well balance routability and wirelength. Experimental results show that our placer can achieve the best routability and routing time among all published works.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121632441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653715
Tsung-Wei Huang, S. Yeh, Tsung-Yi Ho
Electrowetting-on-dielectric (EWOD) chips have emerged as the most widely used actuators for digital microfluidic (DMF) systems. These devices enable the electrical manipulation of microfluidics with various advantages such as low power consumption, flexibility, accuracy, and efficiency. In addressing the need for low-cost and practical fabrication, pin-count reduction has become a key problem to the large-scale integration of EWOD-chip designs. One of the major approaches, broadcast addressing, reduces the pin count by assigning a single control pin to multiple electrodes with mutually compatible control signals. Most previous studies utilize this addressing scheme by scheduling fluidic-level synthesis on pin-constrained chip arrays. However, the associated interconnect routing problem is still not provided in currently available DMF automations, and thus the broadcast-addressing scheme cannot be actually realized. In this paper, we present the first network-flow based pin-count aware routing algorithm for EWOD-chip designs with a broadcast electrode-addressing scheme. Our algorithm simultaneously takes pin-count reduction and wirelength minimization into consideration for higher integration and better design performance. Experimental results show the effectiveness and scalability of our algorithm on a set of real-life chip applications.
{"title":"A network-flow based pin-count aware routing algorithm for broadcast electrode-addressing EWOD chips","authors":"Tsung-Wei Huang, S. Yeh, Tsung-Yi Ho","doi":"10.1109/ICCAD.2010.5653715","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653715","url":null,"abstract":"Electrowetting-on-dielectric (EWOD) chips have emerged as the most widely used actuators for digital microfluidic (DMF) systems. These devices enable the electrical manipulation of microfluidics with various advantages such as low power consumption, flexibility, accuracy, and efficiency. In addressing the need for low-cost and practical fabrication, pin-count reduction has become a key problem to the large-scale integration of EWOD-chip designs. One of the major approaches, broadcast addressing, reduces the pin count by assigning a single control pin to multiple electrodes with mutually compatible control signals. Most previous studies utilize this addressing scheme by scheduling fluidic-level synthesis on pin-constrained chip arrays. However, the associated interconnect routing problem is still not provided in currently available DMF automations, and thus the broadcast-addressing scheme cannot be actually realized. In this paper, we present the first network-flow based pin-count aware routing algorithm for EWOD-chip designs with a broadcast electrode-addressing scheme. Our algorithm simultaneously takes pin-count reduction and wirelength minimization into consideration for higher integration and better design performance. Experimental results show the effectiveness and scalability of our algorithm on a set of real-life chip applications.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121685968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654344
Gregory Lucas, Deming Chen
With the move to deep submicron processes, the design-productivity gap has continued to widen for RTL-based design methodologies. High-level synthesis has been touted as a solution to the design-productivity gap by allowing designers to move up to a higher level of abstraction where they focus on the functionality of the circuit instead of the low level details. However, at the same time, the move to deep submicron processes has led to increased levels of process variation, which must be considered during synthesis so that the performance yield of the circuit meets design specifications. In this paper, we tackle the problem of performance yield optimization during the scheduling task of high-level synthesis. We formulate the problem of performance yield optimization for scheduling as an integer linear programming problem (ILP) and offer the following contributions: 1) a totally unimodular ILP formulation for performance yield maximization and 2) a variation-aware and layout-driven iterative algorithm for performance yield improvement. Experimental results show that we can obtain significant gain in performance yield compared to a state-of-the-art variation-aware high-level synthesis tool Fast Yield.
{"title":"Variation-aware layout-driven scheduling for performance yield optimization","authors":"Gregory Lucas, Deming Chen","doi":"10.1109/ICCAD.2010.5654344","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654344","url":null,"abstract":"With the move to deep submicron processes, the design-productivity gap has continued to widen for RTL-based design methodologies. High-level synthesis has been touted as a solution to the design-productivity gap by allowing designers to move up to a higher level of abstraction where they focus on the functionality of the circuit instead of the low level details. However, at the same time, the move to deep submicron processes has led to increased levels of process variation, which must be considered during synthesis so that the performance yield of the circuit meets design specifications. In this paper, we tackle the problem of performance yield optimization during the scheduling task of high-level synthesis. We formulate the problem of performance yield optimization for scheduling as an integer linear programming problem (ILP) and offer the following contributions: 1) a totally unimodular ILP formulation for performance yield maximization and 2) a variation-aware and layout-driven iterative algorithm for performance yield improvement. Experimental results show that we can obtain significant gain in performance yield compared to a state-of-the-art variation-aware high-level synthesis tool Fast Yield.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125469351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654214
Tan Yan, Pei-Ci Wu, Q. Ma, Martin D. F. Wong
As an important step in PCB design, the escape routing problem has been extensively studied in literature. However, few studies have been done on the escape routing of differential pairs. In this paper, we study the differential pair escape routing problem and propose two algorithms. The first one computes the optimal routing for a single differential pair while the second one is able to simultaneously route multiple differential pairs considering both routability and wire length. We then propose a two-stage routing scheme based on the two algorithms. Experimental results show that our routing scheme efficiently and effectively solves the differential pair escape routing test cases we obtained from industry.
{"title":"On the escape routing of differential pairs","authors":"Tan Yan, Pei-Ci Wu, Q. Ma, Martin D. F. Wong","doi":"10.1109/ICCAD.2010.5654214","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654214","url":null,"abstract":"As an important step in PCB design, the escape routing problem has been extensively studied in literature. However, few studies have been done on the escape routing of differential pairs. In this paper, we study the differential pair escape routing problem and propose two algorithms. The first one computes the optimal routing for a single differential pair while the second one is able to simultaneously route multiple differential pairs considering both routability and wire length. We then propose a two-stage routing scheme based on the two algorithms. Experimental results show that our routing scheme efficiently and effectively solves the differential pair escape routing test cases we obtained from industry.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115035207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654064
Karthick Parashar, D. Ménard, R. Rocher, O. Sentieys, D. Novo, F. Catthoor
Fixed-point refinement of signal processing systems is an essential step performed before implementation of any signal processing system. Existing analytical techniques to evaluate performance of fixed-point systems are not applicable to the errors due to quantization in the presence of un-smooth operators. Thus, it is inevitable to use simulation to evaluate performance of fixed-point systems in the presence un-smooth operators. This paper proposes a hybrid technique which can be used in place of pure simulation to accelerate the performance evaluation. The principle idea in the proposed hybrid approach is to selectively simulate parts of the system only when un-smooth errors occur but use analytical results otherwise. The acceleration thus obtained reduces the performance evaluation time which can be used to explore a wider word-length design space or speedup the optimization process. This method has been tried on a complex MIMO sphere decoding algorithm and the results obtained show several orders of magnitude improvement in terms of evaluation time.
{"title":"Fast performance evaluation of fixed-point systems with un-smooth operators","authors":"Karthick Parashar, D. Ménard, R. Rocher, O. Sentieys, D. Novo, F. Catthoor","doi":"10.1109/ICCAD.2010.5654064","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654064","url":null,"abstract":"Fixed-point refinement of signal processing systems is an essential step performed before implementation of any signal processing system. Existing analytical techniques to evaluate performance of fixed-point systems are not applicable to the errors due to quantization in the presence of un-smooth operators. Thus, it is inevitable to use simulation to evaluate performance of fixed-point systems in the presence un-smooth operators. This paper proposes a hybrid technique which can be used in place of pure simulation to accelerate the performance evaluation. The principle idea in the proposed hybrid approach is to selectively simulate parts of the system only when un-smooth errors occur but use analytical results otherwise. The acceleration thus obtained reduces the performance evaluation time which can be used to explore a wider word-length design space or speedup the optimization process. This method has been tried on a complex MIMO sphere decoding algorithm and the results obtained show several orders of magnitude improvement in terms of evaluation time.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114961228","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For high-performance chip designs, a clock network with high tolerance towards process-variation is essential for chip synchronization. Clock mesh structure are widely used in these designs because of its resistant to variations. However, traditional mesh structures suffer from several drawbacks such as difficulty in timing estimation, inability to handle obstacles, and high power consumption. This paper proposes a new obstacle-avoiding clock mesh synthesis method which applies a two-stage approach of mesh construction followed by driving-tree synthesis. The method achieves very low skew through structural optimization, thus eliminating the need of direct timing estimation and/or SPICE simulation during clock network synthesis. In addition, our approach handles obstacles with the structural consideration, and reduces power consumption by removing non-critical mesh components and optimizing the driving-tree structure. Based on the benchmarks of the ISPD'10 Clock Network Synthesis Contest, the top contest performers result in 1.32X skew over our approach by using mesh structure, and more than 2.0X skew over our approach by using tree structure. Our approach runs 8326X/11421X faster than teams that used simulation, and 67X/90X times faster than teams that did not use simulation.
{"title":"High variation-tolerant obstacle-avoiding clock mesh synthesis with symmetrical driving trees","authors":"Xin-Wei Shih, Hsu-Chieh Lee, Kuan-Hsien Ho, Yao-Wen Chang","doi":"10.1109/ICCAD.2010.5653754","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653754","url":null,"abstract":"For high-performance chip designs, a clock network with high tolerance towards process-variation is essential for chip synchronization. Clock mesh structure are widely used in these designs because of its resistant to variations. However, traditional mesh structures suffer from several drawbacks such as difficulty in timing estimation, inability to handle obstacles, and high power consumption. This paper proposes a new obstacle-avoiding clock mesh synthesis method which applies a two-stage approach of mesh construction followed by driving-tree synthesis. The method achieves very low skew through structural optimization, thus eliminating the need of direct timing estimation and/or SPICE simulation during clock network synthesis. In addition, our approach handles obstacles with the structural consideration, and reduces power consumption by removing non-critical mesh components and optimizing the driving-tree structure. Based on the benchmarks of the ISPD'10 Clock Network Synthesis Contest, the top contest performers result in 1.32X skew over our approach by using mesh structure, and more than 2.0X skew over our approach by using tree structure. Our approach runs 8326X/11421X faster than teams that used simulation, and 67X/90X times faster than teams that did not use simulation.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129898205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654349
Wangyang Zhang, Xin Li, E. Acar, Frank Liu, Rob A. Rutenbar
In this paper, we propose a new technique, referred to as Multi-Wafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian inference is derived to extract a shared model template to explore the wafer-to-wafer correlation information within the same lot. In addition, a robust regression algorithm is proposed to automatically detect and remove outliers (i.e., abnormal measurement data with large error) so that they do not bias the modeling results. The proposed MVP method is extensively tested for silicon measurement data collected from 200 wafers at an advanced technology node. Our experimental results demonstrate that MVP offers superior accuracy over other traditional approaches such as VP [7] and EM [8], if a limited number of measurement data are available.
{"title":"Multi-Wafer Virtual Probe: Minimum-cost variation characterization by exploring wafer-to-wafer correlation","authors":"Wangyang Zhang, Xin Li, E. Acar, Frank Liu, Rob A. Rutenbar","doi":"10.1109/ICCAD.2010.5654349","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654349","url":null,"abstract":"In this paper, we propose a new technique, referred to as Multi-Wafer Virtual Probe (MVP) to efficiently model wafer-level spatial variations for nanoscale integrated circuits. Towards this goal, a novel Bayesian inference is derived to extract a shared model template to explore the wafer-to-wafer correlation information within the same lot. In addition, a robust regression algorithm is proposed to automatically detect and remove outliers (i.e., abnormal measurement data with large error) so that they do not bias the modeling results. The proposed MVP method is extensively tested for silicon measurement data collected from 200 wafers at an advanced technology node. Our experimental results demonstrate that MVP offers superior accuracy over other traditional approaches such as VP [7] and EM [8], if a limited number of measurement data are available.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133225106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653648
Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang
Spare cells are often used in engineering change order (ECO) timing optimization. By applying spare-cell rewiring techniques, timing-violated paths in a design can be fixed. In addition, mask re-spin cost economization has become a critical challenge for modern IC design, and it can be achieved by reducing the number of layers used to rewire spare cells. This paper presents the first work for the problem of ECO timing optimization considering redundant wires (unused wires or dummy metals) to minimize the number of rewiring layers. We first propose a multi-commodity flow model for the spare-cell selection problem and apply integer linear programming (ILP) to simultaneously optimize all timing-violated paths. The ILP formulation minimizes the number of used spare cells and considers the routability of the selected spare cells. Then, we develop a tile-based ECO router which minimizes the number of rewiring layers by reusing redundant wires. Experimental results based on five industry benchmarks show that our algorithm not only effectively resolves timing violations but also reduces the number of rewiring layers under reasonable runtime.
{"title":"Redundant-wires-aware ECO timing and mask cost optimization","authors":"Shao-Yun Fang, Tzuo-Fan Chien, Yao-Wen Chang","doi":"10.1109/ICCAD.2010.5653648","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653648","url":null,"abstract":"Spare cells are often used in engineering change order (ECO) timing optimization. By applying spare-cell rewiring techniques, timing-violated paths in a design can be fixed. In addition, mask re-spin cost economization has become a critical challenge for modern IC design, and it can be achieved by reducing the number of layers used to rewire spare cells. This paper presents the first work for the problem of ECO timing optimization considering redundant wires (unused wires or dummy metals) to minimize the number of rewiring layers. We first propose a multi-commodity flow model for the spare-cell selection problem and apply integer linear programming (ILP) to simultaneously optimize all timing-violated paths. The ILP formulation minimizes the number of used spare cells and considers the routability of the selected spare cells. Then, we develop a tile-based ECO router which minimizes the number of rewiring layers by reusing redundant wires. Experimental results based on five industry benchmarks show that our algorithm not only effectively resolves timing violations but also reduces the number of rewiring layers under reasonable runtime.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134621123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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