Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653788
Andrea Pellegrini, V. Bertacco
Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Current online testing mechanisms focus on testing all components in a microprocessor, including hardware that has not been exercised, and thus have high performance penalties. We propose a hybrid hardware/software online testing solution where components that are heavily utilized by the software application are tested more thoroughly and frequently. Thus, our online testing approach focuses on the processor units that affect application correctness the most, and it achieves high coverage while incurring minimal performance overhead. We also introduce a new metric, Application-Aware Fault Coverage, measuring a test's capability to detect faults that might have corrupted the state or the output of an application. Test coverage is further improved through the insertion of observation points that augment the coverage of the testing system. By evaluating our technique on a Sun OpenSPARC T1, we show that our solution maintains high Application-Aware Fault Coverage while reducing the performance overhead of online testing by more than a factor of 2 when compared to solutions oblivious to application's behavior. Specifically, we found that our solution can achieve 95% fault coverage while maintaining a minimal performance overhead (1.3%) and area impact (0.4%).
{"title":"Application-Aware diagnosis of runtime hardware faults","authors":"Andrea Pellegrini, V. Bertacco","doi":"10.1109/ICCAD.2010.5653788","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653788","url":null,"abstract":"Extreme technology scaling in silicon devices drastically affects reliability, particularly because of runtime failures induced by transistor wearout. Current online testing mechanisms focus on testing all components in a microprocessor, including hardware that has not been exercised, and thus have high performance penalties. We propose a hybrid hardware/software online testing solution where components that are heavily utilized by the software application are tested more thoroughly and frequently. Thus, our online testing approach focuses on the processor units that affect application correctness the most, and it achieves high coverage while incurring minimal performance overhead. We also introduce a new metric, Application-Aware Fault Coverage, measuring a test's capability to detect faults that might have corrupted the state or the output of an application. Test coverage is further improved through the insertion of observation points that augment the coverage of the testing system. By evaluating our technique on a Sun OpenSPARC T1, we show that our solution maintains high Application-Aware Fault Coverage while reducing the performance overhead of online testing by more than a factor of 2 when compared to solutions oblivious to application's behavior. Specifically, we found that our solution can achieve 95% fault coverage while maintaining a minimal performance overhead (1.3%) and area impact (0.4%).","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114173434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The past several years have witnessed a significant interest in developing parallel CAD algorithms and implementations that exploit various multi-core and distributed computing hardware. In addition to fundamental parallel algorithm design, the ability in modeling parallel performance and facilitating runtime optimization is indispensable for achieving good efficiency for complex parallel CAD applications. Under the context of a recently developed hierarchical multi-algorithm parallel circuit simulation (HMAPS) framework, we demonstrate a runtime optimization approach that allows for automatic on-the-fly reconfiguration of the parallel simulation code. We show how the runtime information, collected as parallel simulation proceeds, can be combined with static parallel performance models to enable dynamic adaptation of parallel simulation execution for improved performance and robustness. Our results have shown that the proposed approach not only finds the near-optimal code configuration over a large configuration space, it also outperforms multi-algorithm circuit simulation assisted only with static pre-runtime parallel performance modeling.
{"title":"On-the-fly runtime adaptation for efficient execution of parallel multi-algorithm circuit simulation","authors":"Xiaoji Ye, Peng Li","doi":"10.5555/2133429.2133492","DOIUrl":"https://doi.org/10.5555/2133429.2133492","url":null,"abstract":"The past several years have witnessed a significant interest in developing parallel CAD algorithms and implementations that exploit various multi-core and distributed computing hardware. In addition to fundamental parallel algorithm design, the ability in modeling parallel performance and facilitating runtime optimization is indispensable for achieving good efficiency for complex parallel CAD applications. Under the context of a recently developed hierarchical multi-algorithm parallel circuit simulation (HMAPS) framework, we demonstrate a runtime optimization approach that allows for automatic on-the-fly reconfiguration of the parallel simulation code. We show how the runtime information, collected as parallel simulation proceeds, can be combined with static parallel performance models to enable dynamic adaptation of parallel simulation execution for improved performance and robustness. Our results have shown that the proposed approach not only finds the near-optimal code configuration over a large configuration space, it also outperforms multi-algorithm circuit simulation assisted only with static pre-runtime parallel performance modeling.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"746 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122963647","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654224
Hao Xu, R. Vemuri, W. Jone
Power gating has been widely adopted in multicore designs. The design of fast and reliable power mode transition for per-core power gating remains a challenging problem. This paper studies the design methodology for fast power gating wake-up with guaranteed power integrity. Two novel techniques, namely current shaping and multi-thread activation are proposed. Models and physical implementation of both techniques are analyzed. Experimental results demonstrated 1.5 to 11 times wake-up time speedup with no penalty on area or power consumptions by using the proposed techniques.
{"title":"Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs","authors":"Hao Xu, R. Vemuri, W. Jone","doi":"10.1109/ICCAD.2010.5654224","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654224","url":null,"abstract":"Power gating has been widely adopted in multicore designs. The design of fast and reliable power mode transition for per-core power gating remains a challenging problem. This paper studies the design methodology for fast power gating wake-up with guaranteed power integrity. Two novel techniques, namely current shaping and multi-thread activation are proposed. Models and physical implementation of both techniques are analyzed. Experimental results demonstrated 1.5 to 11 times wake-up time speedup with no penalty on area or power consumptions by using the proposed techniques.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129830693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654174
Chenjie Gu, J. Roychowdhury
We extend the concept of timing/phase macromodels, previously established rigorously only for oscillators, to apply to general systems, both non-oscillatory and oscillatory. We do so by first establishing a solid foundation for the timing/phase response of any nonlinear dynamical system, then deriving a timing/phase macromodel via nonlinear perturbation analysis. The macromodel that emerges is a scalar, nonlinear time-varying equation that accurately characterizes the system's phase/timing responses. We establish strong links of this technique with projection frameworks for model order reduction. We then present numerical methods to compute the phase model. The computation involves a full Floquet decomposition — we discuss numerical issues that arise if direct computation of the monodromy matrix is used for Floquet analysis, and propose an alternative method that are numerically superior. The new method has elegant connections to the Jacobian matrix in harmonic balance method (readily available in most RF simulators). We validate the technique on several highly nonlinear systems, including an inverter chain and a firing neuron. We demonstrate that the new scalar nonlinear phase model captures phase responses under various types of input perturbations, achieving accuracies considerably superior to those of reduced models obtained using LTI/LPTV MOR methods. Thus, we establish a powerful new way to extract timing models of combinatorial/sequential systems and memory (e.g., SRAMs/DRAMs), synchronization systems based on oscillator enslaving (e.g., PLLs, injection-locked oscillators, CDR systems, neural processing, energy grids), signal-processing blocks (e.g., ADCs/DACs, FIR/IIR filters), etc.
{"title":"Generalized nonlinear timing/phase macromodeling: Theory, numerical methods and applications","authors":"Chenjie Gu, J. Roychowdhury","doi":"10.1109/ICCAD.2010.5654174","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654174","url":null,"abstract":"We extend the concept of timing/phase macromodels, previously established rigorously only for oscillators, to apply to general systems, both non-oscillatory and oscillatory. We do so by first establishing a solid foundation for the timing/phase response of any nonlinear dynamical system, then deriving a timing/phase macromodel via nonlinear perturbation analysis. The macromodel that emerges is a scalar, nonlinear time-varying equation that accurately characterizes the system's phase/timing responses. We establish strong links of this technique with projection frameworks for model order reduction. We then present numerical methods to compute the phase model. The computation involves a full Floquet decomposition — we discuss numerical issues that arise if direct computation of the monodromy matrix is used for Floquet analysis, and propose an alternative method that are numerically superior. The new method has elegant connections to the Jacobian matrix in harmonic balance method (readily available in most RF simulators). We validate the technique on several highly nonlinear systems, including an inverter chain and a firing neuron. We demonstrate that the new scalar nonlinear phase model captures phase responses under various types of input perturbations, achieving accuracies considerably superior to those of reduced models obtained using LTI/LPTV MOR methods. Thus, we establish a powerful new way to extract timing models of combinatorial/sequential systems and memory (e.g., SRAMs/DRAMs), synchronization systems based on oscillator enslaving (e.g., PLLs, injection-locked oscillators, CDR systems, neural processing, energy grids), signal-processing blocks (e.g., ADCs/DACs, FIR/IIR filters), etc.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127414019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Oscillations and rhythmic activity are seen in natural and man-made systems. Dynamics of oscillators can be compactly described by phase domain models. Phase equations for periodic, single-frequency oscillators have been developed and utilized in analyzing oscillation phenomena that arise in electronic systems, circadian clocks, and the nervous system. We consider quasi-periodic oscillators and present a general phase model theory and numerical techniques for the construction of phase equations for multi-frequency oscillators. We demonstrate the utility of these phase equations in analyzing oscillators experiencing perturbations.
{"title":"Phase equations for quasi-periodic oscillators","authors":"A. Demir, Chenjie Gu, J. Roychowdhury","doi":"10.5555/2133429.2133491","DOIUrl":"https://doi.org/10.5555/2133429.2133491","url":null,"abstract":"Oscillations and rhythmic activity are seen in natural and man-made systems. Dynamics of oscillators can be compactly described by phase domain models. Phase equations for periodic, single-frequency oscillators have been developed and utilized in analyzing oscillation phenomena that arise in electronic systems, circadian clocks, and the nervous system. We consider quasi-periodic oscillators and present a general phase model theory and numerical techniques for the construction of phase equations for multi-frequency oscillators. We demonstrate the utility of these phase equations in analyzing oscillators experiencing perturbations.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128460849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power grid voltage integrity verification requires one to check if all the voltage drops on the grid are less than a certain threshold. This paper addresses the problem of correcting the grid when some voltage drops exceed this threshold, by making minor modifications to the existing design. The method uses current constraints that capture the uncertainty about the underlying circuit behavior to find the maximum voltage drop on the grid, and then to estimate the voltage drop as a function of the metal widths on the grid. It formulates a non-linear optimization problem and finds the required change in widths that reduces the maximum voltage drop below the threshold while keeping the total area cost at a minimum.
{"title":"Power grid correction using sensitivity analysis","authors":"Meric Aydonat, F. Najm","doi":"10.5555/2133429.2133598","DOIUrl":"https://doi.org/10.5555/2133429.2133598","url":null,"abstract":"Power grid voltage integrity verification requires one to check if all the voltage drops on the grid are less than a certain threshold. This paper addresses the problem of correcting the grid when some voltage drops exceed this threshold, by making minor modifications to the existing design. The method uses current constraints that capture the uncertainty about the underlying circuit behavior to find the maximum voltage drop on the grid, and then to estimate the voltage drop as a function of the metal widths on the grid. It formulates a non-linear optimization problem and finds the required change in widths that reduces the maximum voltage drop below the threshold while keeping the total area cost at a minimum.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123011441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654165
H. Stratigopoulos, S. Mir
The high cost of analog circuit testing has sparked off intensified efforts to identify robust and low-cost alternative tests that could effectively replace the standard specification-based tests. Nevertheless, the current practice is still specification-based testing. One of the primary reasons is the lack of tools to evaluate in advance the indirect costs (e.g. parametric test escape and yield loss) associated with alternative tests. To this end, in this paper, we present a method to estimate test escape and yield loss that occur as a result of replacing one costly specification test by one low-cost alternative test. This evaluation is performed at the design or test development stage with parts per million (PPM) accuracy. The method is based on extreme value theory and on a fast simulation technique of extreme events called statistical blockade.
{"title":"Analog test metrics estimates with PPM accuracy","authors":"H. Stratigopoulos, S. Mir","doi":"10.1109/ICCAD.2010.5654165","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654165","url":null,"abstract":"The high cost of analog circuit testing has sparked off intensified efforts to identify robust and low-cost alternative tests that could effectively replace the standard specification-based tests. Nevertheless, the current practice is still specification-based testing. One of the primary reasons is the lack of tools to evaluate in advance the indirect costs (e.g. parametric test escape and yield loss) associated with alternative tests. To this end, in this paper, we present a method to estimate test escape and yield loss that occur as a result of replacing one costly specification test by one low-cost alternative test. This evaluation is performed at the design or test development stage with parts per million (PPM) accuracy. The method is based on extreme value theory and on a fast simulation technique of extreme events called statistical blockade.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128521786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653703
M. Pathak, Young-Joon Lee, Thomas Moon, S. Lim
In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger area than regular gates. In this paper, we address two critical aspects of TSV management in 3D designs. First, we address the problem of how many TSVs to add in a design. Since TSVs occupy significant silicon area, a general tendency has been to use a minimum number of TSVs in 3D circuits. We show that such an approach does not give us the best possible result. Second, we address the problem of TSV insertion. Because TSVs occupy silicon area, their location is decided during the placement stage of 3D design. However, we show that this is not the best possible stage for TSV insertion. We propose a change in the physical design flow for 3D integrated circuits to address the limitations of existing TSV placement methodology. All our algorithms are integrated with commercial tools, and our results are validated based on actual GDSII layouts. Our experimental results show the effectiveness of our methods.
{"title":"Through-silicon-via management during 3D physical design: When to add and how many?","authors":"M. Pathak, Young-Joon Lee, Thomas Moon, S. Lim","doi":"10.1109/ICCAD.2010.5653703","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653703","url":null,"abstract":"In 3D integrated circuits through silicon vias (TSVs) are used to connect different dies stacked on top of each other. These TSV occupy silicon area and have significantly larger area than regular gates. In this paper, we address two critical aspects of TSV management in 3D designs. First, we address the problem of how many TSVs to add in a design. Since TSVs occupy significant silicon area, a general tendency has been to use a minimum number of TSVs in 3D circuits. We show that such an approach does not give us the best possible result. Second, we address the problem of TSV insertion. Because TSVs occupy silicon area, their location is decided during the placement stage of 3D design. However, we show that this is not the best possible stage for TSV insertion. We propose a change in the physical design flow for 3D integrated circuits to address the limitations of existing TSV placement methodology. All our algorithms are integrated with commercial tools, and our results are validated based on actual GDSII layouts. Our experimental results show the effectiveness of our methods.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116017744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654260
S. H. Rasouli, K. Endo, K. Banerjee
This paper, for the first time, shows that the work-function variation (WFV) in emerging metal-gate devices results in significant fluctuation in the gate-oxide electric field, and hence fluctuation in bias temperature instability (BTI) characteristics (both NBTI and PBTI). We modify the existing NBTI and PBTI models in order to accurately characterize the BTI characteristics of the metal-gate devices. It is shown that the impact of the oxide electric field on threshold voltage degradation is substantially underestimated if WFV is neglected. Moreover, in FinFET devices, work-function variation induced electric field (which is independent of the gate-source bias) not only results in fluctuation in the BTI characteristics, but also causes variation in the recovery process. It is highlighted for the first time that WFV induced BTI fluctuation can have significant impact on the performance and reliability characteristics of digital circuits such as SRAM cells and Domino logic gates.
{"title":"Work-function variation induced fluctuation in bias-temperature-instability characteristics of emerging metal-gate devices and implications for digital design","authors":"S. H. Rasouli, K. Endo, K. Banerjee","doi":"10.1109/ICCAD.2010.5654260","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654260","url":null,"abstract":"This paper, for the first time, shows that the work-function variation (WFV) in emerging metal-gate devices results in significant fluctuation in the gate-oxide electric field, and hence fluctuation in bias temperature instability (BTI) characteristics (both NBTI and PBTI). We modify the existing NBTI and PBTI models in order to accurately characterize the BTI characteristics of the metal-gate devices. It is shown that the impact of the oxide electric field on threshold voltage degradation is substantially underestimated if WFV is neglected. Moreover, in FinFET devices, work-function variation induced electric field (which is independent of the gate-source bias) not only results in fluctuation in the BTI characteristics, but also causes variation in the recovery process. It is highlighted for the first time that WFV induced BTI fluctuation can have significant impact on the performance and reliability characteristics of digital circuits such as SRAM cells and Domino logic gates.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125686822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Power consumption has become one of the major concerns in today's integrated circuit design, and especially in System-on-Chip development where numerous heterogeneous functions are integrated in a single chip. In this context system architects have the challenge to identify power issues very early in the design flow from a complex set of use scenarios. This paper explains how to achieve this challenge through the deployment of a modeling framework that enables low power technique exploration. The principle that sustains the framework is first introduced. A description of some of the power saving techniques that can be supported together with a presentation of the modeling data then follows. A few examples finally show the results a system designer can expect using the framework.
{"title":"ESL solutions for low power design","authors":"Sylvian Kaiser, Ilija Materic, Rabih Saade","doi":"10.5555/2133429.2133501","DOIUrl":"https://doi.org/10.5555/2133429.2133501","url":null,"abstract":"Power consumption has become one of the major concerns in today's integrated circuit design, and especially in System-on-Chip development where numerous heterogeneous functions are integrated in a single chip. In this context system architects have the challenge to identify power issues very early in the design flow from a complex set of use scenarios. This paper explains how to achieve this challenge through the deployment of a modeling framework that enables low power technique exploration. The principle that sustains the framework is first introduced. A description of some of the power saving techniques that can be supported together with a presentation of the modeling data then follows. A few examples finally show the results a system designer can expect using the framework.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126836572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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