Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654341
Shayak Banerjee, K. Agarwal, M. Orshansky
Low-k1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower level metals used for local routing, where bi-directionality gives rise to lithography unfriendly layout patterns. However, one can modify such wires without significantly affecting design behavior. In this paper, we propose to simultaneously modify mask and target during OPC to improve lithographic yield. The method uses image slope information, available during image simulation at no extra cost, as a measure of process window. We derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We then develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample metal1 (M1) layouts show that the use of SMATO reduces the Process Manufacturability Index (PMI) [18] by 15.4% compared to OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared to PWOPC, we observe 4.6% improvement in PMI at large (2.6X) improvement in runtime.
{"title":"SMATO: Simultaneous mask and target optimization for improving lithographic process window","authors":"Shayak Banerjee, K. Agarwal, M. Orshansky","doi":"10.1109/ICCAD.2010.5654341","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654341","url":null,"abstract":"Low-k1 lithography results in features that suffer from poor lithographic yield in the presence of process variation. The problem is especially pronounced for lower level metals used for local routing, where bi-directionality gives rise to lithography unfriendly layout patterns. However, one can modify such wires without significantly affecting design behavior. In this paper, we propose to simultaneously modify mask and target during OPC to improve lithographic yield. The method uses image slope information, available during image simulation at no extra cost, as a measure of process window. We derive a cost function that maximizes both contour fidelity and robustness to drive our simultaneous mask and target optimization (SMATO) method. We then develop analytical equations to predict the cost for a given mask and target modification and use a fast algorithm to minimize this cost function to obtain an optimal mask and target solution. Our experiments on sample metal1 (M1) layouts show that the use of SMATO reduces the Process Manufacturability Index (PMI) [18] by 15.4% compared to OPC, which further leads to 69% reduction in the number of layout hotspots. Additionally, such improvement is obtained at low average runtime overhead (5.5%). Compared to PWOPC, we observe 4.6% improvement in PMI at large (2.6X) improvement in runtime.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114643261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654190
Tan Yan, Martin D. F. Wong
The increasing complexity of electronic systems has made PCB layout a difficult problem. A large amount of research efforts are dedicated to the study of this problem. In this paper, we provide an overview of recent research results on the PCB layout problem. We focus on the escape routing problem and the length-matching routing problem, which are the two most important problems in PCB layout. Other relevant works are also briefly introduced.
{"title":"Recent research development in PCB layout","authors":"Tan Yan, Martin D. F. Wong","doi":"10.1109/ICCAD.2010.5654190","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654190","url":null,"abstract":"The increasing complexity of electronic systems has made PCB layout a difficult problem. A large amount of research efforts are dedicated to the study of this problem. In this paper, we provide an overview of recent research results on the PCB layout problem. We focus on the escape routing problem and the length-matching routing problem, which are the two most important problems in PCB layout. Other relevant works are also briefly introduced.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120995511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654275
Chun Zhang, Yu Hu, Lingli Wang, Lei He, J. Tong
Software as a Service (SaaS) 1.0 signifcantly lowers the infrastructure and maintenance cost and increases the accessibility of the software by hosting software via the web. Compared with SaaS 1.0, SaaS 2.0 is more flexible since it leverages software tools from both server and client sides with closer interaction between them. The SaaS 2.0 paradigm provides new opportunities and challenges for EDA. In this paper, we take Boolean matching, one of the core sub algorithms in logic synthesis for field programmable gate arrays (FPGAs), as a case study. We investigate the advantages and challenges of implementing a scalable EDA algorithm under SaaS 2.0 paradigm from a technical perspective. We propose SaaS-BM, a new Boolean matching algorithm customized to take full advantage of the cloud while addressing concerns such as security and the internet bandwidth limit. Extensive experiments are performed under a networked environment with concurrent accesses. Integrated into a post-mapping re-synthesis algorithm minimizing area, the proposed SaaS-BM is 863X times faster than state-of-the-art SAT-based Boolean matching with 0.5% area overhead. Compared with a recent Bloom Filter-based Boolean matching algorithm, our proposed SaaS-BM is 53X times faster on large circuits with no area overhead.
{"title":"Engineering a scalable Boolean matching based on EDA SaaS 2.0","authors":"Chun Zhang, Yu Hu, Lingli Wang, Lei He, J. Tong","doi":"10.1109/ICCAD.2010.5654275","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654275","url":null,"abstract":"Software as a Service (SaaS) 1.0 signifcantly lowers the infrastructure and maintenance cost and increases the accessibility of the software by hosting software via the web. Compared with SaaS 1.0, SaaS 2.0 is more flexible since it leverages software tools from both server and client sides with closer interaction between them. The SaaS 2.0 paradigm provides new opportunities and challenges for EDA. In this paper, we take Boolean matching, one of the core sub algorithms in logic synthesis for field programmable gate arrays (FPGAs), as a case study. We investigate the advantages and challenges of implementing a scalable EDA algorithm under SaaS 2.0 paradigm from a technical perspective. We propose SaaS-BM, a new Boolean matching algorithm customized to take full advantage of the cloud while addressing concerns such as security and the internet bandwidth limit. Extensive experiments are performed under a networked environment with concurrent accesses. Integrated into a post-mapping re-synthesis algorithm minimizing area, the proposed SaaS-BM is 863X times faster than state-of-the-art SAT-based Boolean matching with 0.5% area overhead. Compared with a recent Bloom Filter-based Boolean matching algorithm, our proposed SaaS-BM is 53X times faster on large circuits with no area overhead.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125130944","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5651402
Amandeep Singh, Peng Li
This paper presents a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as PLLs, ADCs and I/O's. We verify the equivalence between a behavioral model and its electrical implementation over a limited, but highly likely, input space defined as the Constrained Behavioral Input Space. Further, we clearly distinguish between the behavioral and electrical domains and define mappings between the two domains to allow for calculation of deviation between the behavioral and electrical implementation. The verification problem is then formulated as an optimization problem which is solved by interfacing a SQP based optimizer with commercial circuit simulation tools. The proposed methodology is then applied for equivalence checking of a PLL as a test case.
{"title":"On behavioral model equivalence checking for large analog/mixed signal systems","authors":"Amandeep Singh, Peng Li","doi":"10.1109/ICCAD.2010.5651402","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5651402","url":null,"abstract":"This paper presents a systematic, hierarchical, optimization based semi-formal equivalence checking methodology for large analog/mixed signal systems such as PLLs, ADCs and I/O's. We verify the equivalence between a behavioral model and its electrical implementation over a limited, but highly likely, input space defined as the Constrained Behavioral Input Space. Further, we clearly distinguish between the behavioral and electrical domains and define mappings between the two domains to allow for calculation of deviation between the behavioral and electrical implementation. The verification problem is then formulated as an optimization problem which is solved by interfacing a SQP based optimizer with commercial circuit simulation tools. The proposed methodology is then applied for equivalence checking of a PLL as a test case.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122361780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5654134
M. Glaß, M. Lukasiewycz, Felix Reimann, C. Haubelt, J. Teich
More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such complex systems in terms of monetary costs, power consumption, reliability etc. demands for new analysis approaches at the electronic system level. In this paper, two symbolic system level reliability analysis approaches are introduced. First, a formal approach based on Binary Decision Diagrams is presented that allows to calculate exact reliability measures for small to moderate-sized systems. Second, a simulative approach is presented that hybridizes a Monte Carlo simulation with a SAT solver and delivers adequate approximations of the reliability measures for large and complex systems.
{"title":"Symbolic system level reliability analysis","authors":"M. Glaß, M. Lukasiewycz, Felix Reimann, C. Haubelt, J. Teich","doi":"10.1109/ICCAD.2010.5654134","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5654134","url":null,"abstract":"More and more embedded systems provide a multitude of services, implemented by a large number of networked hardware components. In early design phases, dimensioning such complex systems in terms of monetary costs, power consumption, reliability etc. demands for new analysis approaches at the electronic system level. In this paper, two symbolic system level reliability analysis approaches are introduced. First, a formal approach based on Binary Decision Diagrams is presented that allows to calculate exact reliability measures for small to moderate-sized systems. Second, a simulative approach is presented that hybridizes a Monte Carlo simulation with a SAT solver and delivers adequate approximations of the reliability measures for large and complex systems.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122140919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K. Parhi
We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstrate how to synthesize biomolecular reactions that produce time-varying output quantities of molecules as a function of time-varying input quantities. Unlike all previous schemes for biomolecular computation, ours produces designs that are dependent only on coarse rate categories for the reactions (“fast” and “slow”). Given such categories, the computation is exact and independent of the specific reaction rates. We implement DSP operations through a self-timed “handshaking” protocol that transfers quantities between molecular types based on the absence of other types. We illustrate our methodology with the design of a simple moving-average filter as well as a more complex biquad filter. We validate our designs through transient stochastic simulations of the chemical kinetics. Although conceptual for the time being, the proposed methodology has potential applications in domains of synthetic biology such as biochemical sensing and drug delivery. We are exploring DNA-based computation via strand displacement as a possible experimental chassis.
{"title":"A synthesis flow for digital signal processing with biomolecular reactions","authors":"Hua Jiang, Aleksandra P. Kharam, Marc D. Riedel, K. Parhi","doi":"10.5555/2133429.2133518","DOIUrl":"https://doi.org/10.5555/2133429.2133518","url":null,"abstract":"We present a methodology for implementing digital signal processing (DSP) operations such as filtering with biomolecular reactions. From a DSP specification, we demonstrate how to synthesize biomolecular reactions that produce time-varying output quantities of molecules as a function of time-varying input quantities. Unlike all previous schemes for biomolecular computation, ours produces designs that are dependent only on coarse rate categories for the reactions (“fast” and “slow”). Given such categories, the computation is exact and independent of the specific reaction rates. We implement DSP operations through a self-timed “handshaking” protocol that transfers quantities between molecular types based on the absence of other types. We illustrate our methodology with the design of a simple moving-average filter as well as a more complex biquad filter. We validate our designs through transient stochastic simulations of the chemical kinetics. Although conceptual for the time being, the proposed methodology has potential applications in domains of synthetic biology such as biochemical sensing and drug delivery. We are exploring DNA-based computation via strand displacement as a possible experimental chassis.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"301 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128622487","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653885
Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, G. Pang, N. Wong
Passivity is a crucial property of macromodels to guarantee stable global (interconnected) simulation. However, weakly nonpassive models may be generated for passive circuits and systems in various contexts, such as data fitting, model order reduction (MOR) and electromagnetic (EM) macromodeling. Therefore, a post-processing passivity enforcement algorithm is desired. Most existing algorithms are designed to handle pole-residue models. The few algorithms for state space models only handle regular systems (RSs) with a nonsingular D+DT term. To the authors' best knowledge, no algorithm has been proposed to enforce passivity for more general descriptor systems (DSs) and state space models with singular D+DT terms. In this paper, a new post-processing passivity enforcement algorithm based on perturbation of Hamiltonian-symplectic matrix pencil, PEDS, is proposed. PEDS, for the first time, can enforce passivity for DSs. It can also handle all kinds of state space models (both RSs and DSs) with singular D+DT terms. Moreover, a criterion to control the error of perturbation is devised, with which the optimal passive models with the best accuracy can be obtained. Numerical examples then verify that PEDS is efficient, robust and relatively cheap for passivity enforcement of DSs with mild passivity violations.
{"title":"PEDS: Passivity enforcement for descriptor systems via Hamiltonian-symplectic matrix pencil perturbation","authors":"Yuanzhe Wang, Zheng Zhang, Cheng-Kok Koh, G. Pang, N. Wong","doi":"10.1109/ICCAD.2010.5653885","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653885","url":null,"abstract":"Passivity is a crucial property of macromodels to guarantee stable global (interconnected) simulation. However, weakly nonpassive models may be generated for passive circuits and systems in various contexts, such as data fitting, model order reduction (MOR) and electromagnetic (EM) macromodeling. Therefore, a post-processing passivity enforcement algorithm is desired. Most existing algorithms are designed to handle pole-residue models. The few algorithms for state space models only handle regular systems (RSs) with a nonsingular D+DT term. To the authors' best knowledge, no algorithm has been proposed to enforce passivity for more general descriptor systems (DSs) and state space models with singular D+DT terms. In this paper, a new post-processing passivity enforcement algorithm based on perturbation of Hamiltonian-symplectic matrix pencil, PEDS, is proposed. PEDS, for the first time, can enforce passivity for DSs. It can also handle all kinds of state space models (both RSs and DSs) with singular D+DT terms. Moreover, a criterion to control the error of perturbation is devised, with which the optimal passive models with the best accuracy can be obtained. Numerical examples then verify that PEDS is efficient, robust and relatively cheap for passivity enforcement of DSs with mild passivity violations.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"351 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123324852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Networks-on-chip (NoC) is emerging as a promising communication structure, which is scalable with respect to chip complexity. Meanwhile, latest chip designs are increasingly leveraging multiple voltage-frequency domains for energy-efficiency improvement. In this work, we propose a simultaneous task and voltage scheduling algorithm for energy minimization in NoC based designs. The energy-latency tradeoff is handled by Lagrangian relaxation. The core algorithm is a clustering based approach which not only assigns voltage levels and starting time to each task (or Processing Element) but also naturally finds voltage-frequency clusters. Compared to a recent previous work, which performs task scheduling and voltage assignment sequentially, our method leads to an average of 20% energy reduction.
{"title":"Clustering-based simultaneous task and voltage scheduling for NoC systems","authors":"Yifang Liu, Yu Yang, Jiang Hu","doi":"10.5555/2133429.2133488","DOIUrl":"https://doi.org/10.5555/2133429.2133488","url":null,"abstract":"Networks-on-chip (NoC) is emerging as a promising communication structure, which is scalable with respect to chip complexity. Meanwhile, latest chip designs are increasingly leveraging multiple voltage-frequency domains for energy-efficiency improvement. In this work, we propose a simultaneous task and voltage scheduling algorithm for energy minimization in NoC based designs. The energy-latency tradeoff is handled by Lagrangian relaxation. The core algorithm is a clustering based approach which not only assigns voltage levels and starting time to each task (or Processing Element) but also naturally finds voltage-frequency clusters. Compared to a recent previous work, which performs task scheduling and voltage assignment sequentially, our method leads to an average of 20% energy reduction.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":" 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113950694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-11-07DOI: 10.1109/ICCAD.2010.5653738
Dongjin Lee, Myung-Chul Kim, I. Markov
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a large parameter space and the increasing impact of process variation make clock network synthesis particularly challenging. In this work, we develop new modeling techniques and algorithms, as well as a methodology, for clock power optimization subject to tight skew constraints in the presence of process variations. Key contributions include a new time-budgeting step for clock-tree tuning, accurate optimizations that satisfy budgets, modeling and optimization of variational skew. Our implementation, Contango 2.0, outperforms the winners of the ISPD 2010 clock-network synthesis contest on 45nm benchmarks from Intel and IBM.
{"title":"Low-power clock trees for CPUs","authors":"Dongjin Lee, Myung-Chul Kim, I. Markov","doi":"10.1109/ICCAD.2010.5653738","DOIUrl":"https://doi.org/10.1109/ICCAD.2010.5653738","url":null,"abstract":"Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a large parameter space and the increasing impact of process variation make clock network synthesis particularly challenging. In this work, we develop new modeling techniques and algorithms, as well as a methodology, for clock power optimization subject to tight skew constraints in the presence of process variations. Key contributions include a new time-budgeting step for clock-tree tuning, accurate optimizations that satisfy budgets, modeling and optimization of variational skew. Our implementation, Contango 2.0, outperforms the winners of the ISPD 2010 clock-network synthesis contest on 45nm benchmarks from Intel and IBM.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"1 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132477593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many embedded processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.
{"title":"Scheduling of synchronous data flow models on scratchpad memory based embedded processors","authors":"W. Che, Karam S. Chatha","doi":"10.1145/2536747.2536752","DOIUrl":"https://doi.org/10.1145/2536747.2536752","url":null,"abstract":"Many embedded processors incorporate scratchpad memories (SPM) due to their lower power consumption characteristics. SPMs are utilized to host both code and data, often on the same physical unit. Synchronous dataflow (SDF) is a popular format for specifying many embedded system applications particularly in multimedia and network processing domains. Execution of SDF specifications on SPM based processors involves division of memory between actor code and buffers, and scheduling of actor executions and code overlays such that latency is minimized subject to the memory constraints. In our problem instance a traditional minimum buffer SDF schedule could require a larger code overlay overhead and therefore may not be optimal. The paper presents a three stage integer linear programming (ILP) formulation to solve the problem. Further, the paper also introduces modifications to the three stage ILP for incorporating code prefetching optimization to further reduce the code overlay overhead. The effectiveness of the proposed approaches is evaluated by comparisons with minimum buffer SDF schedules for several benchmark applications.","PeriodicalId":344703,"journal":{"name":"2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132514283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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