Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062763
S. A. Abbas, D. Selvathi, V. Nandhini, S. Thiruvengadam
The mobile applications such as web browsing, streaming, and file transfer demand for higher data rates. Such high data rate is achieved by means of spatial multiplexing which uses two codewords. Spatial multiplexing is a transmission technique in wireless communication to transmit independent and separately encoded data signals. Instead of increasing diversity, multiple antennas are used in this case to increase the data rate or capacity of the system. In this paper, VLSI architecture for Layer mapping (LMSM) and Precoding (PCSM) of LTE physical data channels using Spatial multiplexing is proposed. Spatial multiplexing aims mainly for good SINR conditions when compared with transmit diversity. The performance of the proposed architecture is analyzed. It is inferred that the data rate is increased without any increase of bandwidth and power.
{"title":"Synthesis and implementation of spatial multiplexing blocks for 3GPP-LTE using FPGA","authors":"S. A. Abbas, D. Selvathi, V. Nandhini, S. Thiruvengadam","doi":"10.1109/CNT.2014.7062763","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062763","url":null,"abstract":"The mobile applications such as web browsing, streaming, and file transfer demand for higher data rates. Such high data rate is achieved by means of spatial multiplexing which uses two codewords. Spatial multiplexing is a transmission technique in wireless communication to transmit independent and separately encoded data signals. Instead of increasing diversity, multiple antennas are used in this case to increase the data rate or capacity of the system. In this paper, VLSI architecture for Layer mapping (LMSM) and Precoding (PCSM) of LTE physical data channels using Spatial multiplexing is proposed. Spatial multiplexing aims mainly for good SINR conditions when compared with transmit diversity. The performance of the proposed architecture is analyzed. It is inferred that the data rate is increased without any increase of bandwidth and power.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062757
G. LakshmiPriya, S. Manikandan, N. Balamurugan, S. Theodore Chandra
A Novel scaling theory for Single Gate AlInSb/InSb High Electron Mobility Transistors (HEMTs)is derived by solving the 2D Poisson equation. To combat with the issues introduced by device scaling,Effective Conductive Path Effect (ECPE) has been taken into account.From literature, scaling Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)with ECPE has shown stronger immunity towards short channel effects (SCEs). Hence, on introducing the ECPE in HEMT, a simple scaling equation has been derived and on solving this equation the minimum channel potential Φdeff,min and the new scaling factor α is obtained to model the subthreshold behavior of high electron mobility transistors. The analytical model has been further extended in finding the various device parameters. Then simulations of the proposed work are performed using 2D TCAD sentaurus device simulator. The analytical results are compared and verified with the TCAD simulation results. Finally, results of the proposed work are compared with the scaling theory for MOSFETs with ECPE.
{"title":"A Novel scaling theory for Single Gate AlInSb/InSb High Electron Mobility Transistors","authors":"G. LakshmiPriya, S. Manikandan, N. Balamurugan, S. Theodore Chandra","doi":"10.1109/CNT.2014.7062757","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062757","url":null,"abstract":"A Novel scaling theory for Single Gate AlInSb/InSb High Electron Mobility Transistors (HEMTs)is derived by solving the 2D Poisson equation. To combat with the issues introduced by device scaling,Effective Conductive Path Effect (ECPE) has been taken into account.From literature, scaling Metal Oxide Semiconductor Field Effect Transistors (MOSFETs)with ECPE has shown stronger immunity towards short channel effects (SCEs). Hence, on introducing the ECPE in HEMT, a simple scaling equation has been derived and on solving this equation the minimum channel potential Φdeff,min and the new scaling factor α is obtained to model the subthreshold behavior of high electron mobility transistors. The analytical model has been further extended in finding the various device parameters. Then simulations of the proposed work are performed using 2D TCAD sentaurus device simulator. The analytical results are compared and verified with the TCAD simulation results. Finally, results of the proposed work are compared with the scaling theory for MOSFETs with ECPE.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128015403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062722
G. Prema, P. Gayatri
Cognitive Radio is an enabling technology for accessing the unused spectrum. It may need to work in blind scenarios where it is unaware of the received signal parameters. In real-time military applications, the cyclostationary analysis of OFDM signals involves high computational complexity and requires additional processing and detection time. In order to detect the active carrier frequencies in such a scenario, we propose a blind two stage spectrum sensing scheme where the sequential sliding window energy detection is followed by cyclostationary feature detection that extracts the underlying periodic properties of the OFDM signal. The second-order cyclostationarity due to the equally spaced pilot subcarriers and due to the preamble with cyclic extension is explored. The peaks due to pilots and due to the preamble and cyclic extension are captured. The cyclostationary feature detection is performed over a selected cyclic spectrum instead of exploring the entire spectrum. The blind energy/cyclostationary detection of OFDM signals is compared with the matched filter based spectrum sensing algorithm of detecting OFDM signals. Simulations demonstrate the reliable and highly robust performance of the proposed non-parametric spectrum sensing method in Gaussian environment.
{"title":"Blind spectrum sensing method for OFDM signal detection in Cognitive Radio communications","authors":"G. Prema, P. Gayatri","doi":"10.1109/CNT.2014.7062722","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062722","url":null,"abstract":"Cognitive Radio is an enabling technology for accessing the unused spectrum. It may need to work in blind scenarios where it is unaware of the received signal parameters. In real-time military applications, the cyclostationary analysis of OFDM signals involves high computational complexity and requires additional processing and detection time. In order to detect the active carrier frequencies in such a scenario, we propose a blind two stage spectrum sensing scheme where the sequential sliding window energy detection is followed by cyclostationary feature detection that extracts the underlying periodic properties of the OFDM signal. The second-order cyclostationarity due to the equally spaced pilot subcarriers and due to the preamble with cyclic extension is explored. The peaks due to pilots and due to the preamble and cyclic extension are captured. The cyclostationary feature detection is performed over a selected cyclic spectrum instead of exploring the entire spectrum. The blind energy/cyclostationary detection of OFDM signals is compared with the matched filter based spectrum sensing algorithm of detecting OFDM signals. Simulations demonstrate the reliable and highly robust performance of the proposed non-parametric spectrum sensing method in Gaussian environment.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121674162","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062773
D. Selvathi, M. Pown, Junior Research Fellow
The Band Pass Filters are commonly used in wireless receivers and transmitter. The usage of spiral inductor in the band pass filters requires large chip area which can increase the band pass filter size and is difficult to obtain high Q-factor. This paper presents the active inductor based band pass filter using TSMC 0.18μm RF CMOS process. The band pass filter is realized using active inductor with suitable input and output buffer stages. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator. This structure provides the negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The tuning of the center frequency is achieved through the controllable current sources. This active inductor demonstrates a maximum quality factor of 244 with a 154nH inductance. The simulation result of band pass filter designed at 100MHz has the gain of 6.129 dB and input return loss of -11.474 dB. The simulated IIP3 is -19 dBm and power consumed by the BPF is 28mW.
{"title":"Design of Band Pass Filter using active inductor for RF receiver front-end","authors":"D. Selvathi, M. Pown, Junior Research Fellow","doi":"10.1109/CNT.2014.7062773","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062773","url":null,"abstract":"The Band Pass Filters are commonly used in wireless receivers and transmitter. The usage of spiral inductor in the band pass filters requires large chip area which can increase the band pass filter size and is difficult to obtain high Q-factor. This paper presents the active inductor based band pass filter using TSMC 0.18μm RF CMOS process. The band pass filter is realized using active inductor with suitable input and output buffer stages. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator. This structure provides the negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The tuning of the center frequency is achieved through the controllable current sources. This active inductor demonstrates a maximum quality factor of 244 with a 154nH inductance. The simulation result of band pass filter designed at 100MHz has the gain of 6.129 dB and input return loss of -11.474 dB. The simulated IIP3 is -19 dBm and power consumed by the BPF is 28mW.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128649362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062759
S. Syed Ameer Abbas, D. Selvathi, G. Shobana, S. Thiruvengadam
In Long Term Evolution (LTE) downlink systems, the Physical Control Format Indicator Channel (PCFICH) carries the control information about the number of Orthogonal Frequency Division Multiplexing (OFDM) symbols used for transmission of control information. In this paper, receiver structure using argument maximum in maximum likelihood (ML) algorithm that utilizes less hardware are proposed and implemented for decoding the CFI value. The proposed architectures are implemented in Virtex-6 xc6vlx240tff1156-1 FPGA device for various antenna configurations at base station and User Equipment (UE). The performance of the proposed architectures is analyzed and compared with the architecture already designed using argument minimum and direct methods in terms of timing cycles and resource complexity. It is shown that the proposed architectures use fewer amounts of hardware resources in FPGA compared to other methods.
{"title":"Performance analysis of maximum likelihood arrangement in the receiver structure for LTE PCFICH aiming at low resource utilization using VLSI DSP techniques","authors":"S. Syed Ameer Abbas, D. Selvathi, G. Shobana, S. Thiruvengadam","doi":"10.1109/CNT.2014.7062759","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062759","url":null,"abstract":"In Long Term Evolution (LTE) downlink systems, the Physical Control Format Indicator Channel (PCFICH) carries the control information about the number of Orthogonal Frequency Division Multiplexing (OFDM) symbols used for transmission of control information. In this paper, receiver structure using argument maximum in maximum likelihood (ML) algorithm that utilizes less hardware are proposed and implemented for decoding the CFI value. The proposed architectures are implemented in Virtex-6 xc6vlx240tff1156-1 FPGA device for various antenna configurations at base station and User Equipment (UE). The performance of the proposed architectures is analyzed and compared with the architecture already designed using argument minimum and direct methods in terms of timing cycles and resource complexity. It is shown that the proposed architectures use fewer amounts of hardware resources in FPGA compared to other methods.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128899517","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062739
L. Femila, V. Vijayarangan
MANET is a set of mobile devices with no fixed topology. Ad hoc means “for this purpose”. In MANET nodes are battery operated with dynamic network topology hence energy efficiency is an important design consideration to extend the lifetime of networks. Topology of network plays an important role for energy conservation. Topology control is to decide the transmission power of nodes and to increase network connectivity as well as increase the energy efficiency. In this paper, we present Cooperative Communication(CC) is to link disconnected networks in order to reduce transmission power of nodes with increased network connectivity.CC is a proficient technology to confess the quality of service (QoS) in MANETs. Thus, this paper proposes the energy efficient routing for MANET with the use of CC and network coding. Network coding used to reduce bandwidth consumption and hence power consumption also reduced. The proposed routing algorithm is efficient power aware routing with network coding (EPARN) identifies the capacity of a node not just by its residual battery power, but also by the expected energy spent in reliably forwarding data packets over a specific link. In simulation results, the performance of the proposed algorithms is compared with the other existing methods.
{"title":"Transmission power control in mobile ad hoc network using network coding and Co-Operative Communication","authors":"L. Femila, V. Vijayarangan","doi":"10.1109/CNT.2014.7062739","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062739","url":null,"abstract":"MANET is a set of mobile devices with no fixed topology. Ad hoc means “for this purpose”. In MANET nodes are battery operated with dynamic network topology hence energy efficiency is an important design consideration to extend the lifetime of networks. Topology of network plays an important role for energy conservation. Topology control is to decide the transmission power of nodes and to increase network connectivity as well as increase the energy efficiency. In this paper, we present Cooperative Communication(CC) is to link disconnected networks in order to reduce transmission power of nodes with increased network connectivity.CC is a proficient technology to confess the quality of service (QoS) in MANETs. Thus, this paper proposes the energy efficient routing for MANET with the use of CC and network coding. Network coding used to reduce bandwidth consumption and hence power consumption also reduced. The proposed routing algorithm is efficient power aware routing with network coding (EPARN) identifies the capacity of a node not just by its residual battery power, but also by the expected energy spent in reliably forwarding data packets over a specific link. In simulation results, the performance of the proposed algorithms is compared with the other existing methods.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127111417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062770
T. Manonmani, K. Mala
Videos are of the most popular rich media formats carrying large amount of visual, audio and textual information. In recent years people all over the world show great interest in video mining to extract meaningful patterns and knowledge to enhance the smart level of video applications. In this work Speeded Up Robust Features (SURF) are used to detect the candidate frames among the set of key frames extracted from a video content. By eliminating the presence of duplicate key frames the computational and time complexity of processing a large number of frames is reduced. From the identified candidate frames semantic objects with meaningful content are extracted which improves the efficiency of video mining applications like Video recommendation systems, Video concept detection etc. Experimental results show that the proposed approach eliminates the duplicate frames without a prior knowledge of the video content.
{"title":"Robust candidate frame detection in videos using semantic content modeling","authors":"T. Manonmani, K. Mala","doi":"10.1109/CNT.2014.7062770","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062770","url":null,"abstract":"Videos are of the most popular rich media formats carrying large amount of visual, audio and textual information. In recent years people all over the world show great interest in video mining to extract meaningful patterns and knowledge to enhance the smart level of video applications. In this work Speeded Up Robust Features (SURF) are used to detect the candidate frames among the set of key frames extracted from a video content. By eliminating the presence of duplicate key frames the computational and time complexity of processing a large number of frames is reduced. From the identified candidate frames semantic objects with meaningful content are extracted which improves the efficiency of video mining applications like Video recommendation systems, Video concept detection etc. Experimental results show that the proposed approach eliminates the duplicate frames without a prior knowledge of the video content.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129192580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062762
K. Paldurai, K. Hariharan, G. Karthikeyan, K. Lakshmanan
The Multiply-Accumulator (MAC) unit always lies in the critical path that determines the speed of the overall hardware systems. Therefore, a high-speed MAC that is capable of supporting multiple precisions and parallel operations is highly desirable. This paper describes the implementation of a MAC unit using area efficient Vedic multiplier which enhanced in terms of area and path delay. Speed of the multiplier is very important to any Digital Signal Processors (DSPs). To construct a N×N bit Vedic Multiplier, four N/2×N/2 VM and three N-bit Ripple Carry Adders (RCAs) are required. But in our proposed VM, instead of 3 N-bit RCA, only one N-bit RCA and our two proposed adders are used. In our proposed Adders, the area required for N-bit RCA has been reduced, leading to a greater reduction in the logic delay. We have developed the generalized architectures for NxN VM, MAC unit and for our proposed Adders. The proposed MAC and conventional MAC are coded in Verilog, synthesized and simulated using ISE simulator. It is implemented on the Xilinx Spartan6 family xc6slx150t-4fgg900 FPGA. The Area and logic delay of the proposed MAC and conventional VM are compared.
{"title":"Implementation of MAC using area efficient and reduced delay vedic multiplier targeted at FPGA architectures","authors":"K. Paldurai, K. Hariharan, G. Karthikeyan, K. Lakshmanan","doi":"10.1109/CNT.2014.7062762","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062762","url":null,"abstract":"The Multiply-Accumulator (MAC) unit always lies in the critical path that determines the speed of the overall hardware systems. Therefore, a high-speed MAC that is capable of supporting multiple precisions and parallel operations is highly desirable. This paper describes the implementation of a MAC unit using area efficient Vedic multiplier which enhanced in terms of area and path delay. Speed of the multiplier is very important to any Digital Signal Processors (DSPs). To construct a N×N bit Vedic Multiplier, four N/2×N/2 VM and three N-bit Ripple Carry Adders (RCAs) are required. But in our proposed VM, instead of 3 N-bit RCA, only one N-bit RCA and our two proposed adders are used. In our proposed Adders, the area required for N-bit RCA has been reduced, leading to a greater reduction in the logic delay. We have developed the generalized architectures for NxN VM, MAC unit and for our proposed Adders. The proposed MAC and conventional MAC are coded in Verilog, synthesized and simulated using ISE simulator. It is implemented on the Xilinx Spartan6 family xc6slx150t-4fgg900 FPGA. The Area and logic delay of the proposed MAC and conventional VM are compared.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132491008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062715
Shivani Gupta, Saket Kumar
In this paper Design and Analysis of Compact and Broadband High Gain Micro strip Patch Antennas is presented using via hole technique for enhancement in bandwidth. This paper present optimization of inductance using Via hole technique, via hole technique used to reduced losses of ground plane and enhance surface current, the proposed antenna is validated in IE3D Simulator, from the simulation results we found this technique provided broad bandwidth. The proposed antenna used for C-Band application, Microstrip Patch Antenna (MPA) is generally used in modern communication devices and a large part of day-to-day communication is done through it. Study of literature of past few year shows that, the leading work on MPA is focused on designing compact sized broadband microstrip antenna. But inherently MPA have narrow bandwidth so to enhance bandwidth various techniques are engaged.
{"title":"Design and Analysis of Compact and Broadband High Gain Micro strip Patch Antennas","authors":"Shivani Gupta, Saket Kumar","doi":"10.1109/CNT.2014.7062715","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062715","url":null,"abstract":"In this paper Design and Analysis of Compact and Broadband High Gain Micro strip Patch Antennas is presented using via hole technique for enhancement in bandwidth. This paper present optimization of inductance using Via hole technique, via hole technique used to reduced losses of ground plane and enhance surface current, the proposed antenna is validated in IE3D Simulator, from the simulation results we found this technique provided broad bandwidth. The proposed antenna used for C-Band application, Microstrip Patch Antenna (MPA) is generally used in modern communication devices and a large part of day-to-day communication is done through it. Study of literature of past few year shows that, the leading work on MPA is focused on designing compact sized broadband microstrip antenna. But inherently MPA have narrow bandwidth so to enhance bandwidth various techniques are engaged.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115156877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-12-01DOI: 10.1109/CNT.2014.7062771
G. S. Yogesh, S. Ramachandran
This paper presents a software implementation of context adaptive variable length decoder (CAVLD) and context adaptive variable length coder (CAVLC). Efficient algorithms for coding and decoding of Coeff_Token, levels, total zeros, and run_before have been developed, which are the five vital syntax elements of CAVLC and CAVLD. The necessary blocks namely Integer Transform, quantization and their inverses are also coded. This implementation can process video sequences of any size. Experiments have been conducted to process video sequences up to High Definition 720p (1280×720 pixels) resolution and up to 30fps frame rate and also for high resolution pictures. The reconstructed pictures are of acceptable video quality with PSNR values greater than 34dB. The design can be conFig.d to different Qp values. The proposed work is coded using matlab and serves as a basis for FPGA implementation of H.264 Base line video decoder.
{"title":"Context adaptive variable length decoder of H.264","authors":"G. S. Yogesh, S. Ramachandran","doi":"10.1109/CNT.2014.7062771","DOIUrl":"https://doi.org/10.1109/CNT.2014.7062771","url":null,"abstract":"This paper presents a software implementation of context adaptive variable length decoder (CAVLD) and context adaptive variable length coder (CAVLC). Efficient algorithms for coding and decoding of Coeff_Token, levels, total zeros, and run_before have been developed, which are the five vital syntax elements of CAVLC and CAVLD. The necessary blocks namely Integer Transform, quantization and their inverses are also coded. This implementation can process video sequences of any size. Experiments have been conducted to process video sequences up to High Definition 720p (1280×720 pixels) resolution and up to 30fps frame rate and also for high resolution pictures. The reconstructed pictures are of acceptable video quality with PSNR values greater than 34dB. The design can be conFig.d to different Qp values. The proposed work is coded using matlab and serves as a basis for FPGA implementation of H.264 Base line video decoder.","PeriodicalId":347883,"journal":{"name":"2014 International Conference on Communication and Network Technologies","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126837439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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