In this paper we present a class of min-cut placement algorithms for solving some assignment problems related to the physical implementation of electrical circuits. We discuss the need for abandoning classical objective functions based upon distance, and introduce new objective functions based upon "signals cut." The number of signals cut by a line c is a lower bound on the number of routing tracks which must cross c in routing the circuit. Three specific objective functions are introduced and the relationship between one of these and a classical distance measure based upon half-perimeter is presented. Two min-cut placement algorithms are presented. They are referred to as Ouadrature and Slice/Bisection. The concepts of a block and cut line are introduced. These two entities are the major constructs in developing any new min-cut placement algorithm. Most of the concepts presented have been implemented, and some experimental results are given.
{"title":"A class of min-cut placement algorithms","authors":"M. Breuer","doi":"10.1145/62882.62896","DOIUrl":"https://doi.org/10.1145/62882.62896","url":null,"abstract":"In this paper we present a class of min-cut placement algorithms for solving some assignment problems related to the physical implementation of electrical circuits. We discuss the need for abandoning classical objective functions based upon distance, and introduce new objective functions based upon \"signals cut.\" The number of signals cut by a line c is a lower bound on the number of routing tracks which must cross c in routing the circuit. Three specific objective functions are introduced and the relationship between one of these and a classical distance measure based upon half-perimeter is presented. Two min-cut placement algorithms are presented. They are referred to as Ouadrature and Slice/Bisection. The concepts of a block and cut line are introduced. These two entities are the major constructs in developing any new min-cut placement algorithm.\u0000 Most of the concepts presented have been implemented, and some experimental results are given.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125822609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A linear-time heuristic for improving network partitions","authors":"C. M. Fiduccia, R. M. Mattheyses","doi":"10.1145/62882.62910","DOIUrl":"https://doi.org/10.1145/62882.62910","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"197 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121109154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A connectivity comparison program that has proven effective in a production environment is described. The pattern recognition framework utilized automatically recognizes component renaming and pin swapping, and performs robustly in the face of connectivity errors.
{"title":"A comprehensive approach to a connectivity audit, or a fruitful comparison of apples and oranges","authors":"R. M. Allgair, D. Evans","doi":"10.1145/62882.62923","DOIUrl":"https://doi.org/10.1145/62882.62923","url":null,"abstract":"A connectivity comparison program that has proven effective in a production environment is described. The pattern recognition framework utilized automatically recognizes component renaming and pin swapping, and performs robustly in the face of connectivity errors.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"63 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114125869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A 2-dimensional placement algorithm for the layout of electrical circuits","authors":"D. Schweikert","doi":"10.1145/62882.62891","DOIUrl":"https://doi.org/10.1145/62882.62891","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125094111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
LTX is a minicomputer-based design system for largescale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms for two-dimensional placement, string placement, exploitation of equivalent terminals, decomposition of routing into channels, and channel routing. Circuit connectivity is preserved during interactive procedures. LTX runs on an H-P 2100 series computer with 32K of memory and disc. In current applications to polycell-style layouts, one to two weeks is typically required for completion of the layout design of an LSI chip containing 500 cells.
{"title":"LTX-A system for the directed automatic design of LSI circuits","authors":"G. Persky, D. Deutsch, D. Schweikert","doi":"10.1145/62882.62890","DOIUrl":"https://doi.org/10.1145/62882.62890","url":null,"abstract":"LTX is a minicomputer-based design system for largescale integrated circuit chip layout which offers a flexible set of interactive and automatic procedures for translating a circuit connectivity description into a finished mask design. The system encompasses algorithms for two-dimensional placement, string placement, exploitation of equivalent terminals, decomposition of routing into channels, and channel routing. Circuit connectivity is preserved during interactive procedures. LTX runs on an H-P 2100 series computer with 32K of memory and disc. In current applications to polycell-style layouts, one to two weeks is typically required for completion of the layout design of an LSI chip containing 500 cells.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114253399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Using bottom-up design techniques in the synthesis of digital hardware from abstract behavioral descriptions","authors":"M. C. McFarland","doi":"10.1145/62882.62955","DOIUrl":"https://doi.org/10.1145/62882.62955","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"182 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125156104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a method for formally modeling digital logic using algebraic relations. The relations model digital logic at the register-transfer (RT) level. An RT-level behaviorial specification is used to develop the relations, which express timing relationships that must be satisfied by any correct implementation. An extension of the model is shown which can be used for synthesis at the RT level. The growth rate and computational properties of the model are discussed, and an example of synthesis is shown.
{"title":"A formal method for the specification, analysis, and design of register-transferlevel digital logic","authors":"L. Hafer, Alice C. Parker","doi":"10.1145/62882.62947","DOIUrl":"https://doi.org/10.1145/62882.62947","url":null,"abstract":"This paper describes a method for formally modeling digital logic using algebraic relations. The relations model digital logic at the register-transfer (RT) level. An RT-level behaviorial specification is used to develop the relations, which express timing relationships that must be satisfied by any correct implementation. An extension of the model is shown which can be used for synthesis at the RT level. The growth rate and computational properties of the model are discussed, and an example of synthesis is shown.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128317308","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"HAL: A multi-paradigm approach to automatic data path synthesis","authors":"P. Paulin, J. Knight, E. F. Girczyc","doi":"10.1145/62882.62953","DOIUrl":"https://doi.org/10.1145/62882.62953","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114921885","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Timing Verification consists of validating the path delays (primary input or storage element to primary output or storage element) to be sure they are not too long or too short and checking the clock pulses to be sure they are not too wide or too narrow. The programs addressing these problems neither produce input patterns like test pattern generators nor require input patterns like traditional simulators. Several programs (described here) operate by tracing paths [P173, WO78, SA81, KA81]. One program [MC80] extends simulation into a pessimistic analyzer not dependent on test patterns. Timing Analysis, a program described recently in [H182a], is designed to analyze the timing of large digital computers and is based, in part, on the concepts disclosed in a patented method [DO81] for determining the extreme characteristics of logic block diagrams. The output of Timing Analysis includes “slack” at each block to provide a measure of the severity of the timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach.
{"title":"Timing verification and the timing analysis program","authors":"Robert B. Hitchcock","doi":"10.1145/62882.62936","DOIUrl":"https://doi.org/10.1145/62882.62936","url":null,"abstract":"Timing Verification consists of validating the path delays (primary input or storage element to primary output or storage element) to be sure they are not too long or too short and checking the clock pulses to be sure they are not too wide or too narrow. The programs addressing these problems neither produce input patterns like test pattern generators nor require input patterns like traditional simulators. Several programs (described here) operate by tracing paths [P173, WO78, SA81, KA81]. One program [MC80] extends simulation into a pessimistic analyzer not dependent on test patterns. Timing Analysis, a program described recently in [H182a], is designed to analyze the timing of large digital computers and is based, in part, on the concepts disclosed in a patented method [DO81] for determining the extreme characteristics of logic block diagrams. The output of Timing Analysis includes “slack” at each block to provide a measure of the severity of the timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116945624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper discusses a new linerouting algorithm. The algorithm has been programmed in FORTRAN II for the IBM 7094 and in FORTRAN IV for the IBM 360/~5. It has given good results when applied to many llne-routing problems such as mazes, printed circuit boards, substrates, and PERT diagrams. The main advantages of this algorithm, which is based on the continuous plane, over conventional algorithms based on the discrete plane are twofold: 1. Since the algorithm is based on the continuous plane, there is theoretically no limit to the degree of precision used to describe the position of points. In practice, the only factor restricting the precision is the magnitude of the largest (or smallest) number which may be stored in a computer. As a result, the nodes on a printed circuit board, for example, can be input with mil accuracy. If this feat were to be accomplished by existing methods on a 9×9 inch board, a matrix of 81,000,000 cells would have to be stored (and searched) in the computer. 2. The algorithm stores only line segments~ therefore to find a path, only the segments that are currently defined need be investigated. Usually with conventional methods, every cell that lies on every possible minimal path must be investigated. The net result is that this algorithm is much faster than the conventional method.
{"title":"A solution to line routing problems on the continuous plane","authors":"Dave Hightower","doi":"10.1145/62882.62883","DOIUrl":"https://doi.org/10.1145/62882.62883","url":null,"abstract":"This paper discusses a new linerouting algorithm. The algorithm has been programmed in FORTRAN II for the IBM 7094 and in FORTRAN IV for the IBM 360/~5. It has given good results when applied to many llne-routing problems such as mazes, printed circuit boards, substrates, and PERT diagrams. The main advantages of this algorithm, which is based on the continuous plane, over conventional algorithms based on the discrete plane are twofold: 1. Since the algorithm is based on the continuous plane, there is theoretically no limit to the degree of precision used to describe the position of points. In practice, the only factor restricting the precision is the magnitude of the largest (or smallest) number which may be stored in a computer. As a result, the nodes on a printed circuit board, for example, can be input with mil accuracy. If this feat were to be accomplished by existing methods on a 9×9 inch board, a matrix of 81,000,000 cells would have to be stored (and searched) in the computer. 2. The algorithm stores only line segments~ therefore to find a path, only the segments that are currently defined need be investigated. Usually with conventional methods, every cell that lies on every possible minimal path must be investigated. The net result is that this algorithm is much faster than the conventional method.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123683166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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