{"title":"Automatic circuit analysis based on mask information","authors":"B. Preas, B. Lindsey, C. Gwyn","doi":"10.1145/62882.62889","DOIUrl":"https://doi.org/10.1145/62882.62889","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134450942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Donald M. Schuler and Ernst G. Ulrich GTE Laboratories, Incorporated Waltham, Massachusetts This paper presents two algorithms, one for clustering a set of interconnected nodes and the other for forming a linear placement of clustered interconnected nodes. The linear placement algorithm requires the output of clustering as an input. The two algorithms were designed to analyze the structure of digital logic for automatic placement of logic functions on a MOS/LSI chip as part of an automatic layoul system8 and so far have only been used for that application. However, the clustering algorithm could be used to analyze any undirected graph. Both algorithms are noniterative and provide very good results with small amounts of computer time. I. CLUSTERING ALGORITHM Clustering analyzes a set of interconnected nodes and forms groups that have strong internal connections but weak external connections to other groups. The set of interconnected nodes can be thought of as an undirected graph with a weight on each edge equal to the connection strength Cij between node i and node j. Only branches with Cij >o are represented. The undirected graph is represented by its connection matrix C (where Cij is the connection strength between nodes i and j). Since most Cij = 0 and Cij = Cji, a sparse half matrix is used. This greatly reduces storage requirements. Clustering is done in a pairwise fashion. A clustering value is calculated for each pair of interconnected elements where an element can be either a node or a cluster of nodes (initially, of course, all elements are nodes). The clustering value CVij for elements i and j is given by the following equation: cvij = f (S.) C i’ + f (S.) Ci. ’ (TI Cij) 3 (Tj Cij) (1) where: Cij = connection strength between elements i and j Ti = total connection strength to element i Tj = total connection strength to element j f (Si) = some function of the size of element i f (Sj) = some function of the size of element j Assuming that f (Si) = f (Sj) = 1, some examples of the clustering value (CV) are shown in Figure 1.
Donald M. Schuler和Ernst G. Ulrich GTE实验室，Incorporated Waltham, Massachusetts .本文提出了两种算法，一种用于聚类一组相互连接的节点，另一种用于形成聚类相互连接节点的线性放置。线性布局算法需要将聚类的输出作为输入。设计这两种算法是为了分析数字逻辑的结构，以便在MOS/LSI芯片上自动放置逻辑功能，作为自动布局系统的一部分，到目前为止只用于该应用。然而，聚类算法可以用于分析任何无向图。这两种算法都是非迭代的，并且用很少的计算机时间提供非常好的结果。一、聚类算法聚类分析一组相互连接的节点，形成与其他组内部联系强、外部联系弱的组。互连节点集可以看作是一个无向图，每条边的权值等于节点i和节点j之间的连接强度Cij。只表示Cij > 0的分支。无向图由其连接矩阵C表示(其中Cij为节点i和j之间的连接强度)。由于大多数Cij = 0, Cij = Cji，因此使用稀疏半矩阵。这大大降低了存储需求。集群是以成对的方式完成的。为每一对相互连接的元素计算集群值，其中一个元素可以是一个节点，也可以是一个节点集群(当然，最初所有元素都是节点)。元素i和j的聚类值CVij由下式给出:CVij = f (s)C i ' + f (s)Ci。’(TI Cij) 3 (Tj Cij)(1)式中:Cij =元素i与元素j之间的连接强度TI =元素i的总连接强度Tj =元素j的总连接强度f (Si) =元素i大小的某函数f (Sj) =元素j大小的某函数假设f (Si) = f (Sj) = 1，聚类值(CV)的一些示例如图1所示。
{"title":"Clustering and linear placement","authors":"Donald M. Schuler, Ernst G. Ulrich","doi":"10.1145/62882.62885","DOIUrl":"https://doi.org/10.1145/62882.62885","url":null,"abstract":"Donald M. Schuler and Ernst G. Ulrich GTE Laboratories, Incorporated Waltham, Massachusetts This paper presents two algorithms, one for clustering a set of interconnected nodes and the other for forming a linear placement of clustered interconnected nodes. The linear placement algorithm requires the output of clustering as an input. The two algorithms were designed to analyze the structure of digital logic for automatic placement of logic functions on a MOS/LSI chip as part of an automatic layoul system8 and so far have only been used for that application. However, the clustering algorithm could be used to analyze any undirected graph. Both algorithms are noniterative and provide very good results with small amounts of computer time. I. CLUSTERING ALGORITHM Clustering analyzes a set of interconnected nodes and forms groups that have strong internal connections but weak external connections to other groups. The set of interconnected nodes can be thought of as an undirected graph with a weight on each edge equal to the connection strength Cij between node i and node j. Only branches with Cij >o are represented. The undirected graph is represented by its connection matrix C (where Cij is the connection strength between nodes i and j). Since most Cij = 0 and Cij = Cji, a sparse half matrix is used. This greatly reduces storage requirements. Clustering is done in a pairwise fashion. A clustering value is calculated for each pair of interconnected elements where an element can be either a node or a cluster of nodes (initially, of course, all elements are nodes). The clustering value CVij for elements i and j is given by the following equation: cvij = f (S.) C i’ + f (S.) Ci. ’ (TI Cij) 3 (Tj Cij) (1) where: Cij = connection strength between elements i and j Ti = total connection strength to element i Tj = total connection strength to element j f (Si) = some function of the size of element i f (Sj) = some function of the size of element j Assuming that f (Si) = f (Sj) = 1, some examples of the clustering value (CV) are shown in Figure 1.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123115863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
level designer can become the detailed functional specification needed by a lower level. Within a design abstraction there are usually several possible alternative structures for a particular desired behavior. Each of these may exhibit differing cost performance characteristics and require different refinement and optimization techniques. These structures can be grouped into sets of similar characteristics called desrgn styles. Styles reflect varlous design approaches forced by different design constraints to achieve the same behavlor. A simple example Is the choice of ripple-carry addition versus carry-look-ahead. The ripple-carry adder is appropriate if space is at a higher premium than delay time. As each level is designed, constraints are produced which must be propagated to the designers at the lower levels. These constraints reflect design style declslons, or structural partitions of higher-level design constraints. Style decisions constrain the design styles and strategies of sub-section designers. An example is the decision to use pre-charged carry addition, forcing the use of appropriate implementation components. Structural partitioning refers to the dlvlding of global constraints such as time, power, or area into local constraints on these values. A requirement of 175nS as maximum cycle time makes demands on the critical path of operations in each cycle. As the design is implemented, this puts a partitioning constraint on the design of each functional component. Figure 1 shows the possible allocation of timing constraints in two stages of the design process. In the first case the allocation has simply divided the cycle time among the function units. In the second case (later in the design) a failure report from the multiply design task has forced a different allocation of time between the functional units. Iterative refinement of a design requires continuous performance monitoring relative to the design goals. This model assumes a simple approach similar to ‘Knobs’ and ‘Gauges’. A human operator monitoring a process closes the loop manually by reading the appropriate gauges and making adjustments to the knobs (parameters) controlling the process execution. We apply this same simple approach to controlling the design pro-
{"title":"An expert-system paradigm for design","authors":"F. Brewer, D. Gajski","doi":"10.1145/62882.62951","DOIUrl":"https://doi.org/10.1145/62882.62951","url":null,"abstract":"level designer can become the detailed functional specification needed by a lower level. Within a design abstraction there are usually several possible alternative structures for a particular desired behavior. Each of these may exhibit differing cost performance characteristics and require different refinement and optimization techniques. These structures can be grouped into sets of similar characteristics called desrgn styles. Styles reflect varlous design approaches forced by different design constraints to achieve the same behavlor. A simple example Is the choice of ripple-carry addition versus carry-look-ahead. The ripple-carry adder is appropriate if space is at a higher premium than delay time. As each level is designed, constraints are produced which must be propagated to the designers at the lower levels. These constraints reflect design style declslons, or structural partitions of higher-level design constraints. Style decisions constrain the design styles and strategies of sub-section designers. An example is the decision to use pre-charged carry addition, forcing the use of appropriate implementation components. Structural partitioning refers to the dlvlding of global constraints such as time, power, or area into local constraints on these values. A requirement of 175nS as maximum cycle time makes demands on the critical path of operations in each cycle. As the design is implemented, this puts a partitioning constraint on the design of each functional component. Figure 1 shows the possible allocation of timing constraints in two stages of the design process. In the first case the allocation has simply divided the cycle time among the function units. In the second case (later in the design) a failure report from the multiply design task has forced a different allocation of time between the functional units. Iterative refinement of a design requires continuous performance monitoring relative to the design goals. This model assumes a simple approach similar to ‘Knobs’ and ‘Gauges’. A human operator monitoring a process closes the loop manually by reading the appropriate gauges and making adjustments to the knobs (parameters) controlling the process execution. We apply this same simple approach to controlling the design pro-","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"179 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116525498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"TEGAS2 - Anatomy of a general purpose test generation and simulation system for digital logic","authors":"S. Szygenda","doi":"10.1145/62882.62917","DOIUrl":"https://doi.org/10.1145/62882.62917","url":null,"abstract":"","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128085603","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A stochastic model is developed for estimating wiring space requirements for one-dimensional layouts. This model uses as input the number of devices in the complex to be wired, the average length of a connection, and the average number of connections per device, to compute the probability of successfully wiring the devices as a function of the number of tracks provided. A heuristic approach is used to extend this model to the two-dimensional case, and tested against experimen-tal studies. Satisfactory agreement is found between a priori calculations of track requirements for the two-dimensional case against global wiring solutions for artificially generated problems, and for some layouts of actual logic complexes.
{"title":"Prediction of wiring space requirements for LSI","authors":"W. Heller, W. F. Michail, W. Donath","doi":"10.1145/62882.62894","DOIUrl":"https://doi.org/10.1145/62882.62894","url":null,"abstract":"A stochastic model is developed for estimating wiring space requirements for one-dimensional layouts. This model uses as input the number of devices in the complex to be wired, the average length of a connection, and the average number of connections per device, to compute the probability of successfully wiring the devices as a function of the number of tracks provided.\u0000 A heuristic approach is used to extend this model to the two-dimensional case, and tested against experimen-tal studies. Satisfactory agreement is found between a priori calculations of track requirements for the two-dimensional case against global wiring solutions for artificially generated problems, and for some layouts of actual logic complexes.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"2 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116823382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Technology binding is the process of mapping a technology independent description of a circuit into a particular technology. This paper outlines a formalism of this problem and offers a solution to the problem in terms of matching patterns, describing technology specific cells and optimizations, against a technology independent circuit represented as a directed acyclic graph. This solution is implemented in DAGON. DAGON rests on a firm algorithmic foundation, and is able to guarantee locally optimal matches against a set of over three thousand patterns. DAGON is an integral part of a synthesis system that has been found to provide industrial quality solutions to real circuit design problems.
{"title":"DAGON: Technology binding and local optimization by DAG matching","authors":"K. Keutzer","doi":"10.1145/62882.62957","DOIUrl":"https://doi.org/10.1145/62882.62957","url":null,"abstract":"Technology binding is the process of mapping a technology independent description of a circuit into a particular technology. This paper outlines a formalism of this problem and offers a solution to the problem in terms of matching patterns, describing technology specific cells and optimizations, against a technology independent circuit represented as a directed acyclic graph. This solution is implemented in DAGON. DAGON rests on a firm algorithmic foundation, and is able to guarantee locally optimal matches against a set of over three thousand patterns. DAGON is an integral part of a synthesis system that has been found to provide industrial quality solutions to real circuit design problems.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130866730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach.
{"title":"A prototype framework for knowledge-based analog circuit synthesis","authors":"R. Harjani, Rob A. Rutenbar, L. Carley","doi":"10.1145/62882.62956","DOIUrl":"https://doi.org/10.1145/62882.62956","url":null,"abstract":"An organization for a knowledge-based analog circuit synthesis tool is described. Analog circuit topologies are represented as a hierarchy of functional blocks; a planning mechanism is introduced to translate performance specifications between levels in this circuit hierarchy. A prototype implementation, OASYS, synthesizes sized transistor schematics for simple CMOS operational amplifiers from performance specifications and process parameters, and demonstrates the workability of the approach.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"180 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133876730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The electrical circuit simulation of large integrated circuits is very expensive. New relaxation-based algorithms promise to reduce this cost by exploiting the properties of large networks. However, this speed improvement is not sufficient for the cost-effective analysis of very large circuits. While array processors have helped inprove the performance of circuit simulators, further improvement can be achieved by the use of special-purpose multiprocessors. In this paper, the implementation of a relaxation-based circuit simulation algorithm, called Iterated Timing Analaysis, on a multi-processor is described. Initial results indicate that this approach has a great deal of potential for reducing the cost of circuit simulation.
{"title":"A multiprocessor implementation of relaxation-based electrical circuit simulation","authors":"J. T. Deutsch, A. Newton","doi":"10.1145/62882.62940","DOIUrl":"https://doi.org/10.1145/62882.62940","url":null,"abstract":"The electrical circuit simulation of large integrated circuits is very expensive. New relaxation-based algorithms promise to reduce this cost by exploiting the properties of large networks. However, this speed improvement is not sufficient for the cost-effective analysis of very large circuits. While array processors have helped inprove the performance of circuit simulators, further improvement can be achieved by the use of special-purpose multiprocessors. In this paper, the implementation of a relaxation-based circuit simulation algorithm, called Iterated Timing Analaysis, on a multi-processor is described. Initial results indicate that this approach has a great deal of potential for reducing the cost of circuit simulation.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133444595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Critical path tracing determines fault detection without explicit. fault simulation. It appears to be a more efficient alternative to conventional methods.
关键路径跟踪确定了不显式的故障检测。故障模拟。这似乎是一种比传统方法更有效的替代方法。
{"title":"Critical path tracing - an alternative to fault simulation","authors":"M. Abramovici, P. R. Menon, David T. Miller","doi":"10.1145/62882.62938","DOIUrl":"https://doi.org/10.1145/62882.62938","url":null,"abstract":"Critical path tracing determines fault detection without explicit. fault simulation. It appears to be a more efficient alternative to conventional methods.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1984-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121823491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In MOS integrated circuits, signals may propagate between stages with fanout. The exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally simple are presented in this paper. The results can be used 1) to bound the delay, given the signal threshold, or 2) to bound the signal voltage, given a delay time, or 3) certify that a circuit is "fast enough," given both the maximum delay and the voltage threshold.
{"title":"Signal delay in RC tree networks","authors":"J. Rubinstein, P. Penfield, M. Horowitz","doi":"10.1145/62882.62932","DOIUrl":"https://doi.org/10.1145/62882.62932","url":null,"abstract":"In MOS integrated circuits, signals may propagate between stages with fanout. The exact calculation of signal delay through such networks is difficult. However, upper and lower bounds for delay that are computationally simple are presented in this paper. The results can be used 1) to bound the delay, given the signal threshold, or 2) to bound the signal voltage, given a delay time, or 3) certify that a circuit is \"fast enough,\" given both the maximum delay and the voltage threshold.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114579797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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