Giovanni De Picheli, Albert Sangiovanni-Vincentelli
Programmable Logic Arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.
{"title":"Pleasure: a computer program for simple/multiple constrained unconstrained folding of programmable logic arrays","authors":"Giovanni De Picheli, Albert Sangiovanni-Vincentelli","doi":"10.1145/62882.62913","DOIUrl":"https://doi.org/10.1145/62882.62913","url":null,"abstract":"Programmable Logic Arrays are important building blocks of VLSI circuits and systems. We address the problem of optimizing the silicon area and the performances of large logic arrays. In particular we describe a general method for compacting a logic array defined as multiple row and column folding and we address the problem of interconnecting a PLA to the outside circuitry. We define a constrained optimization problem to achieve minimal silicon area occupation with constrained positions of electrical inputs and outputs. We present a new computer program, PLEASURE, which implements several algorithms for multiple and/or constrained PLA folding.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134181824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The channel routing problem is a special care of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle. We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2 x n) grid and on consistent utilization of a "divide and conquer" approach. For the current implementation of the algorithm, the running time is proportional to N x n x log (m), where N is the number of nets, n is the length of the channel (number of columns) and m is the width of the channel (number of tracks). Traditional technological restrictions are assumed, i.e. net terminals are located on vertical grid lines, two wiring layers are available for interconnections - one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change. This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them - Deutsch's "difficult example" - was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks.
当互连必须在没有障碍物的矩形带内进行时，在位于矩形相对两侧的终端之间，通道布线问题是对导线布线问题的特别注意。我们在此提出了一种新的信道路由算法，该算法基于将问题简化为(2 x n)网格的情况，并基于“分而治之”方法的一致利用。对于当前算法的实现，运行时间与N x N x log (m)成正比，其中N为网的数量，N为通道的长度(列的数量)，m为通道的宽度(轨道的数量)。假设传统的技术限制，即网络终端位于垂直的网格线上，两层布线可用于互连-一层专门用于垂直段，另一层用于水平段，并且每层变化都引入过孔。该算法在布线质量上始终优于几种已知的路由器。我们在几个基准问题上测试了该算法。其中一个——Deutsch的“困难的例子”——只用19条水平布线轨道(这种情况下的绝对最小值)布线，而所有其他已知的路由器都需要20条或更多的轨道。
{"title":"Hierarchical channel router","authors":"Michael Burstein, R. Pelavin","doi":"10.1145/62882.62914","DOIUrl":"https://doi.org/10.1145/62882.62914","url":null,"abstract":"The channel routing problem is a special care of the wire routing problem when interconnections have to be performed within a rectangular strip having no obstructions, between terminals located on opposite sides of the rectangle. We present here a new channel routing algorithm, based on reduction of the problem to the case of a (2 x n) grid and on consistent utilization of a \"divide and conquer\" approach. For the current implementation of the algorithm, the running time is proportional to N x n x log (m), where N is the number of nets, n is the length of the channel (number of columns) and m is the width of the channel (number of tracks). Traditional technological restrictions are assumed, i.e. net terminals are located on vertical grid lines, two wiring layers are available for interconnections - one layer is used exclusively for vertical segments, another for horizontal and vias are introduced for each layer change. This algorithm consistently outperforms several known routers in quality of wiring. We tested the algorithm on several benchmark problems. One of them - Deutsch's \"difficult example\" - was routed with only 19 horizontal wiring tracks (the absolute minimum for this case), whereas all other known routers required 20 or more tracks.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1983-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128498289","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Seven placement algorithms - one constructive-initial placement algorithm and six iterative-improvement algorithms - were programmed and run on six problems ranging in size from 60 to 1300 modules. These problems included placing IC packs on a card, cards on a board and circuits on an LSI chip. It was found that the new force-directed pairwise relaxation algorithm was the best algorithm for the larger problems and was competitive with the other algorithms for the smaller problems. Other questions relating to placement strategies (such as, what are the advantages of constructive - initial start vs. random start and what is the best transformation of the placement problem to an associated quadratic assignment problem) are also answered.
{"title":"Some experimental results on placement techniques","authors":"M. Hanan, P. K. Wolff, B. J. Agule","doi":"10.1145/800146.804817","DOIUrl":"https://doi.org/10.1145/800146.804817","url":null,"abstract":"Seven placement algorithms - one constructive-initial placement algorithm and six iterative-improvement algorithms - were programmed and run on six problems ranging in size from 60 to 1300 modules. These problems included placing IC packs on a card, cards on a board and circuits on an LSI chip. It was found that the new force-directed pairwise relaxation algorithm was the best algorithm for the larger problems and was competitive with the other algorithms for the smaller problems. Other questions relating to placement strategies (such as, what are the advantages of constructive - initial start vs. random start and what is the best transformation of the placement problem to an associated quadratic assignment problem) are also answered.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126785249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.
{"title":"A “DOGLEG” channel router","authors":"D. Deutsch","doi":"10.1145/62882.62892","DOIUrl":"https://doi.org/10.1145/62882.62892","url":null,"abstract":"This paper presents an algorithm for interconnecting two sets of terminals across an intervening channel. It is assumed that the routing is done on two distinct levels with all horizontal paths being assigned to one level and all vertical paths to the other. Connections between the levels are made through contact windows. A single net may result in many horizontal and vertical segments. Experimental results indicate that this algorithm is very successful in routing channels that contain severe constraints. Usually, the routing is accomplished within one track of the mathematical lower bound. The routing algorithm presented here was developed as part of LTX, a computer-aided design system for integrated circuit layout and was implemented on an HP-2100 minicomputer. A typical channel (300 terminals, 100 nets) can be routed in less than 5 seconds. Routing results are presented both for polycell chips under development at Bell Laboratories and for examples that exist in the published literature. For the latter, reductions of 10% in the wiring area were typical.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"277 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1976-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114105028","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.
{"title":"Wire routing by optimizing channel assignment within large apertures","authors":"Akihiro Hashimoto, James G. Stevens","doi":"10.1145/800158.805069","DOIUrl":"https://doi.org/10.1145/800158.805069","url":null,"abstract":"The purpose of this paper is to introduce a new wire routing method for two layer printed circuit boards. This technique has been developed at the University of Illinois Center for Advanced Computation and has been programmed in ALGOL for a B5500 computer. The routing method is based on the newly developed channel assignment algorithm and requires many via holes. The primary goals of the method are short execution time and high wireability. Actual design specifications for ILLIAC IV Control Unit boards have been used to test the feasibility of the routing technique. Tests have shown that this algorithm is very fast and can handle large boards.","PeriodicalId":354586,"journal":{"name":"Papers on Twenty-five years of electronic design automation","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1971-06-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115712534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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