Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188726
M. Rathinasabapathy, Rangaswamy Nakkeeran
Adaptive transmission methods can potentially aid to achieve high data rates in Power Line Communication (PLC) system. To realize this potential, the transmitter needs accurate Channel State Information (CSI) for the upcoming transmission frame. In this paper a channel prediction scheme for Exponential Effective SINR Mapping (EESM) algorithm using Neural Network for OFDM system is proposed to select a suitable Modulation and Coding Scheme (MCS) for the current PLC channel realization which renders high throughput, while maintaining a certain target Packet Error Rate (PER). The Neural Network is trained to predict the future channel condition so as to perform adaptive transmission. The performances of three different neural network models are evaluated and it is observed that the proposed channel prediction method has performed more accurately than the conventional prediction systems. The processing time of EESM algorithm improved from 2.31 seconds to 0.26 seconds and thus proving fast adaptation.
{"title":"Adaptive transmission for Power Line Communication using neural networks","authors":"M. Rathinasabapathy, Rangaswamy Nakkeeran","doi":"10.1109/ICDCSYST.2012.6188726","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188726","url":null,"abstract":"Adaptive transmission methods can potentially aid to achieve high data rates in Power Line Communication (PLC) system. To realize this potential, the transmitter needs accurate Channel State Information (CSI) for the upcoming transmission frame. In this paper a channel prediction scheme for Exponential Effective SINR Mapping (EESM) algorithm using Neural Network for OFDM system is proposed to select a suitable Modulation and Coding Scheme (MCS) for the current PLC channel realization which renders high throughput, while maintaining a certain target Packet Error Rate (PER). The Neural Network is trained to predict the future channel condition so as to perform adaptive transmission. The performances of three different neural network models are evaluated and it is observed that the proposed channel prediction method has performed more accurately than the conventional prediction systems. The processing time of EESM algorithm improved from 2.31 seconds to 0.26 seconds and thus proving fast adaptation.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114918233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188718
A. T. Kenjale, P. Khandekar, A. Chitre
We present a sinusoidal single phase power clock generation method for low energy (adiabatic) circuits. In this paper radio frequency resonant DC-AC converter is proposed as power clock generator. We have also obtained square wave from RC oscillator consisting of cascaded NOT gates. This square wave and its inverted and delayed version are used as gate-drive signals for MOSFET switches those are used in the LC resonant circuit. A 2:1 MUX, implemented in Pass-transistor Adiabatic Logic (PAL) style, is operated from this power clock to illustrate power saving. It is observed that power dissipation of PAL 2:1 MUX is about 26 times lesser than that of conventional CMOS 2:1 MUX. If for 2:1 MUX, PAL logic is implemented in place of conventional CMOS logic, power saving per MUX that is achieved is about 96%. Also power dissipated in Power Clock is found to be equivalent to power dissipated in five CMOS 2:1 MUXs. 0.35μm technology is used for obtaining simulation results.
{"title":"Implementation and analysis of power clock generation method for adiabetic circuits","authors":"A. T. Kenjale, P. Khandekar, A. Chitre","doi":"10.1109/ICDCSYST.2012.6188718","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188718","url":null,"abstract":"We present a sinusoidal single phase power clock generation method for low energy (adiabatic) circuits. In this paper radio frequency resonant DC-AC converter is proposed as power clock generator. We have also obtained square wave from RC oscillator consisting of cascaded NOT gates. This square wave and its inverted and delayed version are used as gate-drive signals for MOSFET switches those are used in the LC resonant circuit. A 2:1 MUX, implemented in Pass-transistor Adiabatic Logic (PAL) style, is operated from this power clock to illustrate power saving. It is observed that power dissipation of PAL 2:1 MUX is about 26 times lesser than that of conventional CMOS 2:1 MUX. If for 2:1 MUX, PAL logic is implemented in place of conventional CMOS logic, power saving per MUX that is achieved is about 96%. Also power dissipated in Power Clock is found to be equivalent to power dissipated in five CMOS 2:1 MUXs. 0.35μm technology is used for obtaining simulation results.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115724729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188783
N. Anitha Christy, P. Karthigaikumar
A Low area Advanced Encryption Standard (AES)-128 bit algorithm is proposed in this paper. This technique is implemented using Composite Field Arithmetic (CFA) in byte substitution block, inverse byte substitution block and key expansion block of AES algorithm. The Composite field arithmetic technique provides a low area than the Look Up Table (LUT) in S-Box/Inverse S-Box. The proposed technique is presented with multistage sub-pipelined architecture in order to increase the throughput and its performance is compared with the previous FPGA implementations.
{"title":"FPGA implementation of AES algorithm using Composite Field Arithmetic","authors":"N. Anitha Christy, P. Karthigaikumar","doi":"10.1109/ICDCSYST.2012.6188783","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188783","url":null,"abstract":"A Low area Advanced Encryption Standard (AES)-128 bit algorithm is proposed in this paper. This technique is implemented using Composite Field Arithmetic (CFA) in byte substitution block, inverse byte substitution block and key expansion block of AES algorithm. The Composite field arithmetic technique provides a low area than the Look Up Table (LUT) in S-Box/Inverse S-Box. The proposed technique is presented with multistage sub-pipelined architecture in order to increase the throughput and its performance is compared with the previous FPGA implementations.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124681003","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188711
B. Das, M. Saha, G. Bhattacharya, B. Sikdar
The design inaccuracy (fault) in predictors can cause huge power loss in processor posing serious threat to the designers. The objective of the current analysis of fault impact on the processor power consumption is to devise a methodology for diagnosis of the faulty module in a branch predictor. It is effectively the first step for identification of DPL (design to avoid power loss) in a processor. Exhaustive analysis reveals that the undoubted diagnosis of design inaccuracies, that is effective for DPL, can be formalized in a TWO-LEVEL predictor by sensing the power drainage from processor.
{"title":"Evaluation of branch predictors targeting easeful diagnosis of design inaccuracies","authors":"B. Das, M. Saha, G. Bhattacharya, B. Sikdar","doi":"10.1109/ICDCSYST.2012.6188711","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188711","url":null,"abstract":"The design inaccuracy (fault) in predictors can cause huge power loss in processor posing serious threat to the designers. The objective of the current analysis of fault impact on the processor power consumption is to devise a methodology for diagnosis of the faulty module in a branch predictor. It is effectively the first step for identification of DPL (design to avoid power loss) in a processor. Exhaustive analysis reveals that the undoubted diagnosis of design inaccuracies, that is effective for DPL, can be formalized in a TWO-LEVEL predictor by sensing the power drainage from processor.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123330235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188731
R. Mitter, M. S. Priya
Chaotic maps have been widely used in data encryption. Various chaos map based encryption and decryption algorithms are used but are found to be insecure. Hence a new method is implemented based on BB (Brahmagupta-Bhaskara) equation which is combined with chaos to give a non linear dependency and thus improved security. This paper also improves security by changing chaotic sequence generators and permutation technique. The proposed algorithm is designed and realized using MATLAB and Xilinx ISE softwares.
{"title":"A highly secure cryptosystem for image encryption","authors":"R. Mitter, M. S. Priya","doi":"10.1109/ICDCSYST.2012.6188731","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188731","url":null,"abstract":"Chaotic maps have been widely used in data encryption. Various chaos map based encryption and decryption algorithms are used but are found to be insecure. Hence a new method is implemented based on BB (Brahmagupta-Bhaskara) equation which is combined with chaos to give a non linear dependency and thus improved security. This paper also improves security by changing chaotic sequence generators and permutation technique. The proposed algorithm is designed and realized using MATLAB and Xilinx ISE softwares.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123425327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188649
N. Suma, V. S. Nagaraja, S. Pinjare, K. Neethu, K. Sudharshan
This presents a MEMS thermal actuator which has been fabricated using SOI MUMPs technology. These thermal actuators are used in micro legs, micro grippers, micro positioning applications etc. The operating principle is based on the asymmetrical thermal expansion of the beams with different lengths and cross sections. By applying voltage (current) on different contact pads, and different beams are heated, thereby the microactuator can produce bilateral motion in plane or out-of-plane. The narrow or hot arm heats up and expands more than the wide or cold arm deflecting the device toward the cold arm. Thermal actuators are more power efficient than electrostatic actuators. The work carries the characterization details of the thermal actuator fabricated. It contains the I-V characteristics and voltage versus displacement details.
{"title":"Design and characterization of MEMS thermal actuator","authors":"N. Suma, V. S. Nagaraja, S. Pinjare, K. Neethu, K. Sudharshan","doi":"10.1109/ICDCSYST.2012.6188649","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188649","url":null,"abstract":"This presents a MEMS thermal actuator which has been fabricated using SOI MUMPs technology. These thermal actuators are used in micro legs, micro grippers, micro positioning applications etc. The operating principle is based on the asymmetrical thermal expansion of the beams with different lengths and cross sections. By applying voltage (current) on different contact pads, and different beams are heated, thereby the microactuator can produce bilateral motion in plane or out-of-plane. The narrow or hot arm heats up and expands more than the wide or cold arm deflecting the device toward the cold arm. Thermal actuators are more power efficient than electrostatic actuators. The work carries the characterization details of the thermal actuator fabricated. It contains the I-V characteristics and voltage versus displacement details.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126666915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188720
I. F. Princess Nesamani, P. Sindhu, M. Manikandan, V. Lakshmiprabha, D. Nirmal
The MG FinFETs are designed and its results are compared with the polysiliconFinFETs. The 6T SRAM cell is designed using both gate materials and their variations will be analysed. The 20nm tied gate device is compared with independent gate. The SRAM cell stability enhancement is improved using the IDG-FinFETs by controlling the individual Vth for the PG and the flipflop of the SRAM cell. By the Vth-controllability of the independent-double-gate (IDG) FinFETs the variation problems in SRAMperformance is reduced.
{"title":"Mixed mode simulation of SRAM FinFETS","authors":"I. F. Princess Nesamani, P. Sindhu, M. Manikandan, V. Lakshmiprabha, D. Nirmal","doi":"10.1109/ICDCSYST.2012.6188720","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188720","url":null,"abstract":"The MG FinFETs are designed and its results are compared with the polysiliconFinFETs. The 6T SRAM cell is designed using both gate materials and their variations will be analysed. The 20nm tied gate device is compared with independent gate. The SRAM cell stability enhancement is improved using the IDG-FinFETs by controlling the individual Vth for the PG and the flipflop of the SRAM cell. By the Vth-controllability of the independent-double-gate (IDG) FinFETs the variation problems in SRAMperformance is reduced.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126222956","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188661
B. Sen, J. Das, B. Sikdar
Reversible logic is gaining importance for its ultra low power consumption. It has wide application in quantum computing, nanotechnology and optical computing. In this work, we propose a DFT (design for test) methodology for reversible logic blocks to enable online fault detection. A concurrent error detection technique, based on parity is introduced for the online testing. The methodology proposed for converting a 3×3 reversible gate into an online testable circuit ensures detection of all the stuck-at faults, bit flip faults and almost all multiple bit faults in logic blocks.
{"title":"A DFT methodology targeting online testing of reversible circuit","authors":"B. Sen, J. Das, B. Sikdar","doi":"10.1109/ICDCSYST.2012.6188661","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188661","url":null,"abstract":"Reversible logic is gaining importance for its ultra low power consumption. It has wide application in quantum computing, nanotechnology and optical computing. In this work, we propose a DFT (design for test) methodology for reversible logic blocks to enable online fault detection. A concurrent error detection technique, based on parity is introduced for the online testing. The methodology proposed for converting a 3×3 reversible gate into an online testable circuit ensures detection of all the stuck-at faults, bit flip faults and almost all multiple bit faults in logic blocks.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121726441","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188728
A. K. Sinha, D. Caviglia, P. Gaur
In this paper we presents a signal conditioning unit working at single supply. The unit consists of high pass filter, buffer and a cascaded stage of low pass filter with amplifier. The order of high pass filter and low pass filter was first and second respectively. The unit was realized by using minimum off-the-shelf components through effective sizing rules proposed in this paper. Software simulation was done to ascertain the working of conditioning unit according to the specifications. A hardware prototype has been made to demonstrate the working of the unit.
{"title":"Design of an advanced signal conditioning unit for sensor with reduced off-the-shelf components","authors":"A. K. Sinha, D. Caviglia, P. Gaur","doi":"10.1109/ICDCSYST.2012.6188728","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188728","url":null,"abstract":"In this paper we presents a signal conditioning unit working at single supply. The unit consists of high pass filter, buffer and a cascaded stage of low pass filter with amplifier. The order of high pass filter and low pass filter was first and second respectively. The unit was realized by using minimum off-the-shelf components through effective sizing rules proposed in this paper. Software simulation was done to ascertain the working of conditioning unit according to the specifications. A hardware prototype has been made to demonstrate the working of the unit.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131139619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188689
N. Valliammal, S. Geethalakshmi
Plant recognition is very demanding in biology and agriculture as new plant discovery and the computerization of the management of plant species become more popular. Developing an automatic plant recognition system becomes a very challenging task. Image pre-processing techniques, such as filtering for noise reduction and enhancement of the image is highly essential. The computerized plant recognition mainly suppresses noise in the input image leading to stable feature extraction of plants. By applying Gaussian noise, the leaf image appears blurred, due to which the edges of the leaf vein is not clearly visible. Speckle noise occurrence is often undesirable, and also very dangerously causes damage to the leaf shape and structure. So, the ultimate goal is to develop a system where both multiple Gaussian and speckle noise can be removed and restored so that the image becomes noise free and produces clear vein and shape of the leaf which is highly essential for further process. Hybrid filter method is developed to remove the noise, enhance the quality of image and thereby produces better results compared to other traditional filters. Different parametric metrics are used to evaluate the performance of the hybrid filter and proves by giving suitable results when compared to other traditional filters.
{"title":"Multiple noise reduction using hybrid method for leaf recognition","authors":"N. Valliammal, S. Geethalakshmi","doi":"10.1109/ICDCSYST.2012.6188689","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188689","url":null,"abstract":"Plant recognition is very demanding in biology and agriculture as new plant discovery and the computerization of the management of plant species become more popular. Developing an automatic plant recognition system becomes a very challenging task. Image pre-processing techniques, such as filtering for noise reduction and enhancement of the image is highly essential. The computerized plant recognition mainly suppresses noise in the input image leading to stable feature extraction of plants. By applying Gaussian noise, the leaf image appears blurred, due to which the edges of the leaf vein is not clearly visible. Speckle noise occurrence is often undesirable, and also very dangerously causes damage to the leaf shape and structure. So, the ultimate goal is to develop a system where both multiple Gaussian and speckle noise can be removed and restored so that the image becomes noise free and produces clear vein and shape of the leaf which is highly essential for further process. Hybrid filter method is developed to remove the noise, enhance the quality of image and thereby produces better results compared to other traditional filters. Different parametric metrics are used to evaluate the performance of the hybrid filter and proves by giving suitable results when compared to other traditional filters.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133852329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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