Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188802
S. K. Shome, Abhinav Ahesh, Durgesh Kr Gupta, Srk Vadali
A large number of efficient fixed geometry Fast Fourier Transform (FFT) VLSI designs have been developed till date. We propose a novel architectural design for a highly programmable Radix-2 Decimation-In-Frequency (DIF) FFT processor using relatively simple memory addressing logic. The 5-level programmability of the design, allows computation of 64, 128, 256, 512 or 1024 point FFT of the input signal, depending on application. Besides, the architecture provides the flexibility of computing an N point FFT for M length data (N >; M), i.e. with an enhanced resolution also. A complete system flow of the entire FFT architecture along with twiddle factor multiplication, bit reversal and a detailed efficient Address Generation Block (AGB) are also presented. The address generation methodology adopted for the proposed design is based on counters and multiplexers which significantly saves the hardware as well as the latency requirement introduced thereon.
{"title":"Architectural design of a highly programmable Radix-2 FFT processor with efficient addressing logic","authors":"S. K. Shome, Abhinav Ahesh, Durgesh Kr Gupta, Srk Vadali","doi":"10.1109/ICDCSYST.2012.6188802","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188802","url":null,"abstract":"A large number of efficient fixed geometry Fast Fourier Transform (FFT) VLSI designs have been developed till date. We propose a novel architectural design for a highly programmable Radix-2 Decimation-In-Frequency (DIF) FFT processor using relatively simple memory addressing logic. The 5-level programmability of the design, allows computation of 64, 128, 256, 512 or 1024 point FFT of the input signal, depending on application. Besides, the architecture provides the flexibility of computing an N point FFT for M length data (N >; M), i.e. with an enhanced resolution also. A complete system flow of the entire FFT architecture along with twiddle factor multiplication, bit reversal and a detailed efficient Address Generation Block (AGB) are also presented. The address generation methodology adopted for the proposed design is based on counters and multiplexers which significantly saves the hardware as well as the latency requirement introduced thereon.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188690
R. Singh, N. Chauhan, S. Mishra
This paper presents an average current-mode controller with a feedback clamp circuit based optimal bidirectional battery charger for automotive applications. The proposed controller forces the converter to work as a controlled current source when the battery state-of-charge (SOC) is below a predefined reference level and automatically reverts to controlled voltage source when the battery SOC exceeds the predefined reference level. The controller avoids the use of independent voltage and current loops and extra switching circuits to achieve current clamping in the proposed implementation is not based on saturation of the error amplifier, it is alway feedback controlled and the transition between constant current to constant voltage mode is smooth. The proposed implementation adapts well to Reflex™ charging technique. Experimental and simulation results are presented to verify the proposed algorithm.
{"title":"A novel average current-mode controller based optimal battery charger for automotive applications","authors":"R. Singh, N. Chauhan, S. Mishra","doi":"10.1109/ICDCSYST.2012.6188690","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188690","url":null,"abstract":"This paper presents an average current-mode controller with a feedback clamp circuit based optimal bidirectional battery charger for automotive applications. The proposed controller forces the converter to work as a controlled current source when the battery state-of-charge (SOC) is below a predefined reference level and automatically reverts to controlled voltage source when the battery SOC exceeds the predefined reference level. The controller avoids the use of independent voltage and current loops and extra switching circuits to achieve current clamping in the proposed implementation is not based on saturation of the error amplifier, it is alway feedback controlled and the transition between constant current to constant voltage mode is smooth. The proposed implementation adapts well to Reflex™ charging technique. Experimental and simulation results are presented to verify the proposed algorithm.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122441197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188704
D. Nirmal, S. Varughese, D. Joy, F. Princess, P. V. Kumar
GaN material has a very good potential in today's semiconductor world because of its highlighted characters like wide band gap and high saturation velocity. The combined effect of piezoelectric polarization and spontaneous polarization provides a high electron concentration called 2DEG in Al0.3Ga0.7N/GaN interface which allows higher mobility of carriers in interface than in bulk GaN material. 2-D simulation of power Al0.3Ga0.7N/GaNHFET device is carried out here and the effect of different parameters are analysed and studied using Sentaurus TCAD software. Prameters like IdVg, IdVd, gmetc are obtained. Several analysis are done with source to gate length, passivation layer etc.
{"title":"Design and simulation of AlGaN/GaN HFET","authors":"D. Nirmal, S. Varughese, D. Joy, F. Princess, P. V. Kumar","doi":"10.1109/ICDCSYST.2012.6188704","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188704","url":null,"abstract":"GaN material has a very good potential in today's semiconductor world because of its highlighted characters like wide band gap and high saturation velocity. The combined effect of piezoelectric polarization and spontaneous polarization provides a high electron concentration called 2DEG in Al<sub>0.3</sub>Ga<sub>0.7</sub>N/GaN interface which allows higher mobility of carriers in interface than in bulk GaN material. 2-D simulation of power Al<sub>0.3</sub>Ga<sub>0.7</sub>N/GaNHFET device is carried out here and the effect of different parameters are analysed and studied using Sentaurus TCAD software. Prameters like I<sub>d</sub>V<sub>g</sub>, I<sub>d</sub>V<sub>d</sub>, g<sub>m</sub>etc are obtained. Several analysis are done with source to gate length, passivation layer etc.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123110346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188653
P. T. Rao, P. S. Kumar, C. Ramesh, Y. M. Babu
Pulse compression technique is most widely used in Radar signal processing applications. For better pulse compression, peak signal to side lobe ratio i.e. merit factor should be as high as possible so that the unwanted clutter gets suppressed. To achieve the peaky main lobes and low side lobes, phase coded pulse compression codes are widely used. The simple phase code is obtained from the Binary phase coding. Matched filtering of biphase coded radar signals create unwanted side lobes which may mask important information. Hence the study of poly phase codes like Six phase pulse compression code is needed and the implementation techniques are carried out since the poly phase codes have low sidelobes and are better Doppler tolerant. The VLSI architectures for Phase coded Pulse compression systems described in the literature generate the pulse compression sequences with limited speed and consume more area on chip. But the real time implementation needs optimization of speed, area and power consumption. This paper concentrates on the design of an optimized model which can reduce these constraints. The proposed VLSI architecture can efficiently generate Six Phase pulse compression sequences while improving some of the parameters like area and speed when compared to previous methods. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability.
{"title":"A novel VLSI architecture for generation of Six Phase pulse compression sequences","authors":"P. T. Rao, P. S. Kumar, C. Ramesh, Y. M. Babu","doi":"10.1109/ICDCSYST.2012.6188653","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188653","url":null,"abstract":"Pulse compression technique is most widely used in Radar signal processing applications. For better pulse compression, peak signal to side lobe ratio i.e. merit factor should be as high as possible so that the unwanted clutter gets suppressed. To achieve the peaky main lobes and low side lobes, phase coded pulse compression codes are widely used. The simple phase code is obtained from the Binary phase coding. Matched filtering of biphase coded radar signals create unwanted side lobes which may mask important information. Hence the study of poly phase codes like Six phase pulse compression code is needed and the implementation techniques are carried out since the poly phase codes have low sidelobes and are better Doppler tolerant. The VLSI architectures for Phase coded Pulse compression systems described in the literature generate the pulse compression sequences with limited speed and consume more area on chip. But the real time implementation needs optimization of speed, area and power consumption. This paper concentrates on the design of an optimized model which can reduce these constraints. The proposed VLSI architecture can efficiently generate Six Phase pulse compression sequences while improving some of the parameters like area and speed when compared to previous methods. The VLSI architecture is implemented on the Field Programmable Gate Array (FPGA) as it provides the flexibility of reconfigurability and reprogrammability.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"403 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115919915","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188716
A. H. M. Ripon, A. A. Siddique, S. M. Mustafa, A. B. M. Rafi Sazzad
Solar cell has an enormous developing capacity as kind of green renewable energy source. Nevertheless, accompanied by some losses such as light reflection loss, recombination loss, grid shadowing loss, and low carrier concentration, the energy conversion efficiency of a solar cell remains unsatisfactory. A lot of research work has been done and yet been continued in order to enhance the solar cell efficiency. Among them, surface texturisation is quite enough succeeded in reduction of reflectance through light trapping in the cell and thence higher light absorption. Again, Emitter-Wrap-Through back contact cell technology paves the way to reduce grid loss as well as double-sided carrier collection and therefore increases short circuit current. However, at present, Texturization and Emitter-Wrap-Through (EWT) technology are used individually. In this paper we promote a possible solar cell design by combining these two features along with a PC1D software simulation to enhance the efficiency of solar cell.
{"title":"Efficiency enhancement of solar cell: Fusion of texturisation and back contact Emitter-Wrap-Through modeling","authors":"A. H. M. Ripon, A. A. Siddique, S. M. Mustafa, A. B. M. Rafi Sazzad","doi":"10.1109/ICDCSYST.2012.6188716","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188716","url":null,"abstract":"Solar cell has an enormous developing capacity as kind of green renewable energy source. Nevertheless, accompanied by some losses such as light reflection loss, recombination loss, grid shadowing loss, and low carrier concentration, the energy conversion efficiency of a solar cell remains unsatisfactory. A lot of research work has been done and yet been continued in order to enhance the solar cell efficiency. Among them, surface texturisation is quite enough succeeded in reduction of reflectance through light trapping in the cell and thence higher light absorption. Again, Emitter-Wrap-Through back contact cell technology paves the way to reduce grid loss as well as double-sided carrier collection and therefore increases short circuit current. However, at present, Texturization and Emitter-Wrap-Through (EWT) technology are used individually. In this paper we promote a possible solar cell design by combining these two features along with a PC1D software simulation to enhance the efficiency of solar cell.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"199 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131375579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188679
P. Manikandan, R. Mathew
A class-E power amplifier with modified driver for WLAN and Bluetooth applications is presented in this paper. It is shown that a parallel class-E power amplifier gives better output power at minimum input power levels compared to a conventional class-E power amplifier. A new modified driver stage is proposed which drives the power amplifier efficiently. Negative capacitance concept is implemented to reduce parasitic capacitances at the driver output node to shape the driver output voltage. The negative capacitance is implemented without external circuit and the driver circuit is fed with less than 5dBm input power at 2.4GHz operating frequency. The power amplifier gain is more than 20dBm with 40% PAE at 2.4GHz. The power amplifier and the modified driver circuitry were implemented in 0.18-μm UMC CMOS technology using Cadence tool.
{"title":"Design of CMOS class-E power amplifier for WLAN and bluetooth applications","authors":"P. Manikandan, R. Mathew","doi":"10.1109/ICDCSYST.2012.6188679","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188679","url":null,"abstract":"A class-E power amplifier with modified driver for WLAN and Bluetooth applications is presented in this paper. It is shown that a parallel class-E power amplifier gives better output power at minimum input power levels compared to a conventional class-E power amplifier. A new modified driver stage is proposed which drives the power amplifier efficiently. Negative capacitance concept is implemented to reduce parasitic capacitances at the driver output node to shape the driver output voltage. The negative capacitance is implemented without external circuit and the driver circuit is fed with less than 5dBm input power at 2.4GHz operating frequency. The power amplifier gain is more than 20dBm with 40% PAE at 2.4GHz. The power amplifier and the modified driver circuitry were implemented in 0.18-μm UMC CMOS technology using Cadence tool.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131405238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188795
M. Nagaraju, M. Rakesh
In this paper, we present the ASIC Implementation of OFDM transceiver based on WLAN (IEEE 802.11a) for better optimized power and timing. RTL synthesis of transmitter and receiver blocks without (Viterbi) decoder in the receiver is presented here. While the Punctured Convolution Coding is used to improve the data rate, Quadrature Amplitude modulation improves bandwidth. OFDM is implemented using FFT/IFFT processor. Using separate clocks for modulator/demodulator and transmitter/receiver improves data rate. Timing constraints are met by introducing retiming and Clock Scheduling. Multi-VTH principles and Clock gating are applied to reduce power consumption. The proposed design has been implemented in TSMC 0.18 μm technology. The total area of the chip occupied 2.4×2.4 mm2 and the dynamic power consumption is 72mW, data rate at 91Mbps and 1.8V supply voltage. Our ASIC achieves a considerable performance gain as well support about double data rate as compared to the conventional IEEE 802.11a WLANs.
{"title":"High-speed and low-power ASIC implementation of OFDM transceiver based on WLAN (IEEE 802.11a)","authors":"M. Nagaraju, M. Rakesh","doi":"10.1109/ICDCSYST.2012.6188795","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188795","url":null,"abstract":"In this paper, we present the ASIC Implementation of OFDM transceiver based on WLAN (IEEE 802.11a) for better optimized power and timing. RTL synthesis of transmitter and receiver blocks without (Viterbi) decoder in the receiver is presented here. While the Punctured Convolution Coding is used to improve the data rate, Quadrature Amplitude modulation improves bandwidth. OFDM is implemented using FFT/IFFT processor. Using separate clocks for modulator/demodulator and transmitter/receiver improves data rate. Timing constraints are met by introducing retiming and Clock Scheduling. Multi-VTH principles and Clock gating are applied to reduce power consumption. The proposed design has been implemented in TSMC 0.18 μm technology. The total area of the chip occupied 2.4×2.4 mm2 and the dynamic power consumption is 72mW, data rate at 91Mbps and 1.8V supply voltage. Our ASIC achieves a considerable performance gain as well support about double data rate as compared to the conventional IEEE 802.11a WLANs.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126905152","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188750
D. Balodi, C. Saha, P. A. Govidacharyulu
The importances of MOSFET parameter extraction process along with the requirements for good optimization strategy to obtain better modeling results are discussed. Scope for achieving the flexibilities in parameter extraction process and strategy formation has also been discussed with the example of BSIM MOSFET model in 0.8 μm CMOS technology and it is argued that with the poor extraction strategy, even the more powerful BSIM3 (Level-49) model produces the comparable results to that of BSIM (Level-13) model. Finally the BSIM (Level-13 and Level-49) modeling efforts for various geometry devices are shown in comparative manner which are followed by qualitative analysis to conclude the important aspects of these models with optimization effects.
{"title":"Effect of parameter optimization effort over mosfet models' performances in analog circuits' simulation","authors":"D. Balodi, C. Saha, P. A. Govidacharyulu","doi":"10.1109/ICDCSYST.2012.6188750","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188750","url":null,"abstract":"The importances of MOSFET parameter extraction process along with the requirements for good optimization strategy to obtain better modeling results are discussed. Scope for achieving the flexibilities in parameter extraction process and strategy formation has also been discussed with the example of BSIM MOSFET model in 0.8 μm CMOS technology and it is argued that with the poor extraction strategy, even the more powerful BSIM3 (Level-49) model produces the comparable results to that of BSIM (Level-13) model. Finally the BSIM (Level-13 and Level-49) modeling efforts for various geometry devices are shown in comparative manner which are followed by qualitative analysis to conclude the important aspects of these models with optimization effects.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114310017","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188681
M. Santosh, K. C. Behera, S. Bose
The proposed read-out circuit has a traditional two stage Operational amplifier (op-amp), a Gilbert cell and a Difference amplifier. The sensitivity of the sensor, known as primary with pressure variation can be increased with the help of an additional sensor, which act as a reference sensor. Here, we have used a current bias to increase the sensitivity. The current through both the sensors are controlled by a composite resistor and an op-amp having 70db PSRR. The advantage of using composite resistor is its immunity to process variation as well as stabilization of current sourced into the sensors. The simulation of the sensor along with the read out bias circuit is performed in cadence environment with AMS (Austria Microsystems) 0.35 μm technology design kit. The simulation for in-house fabricated MEMS pressure sensor is done by macro-modeling. The simulated output of the read-out circuit along with the macro model of sensor is showing almost rail-to rail output swing (around 3 V for a 3.3 V supply). The total power dissipation (including the sensor) is less than 10 mW for a 3 mA bias current. The total area occupied by the readout circuit is less than 0.04 mm2. MEMS pressure sensor was fabricated by SNG group of CEERI, fabricated sensor occupies 0.14 mm2 of area.
{"title":"Design of an on chip read-out circuit for piezo-resistive MEMS pressure sensor","authors":"M. Santosh, K. C. Behera, S. Bose","doi":"10.1109/ICDCSYST.2012.6188681","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188681","url":null,"abstract":"The proposed read-out circuit has a traditional two stage Operational amplifier (op-amp), a Gilbert cell and a Difference amplifier. The sensitivity of the sensor, known as primary with pressure variation can be increased with the help of an additional sensor, which act as a reference sensor. Here, we have used a current bias to increase the sensitivity. The current through both the sensors are controlled by a composite resistor and an op-amp having 70db PSRR. The advantage of using composite resistor is its immunity to process variation as well as stabilization of current sourced into the sensors. The simulation of the sensor along with the read out bias circuit is performed in cadence environment with AMS (Austria Microsystems) 0.35 μm technology design kit. The simulation for in-house fabricated MEMS pressure sensor is done by macro-modeling. The simulated output of the read-out circuit along with the macro model of sensor is showing almost rail-to rail output swing (around 3 V for a 3.3 V supply). The total power dissipation (including the sensor) is less than 10 mW for a 3 mA bias current. The total area occupied by the readout circuit is less than 0.04 mm2. MEMS pressure sensor was fabricated by SNG group of CEERI, fabricated sensor occupies 0.14 mm2 of area.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114758002","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188755
Jackuline Moni, Anu K. Priyadharsini
A One-bit adder is designed using modified complementary pass transistor logic (MCPL). The proposed adder is implemented in 4×4 bit high radix multiplier to achieve high speed, low area and less power dissipation. This circuit is simulated by using DSCH2 schematic design tool and layout is taken by Microwind 2 VLSI layout CAD tool, and the analysis is done by using the BSIM4 analyzer. The 4×4 bit high radix multiplier is then compared with Carry Save Array multiplier (CSA multiplier), Baugh-Wooley multiplier, and high radix multiplier to show the better performance in terms of power, area and delay.
{"title":"Design of low-power and high performance radix-4 multiplier","authors":"Jackuline Moni, Anu K. Priyadharsini","doi":"10.1109/ICDCSYST.2012.6188755","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188755","url":null,"abstract":"A One-bit adder is designed using modified complementary pass transistor logic (MCPL). The proposed adder is implemented in 4×4 bit high radix multiplier to achieve high speed, low area and less power dissipation. This circuit is simulated by using DSCH2 schematic design tool and layout is taken by Microwind 2 VLSI layout CAD tool, and the analysis is done by using the BSIM4 analyzer. The 4×4 bit high radix multiplier is then compared with Carry Save Array multiplier (CSA multiplier), Baugh-Wooley multiplier, and high radix multiplier to show the better performance in terms of power, area and delay.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116024966","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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