Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188684
R. Sivarajan, A. Venkatesan, L. Vanitha
In this paper, a new method is proposed to improve the diversity order of the wireless network to combat the fading in the channel. The network is assumed to have multiple sources, multiple relays, and one common destination. The relay in the network is assumed to use the `decode and forward' protocol. The relay, with binary network code (BNC), to transmit the message from source to destination, the network achieves the diversity order of K with K relays. The network is proposed with finite field network code (FFNC) with orthogonal transmission i.e., each user transmit the message in single time slot and it is termed as orthogonal Minimum Distance Separable (MDS) FFNC protocol. Instead of separately retransmitting each source message, if the relay employs a class of spectrally efficient FFNC codes to assist the sources, it is termed as non orthogonal MDS FFNC protocol. Fully orthogonal or fully non orthogonal transmission among sources/ relays does not necessarily provide optimized Diversity Multiplexing tradeoff (DMT) performance. Thus, the transmission protocol that divides the sources and relays into individual clusters, termed as cluster MDS FFNC, is proposed. The nodes within one cluster transmit non- orthogonally while the transmissions of different cluster span orthogonal channels. The DMT for orthogonal, non orthogonal and clustering strategies are compared.
{"title":"Analysis of DMT in multi-user wireless network using orthogonal, non-orthogonal and cluster MDS FFNC","authors":"R. Sivarajan, A. Venkatesan, L. Vanitha","doi":"10.1109/ICDCSYST.2012.6188684","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188684","url":null,"abstract":"In this paper, a new method is proposed to improve the diversity order of the wireless network to combat the fading in the channel. The network is assumed to have multiple sources, multiple relays, and one common destination. The relay in the network is assumed to use the `decode and forward' protocol. The relay, with binary network code (BNC), to transmit the message from source to destination, the network achieves the diversity order of K with K relays. The network is proposed with finite field network code (FFNC) with orthogonal transmission i.e., each user transmit the message in single time slot and it is termed as orthogonal Minimum Distance Separable (MDS) FFNC protocol. Instead of separately retransmitting each source message, if the relay employs a class of spectrally efficient FFNC codes to assist the sources, it is termed as non orthogonal MDS FFNC protocol. Fully orthogonal or fully non orthogonal transmission among sources/ relays does not necessarily provide optimized Diversity Multiplexing tradeoff (DMT) performance. Thus, the transmission protocol that divides the sources and relays into individual clusters, termed as cluster MDS FFNC, is proposed. The nodes within one cluster transmit non- orthogonally while the transmissions of different cluster span orthogonal channels. The DMT for orthogonal, non orthogonal and clustering strategies are compared.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133475386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188643
Md Imran Momtaz, M. Hassan
In this work, a closed form equation for minority carrier density p(x) is obtained based on a proposed relation between electric field and hole profile p(x). Two important parameters of a Schottky Barrier Diode (SBD) namely storage time and injection ratio can be obtained from p(x). In previous analytical works, such study was done for SBDs with uniformly doped Si. The closed form solution for p(x) is applicable for all levels of injection. The effect of low-high (n-n+) junction is also studied in this work. Present analysis shows that minority current, charge storage time and current injection ratio depend on the logarithmic slope and effective surface recombination velocity.
{"title":"Analytical expression for storage time and injection ratio of a non-uniformly doped n-Si SBD","authors":"Md Imran Momtaz, M. Hassan","doi":"10.1109/ICDCSYST.2012.6188643","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188643","url":null,"abstract":"In this work, a closed form equation for minority carrier density p(x) is obtained based on a proposed relation between electric field and hole profile p(x). Two important parameters of a Schottky Barrier Diode (SBD) namely storage time and injection ratio can be obtained from p(x). In previous analytical works, such study was done for SBDs with uniformly doped Si. The closed form solution for p(x) is applicable for all levels of injection. The effect of low-high (n-n+) junction is also studied in this work. Present analysis shows that minority current, charge storage time and current injection ratio depend on the logarithmic slope and effective surface recombination velocity.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121735136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188757
S. Yadav, A. Srivastava, J. Rahul, Kamal Kishor Jha
In the present work we have introduced generic new type of Double Gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET), with Dual Insulator (DI) architecture. The gate insulator of the Dual Insulator Double Gate (DIDG) MOSFET consists of two laterally placed insulator materials with different dielectric constants. This novel gate insulator structure takes advantage of difference of dielectric constants in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel DIDG MOSFET, opposite for p-channel DIDG MOSFET), resulting in a more rapid acceleration of charge carriers in the channel near the source and a screening effect near drain region of channel due to which device shows significant suppression in the drain conductance and a higher drain current than conventional Double Gate MOSFET.
{"title":"TCAD assessment of nonconventional Dual Insulator Double Gate MOSFET","authors":"S. Yadav, A. Srivastava, J. Rahul, Kamal Kishor Jha","doi":"10.1109/ICDCSYST.2012.6188757","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188757","url":null,"abstract":"In the present work we have introduced generic new type of Double Gate Metal Oxide Semiconductor Field Effect Transistor (DG MOSFET), with Dual Insulator (DI) architecture. The gate insulator of the Dual Insulator Double Gate (DIDG) MOSFET consists of two laterally placed insulator materials with different dielectric constants. This novel gate insulator structure takes advantage of difference of dielectric constants in such a way that the threshold voltage near the source is more positive than that near the drain (for n-channel DIDG MOSFET, opposite for p-channel DIDG MOSFET), resulting in a more rapid acceleration of charge carriers in the channel near the source and a screening effect near drain region of channel due to which device shows significant suppression in the drain conductance and a higher drain current than conventional Double Gate MOSFET.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125802500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188751
M. Vanitha, R. Sakthivel, S. Subha
This paper provides an efficient VLSI architecture to increase the throughput and security of the Advanced Encryption Standard (AES) Algorithm. The existing architecture provide the Look up Table technique for the Subbytes and inverse Subbytes transformation used in AES algorithm, our proposed technique uses combinational circuit and pipelining technique which increase the throughput and reduce the delay. This design proposes a new technique for implementing the S-box, which decides the speed and power of AES architecture and the basic components of this architecture is made completely fault detectable by using pseudo-nMOS technology and thereby increases the security of this system. This AES design was modeled using Verilog HDL and synthesized using TSMC's 90 nm standard cell library with RTL Compiler, and physical design implementation was done using SOC Encounter and thereby achieved a through put of 58.18 Gbps after detailed routing. The basic security of the system is validated by using Cadence Virtuoso in the transistor level design.
{"title":"Highly secured high throughput VLSI architecture for AES algorithm","authors":"M. Vanitha, R. Sakthivel, S. Subha","doi":"10.1109/ICDCSYST.2012.6188751","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188751","url":null,"abstract":"This paper provides an efficient VLSI architecture to increase the throughput and security of the Advanced Encryption Standard (AES) Algorithm. The existing architecture provide the Look up Table technique for the Subbytes and inverse Subbytes transformation used in AES algorithm, our proposed technique uses combinational circuit and pipelining technique which increase the throughput and reduce the delay. This design proposes a new technique for implementing the S-box, which decides the speed and power of AES architecture and the basic components of this architecture is made completely fault detectable by using pseudo-nMOS technology and thereby increases the security of this system. This AES design was modeled using Verilog HDL and synthesized using TSMC's 90 nm standard cell library with RTL Compiler, and physical design implementation was done using SOC Encounter and thereby achieved a through put of 58.18 Gbps after detailed routing. The basic security of the system is validated by using Cadence Virtuoso in the transistor level design.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126074589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188772
Mohd Umar Farooq, K. Khan, M. Pasha
Over the years, the usefulness of wireless mobile ad-hoc networks and vehicular ad-hoc networks has been well documented. A lot of effort has gone in to the study of integration of vehicular ad-hoc networks and the internet. This paper discusses the challenges of connecting vehicular ad-hoc networks to the internet. It reviews the characteristic of 5 proposed solutions with their merits & demerits in the light of a few specific parameters. It concludes with a discussion on the suitability of solutions under different scenarios.
{"title":"Integration of vehicular roadside access and the internet: Challenges & a review of strategies","authors":"Mohd Umar Farooq, K. Khan, M. Pasha","doi":"10.1109/ICDCSYST.2012.6188772","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188772","url":null,"abstract":"Over the years, the usefulness of wireless mobile ad-hoc networks and vehicular ad-hoc networks has been well documented. A lot of effort has gone in to the study of integration of vehicular ad-hoc networks and the internet. This paper discusses the challenges of connecting vehicular ad-hoc networks to the internet. It reviews the characteristic of 5 proposed solutions with their merits & demerits in the light of a few specific parameters. It concludes with a discussion on the suitability of solutions under different scenarios.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121972446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188766
V. Sudhakar, N. S. Murthy, L. Anjaneyulu
This paper presents fully parallel and fully serial architectures for Band pass filter. The performances of fully parallel and fully-serial architectures are analyzed for different quantized versions of representation. Filters generated using 8 bit fixed point implementation requires smaller area usage when compared to 16 bit fixed point implementation at the cost of imprecision. The proposed implementations are synthesized with Xilinx ISE 13.2 version. Family of device was Spartan 3E and target device was xa3s250e-4vqg100. The key performance metrics, namely number of Slices, Slice Flip Flops, LUTs, Maximum frequency are compared.
提出了带通滤波器的全并行和全串行结构。分析了全并行和全串行结构在不同量化表示形式下的性能。与16位定点实现相比，使用8位定点实现生成的滤波器需要更小的面积使用，但代价是不精确。提出的实现是用Xilinx ISE 13.2版本合成的。设备家族为Spartan 3E，目标设备为xa3s250e-4vqg100。比较了关键性能指标，即切片数，切片触发器，lut，最大频率。
{"title":"Fully parallel and fully serial architecture for realization of high speed FIR filters with FPGA's","authors":"V. Sudhakar, N. S. Murthy, L. Anjaneyulu","doi":"10.1109/ICDCSYST.2012.6188766","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188766","url":null,"abstract":"This paper presents fully parallel and fully serial architectures for Band pass filter. The performances of fully parallel and fully-serial architectures are analyzed for different quantized versions of representation. Filters generated using 8 bit fixed point implementation requires smaller area usage when compared to 16 bit fixed point implementation at the cost of imprecision. The proposed implementations are synthesized with Xilinx ISE 13.2 version. Family of device was Spartan 3E and target device was xa3s250e-4vqg100. The key performance metrics, namely number of Slices, Slice Flip Flops, LUTs, Maximum frequency are compared.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122319676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188760
G. Maity, S. Maity, J. N. Roy
Reversible logic is an emerging research area and getting remarkable interest over the past few years. Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design, bioinformatics and nanotechnology-based systems. Conventional logic circuits are not reversible. This paper proposes circuit realization of reversible logic gates, called New gate (NG) in all-optical domain. Semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) plays a significant role in this field of ultra fast all-optical signal processing and is used here.
{"title":"Design of all-optical new gate using Mach-Zehnder interferometer","authors":"G. Maity, S. Maity, J. N. Roy","doi":"10.1109/ICDCSYST.2012.6188760","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188760","url":null,"abstract":"Reversible logic is an emerging research area and getting remarkable interest over the past few years. Reversible computation plays an important role in the synthesis of circuits having application in quantum computing, low power CMOS design, bioinformatics and nanotechnology-based systems. Conventional logic circuits are not reversible. This paper proposes circuit realization of reversible logic gates, called New gate (NG) in all-optical domain. Semiconductor optical amplifier (SOA) based Mach-Zehnder interferometer (MZI) plays a significant role in this field of ultra fast all-optical signal processing and is used here.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122340180","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188683
I. Biswas, A. Deka, S. C. Bose
A design methodology for tuning a circuit by analyzing its sensitivity to various design parameters is presented. This analysis helps in comprehending the critical design parameters so that they can be tuned for obtaining the most optimal desired circuit behavior. The methodology is exemplified through the design of a 2.3 GHz radio-frequency Low Noise Amplifier(LNA) for Worldwide Interoperability for Microwave Access (WIMAX) applications using 0.35 um technology. The circuit designed is an inductively loaded amplifier along with inductive source degeneration. The effect of various design circuit parameters on gain, input resistance and noise figure is analyzed. The simulated Noise figure for the optimized LNA is 1.102dB and the voltage gain is 15.11dB at 2.3 GHz. The LNA is designed to match an input impedance of 50Ω and an output impedance of 50Ω. The circuit has an input return loss of -19.23dB and an output return loss of -10.97dB. The 1-dB compression point is 8.69dBm and Input Third-order Intercept Point (IIP3 ) of the LNA is 6.537dBm. The Rollet's Stability factor (K factor) of the circuit is greater than 1 which shows that the circuit is unconditionally stable. The designed LNA consumes a power of 1.656mW at a supply voltage of 3.3 V. The LNA developed in the present work achieves a high gain along with a high linear range while consuming less power.
{"title":"Design of a 2.3 GHz Low Noise Amplifier for WIMAX applications","authors":"I. Biswas, A. Deka, S. C. Bose","doi":"10.1109/ICDCSYST.2012.6188683","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188683","url":null,"abstract":"A design methodology for tuning a circuit by analyzing its sensitivity to various design parameters is presented. This analysis helps in comprehending the critical design parameters so that they can be tuned for obtaining the most optimal desired circuit behavior. The methodology is exemplified through the design of a 2.3 GHz radio-frequency Low Noise Amplifier(LNA) for Worldwide Interoperability for Microwave Access (WIMAX) applications using 0.35 um technology. The circuit designed is an inductively loaded amplifier along with inductive source degeneration. The effect of various design circuit parameters on gain, input resistance and noise figure is analyzed. The simulated Noise figure for the optimized LNA is 1.102dB and the voltage gain is 15.11dB at 2.3 GHz. The LNA is designed to match an input impedance of 50Ω and an output impedance of 50Ω. The circuit has an input return loss of -19.23dB and an output return loss of -10.97dB. The 1-dB compression point is 8.69dBm and Input Third-order Intercept Point (IIP3 ) of the LNA is 6.537dBm. The Rollet's Stability factor (K factor) of the circuit is greater than 1 which shows that the circuit is unconditionally stable. The designed LNA consumes a power of 1.656mW at a supply voltage of 3.3 V. The LNA developed in the present work achieves a high gain along with a high linear range while consuming less power.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128767689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188761
G. Maity, S. Maity, J. N. Roy
An all-optical Manchester code generator is implemented using terahertz optical asymmetric demultiplexer based D flip-flop and exclusive-OR (XOR) logic gates in a configuration exactly like the standard electronic setup. There is 10 Gbit/s all-optical non return to zero--to-Manchester conversion implemented in our simulation system and bit error rate performance of the format conversion is investigated. Transmission performances of the converted Manchester coded signal are discussed in terms of transmission length and received optical power. The performance of the circuit is evaluated through numerical simulation, which confirms its feasibility in terms of the choice of the critical parameters. The proposed scheme has been theoretically demonstrated for a Manchester code generator.
{"title":"All-optical Manchester code generator using TOAD-based D flip-flop","authors":"G. Maity, S. Maity, J. N. Roy","doi":"10.1109/ICDCSYST.2012.6188761","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188761","url":null,"abstract":"An all-optical Manchester code generator is implemented using terahertz optical asymmetric demultiplexer based D flip-flop and exclusive-OR (XOR) logic gates in a configuration exactly like the standard electronic setup. There is 10 Gbit/s all-optical non return to zero--to-Manchester conversion implemented in our simulation system and bit error rate performance of the format conversion is investigated. Transmission performances of the converted Manchester coded signal are discussed in terms of transmission length and received optical power. The performance of the circuit is evaluated through numerical simulation, which confirms its feasibility in terms of the choice of the critical parameters. The proposed scheme has been theoretically demonstrated for a Manchester code generator.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127699630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-03-15DOI: 10.1109/ICDCSYST.2012.6188736
C. Saxena, M. Pattanaik, R. K. Tiwari
Design of complex arithmetic logic circuits considering ground bounce noise, noise immunity, leakage current, active power and area is an important and challenging task in deep submicron circuits. In this paper, a comparative analysis of high performance stacking power gating schemes is done which minimizes the leakage power and provides a way to control the ground bounce noise. The innovative power gating schemes such as stacking power gating, diode based stacking power gating are analyzed which minimizes the peak of ground bounce noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 87.14% over the conventional power gating. It is also found that in stacking power gating, the ground bounce noise has been reduced by 76.28% over the conventional power gating scheme. We have performed simulations using Cadence-Spectre in a 90nm standard CMOS technology at room temperature with supply voltage of 1V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective roadmap for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.
{"title":"Enhanced power gating schemes for low leakage low ground bounce noise in deep submicron circuits","authors":"C. Saxena, M. Pattanaik, R. K. Tiwari","doi":"10.1109/ICDCSYST.2012.6188736","DOIUrl":"https://doi.org/10.1109/ICDCSYST.2012.6188736","url":null,"abstract":"Design of complex arithmetic logic circuits considering ground bounce noise, noise immunity, leakage current, active power and area is an important and challenging task in deep submicron circuits. In this paper, a comparative analysis of high performance stacking power gating schemes is done which minimizes the leakage power and provides a way to control the ground bounce noise. The innovative power gating schemes such as stacking power gating, diode based stacking power gating are analyzed which minimizes the peak of ground bounce noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 87.14% over the conventional power gating. It is also found that in stacking power gating, the ground bounce noise has been reduced by 76.28% over the conventional power gating scheme. We have performed simulations using Cadence-Spectre in a 90nm standard CMOS technology at room temperature with supply voltage of 1V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective roadmap for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.","PeriodicalId":356188,"journal":{"name":"2012 International Conference on Devices, Circuits and Systems (ICDCS)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127654751","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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