Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781174
K. Azad, Z. M. Darus, M.A.M. Ali
This paper presents an approach towards implementing a QRS detection algorithm into a single chip environment for maternal and fetal heart rate monitoring by using a fuzzy decision method to identify maternal and fetal QRS complexes from single-lead maternal abdominal recordings. A top-down design methodology was adopted during the design of the ASIC. Testability strategies were adopted in order to increase the ASIC reliability.
{"title":"Testable ASIC design for a fuzzy logic based QRS complex detector","authors":"K. Azad, Z. M. Darus, M.A.M. Ali","doi":"10.1109/SMELEC.1998.781174","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781174","url":null,"abstract":"This paper presents an approach towards implementing a QRS detection algorithm into a single chip environment for maternal and fetal heart rate monitoring by using a fuzzy decision method to identify maternal and fetal QRS complexes from single-lead maternal abdominal recordings. A top-down design methodology was adopted during the design of the ASIC. Testability strategies were adopted in order to increase the ASIC reliability.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133755528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781158
F. Schuler, O. Kowarik, K. Hoffmann
A BSIM3v3.1 based flash memory degradation compact model for circuit simulators has been developed. By a physics based modification of the Fowler-Nordheim equation, the tunnel current can be calculated considering both positive and negative oxide charges. It has been shown that every known endurance characteristic can be simulated by this model. It allows a precise simulation of worst case operation of flash memories and an optimized circuit design.
{"title":"BSIM3v3 based degradation compact model for circuit simulation of non-volatile flash memories","authors":"F. Schuler, O. Kowarik, K. Hoffmann","doi":"10.1109/SMELEC.1998.781158","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781158","url":null,"abstract":"A BSIM3v3.1 based flash memory degradation compact model for circuit simulators has been developed. By a physics based modification of the Fowler-Nordheim equation, the tunnel current can be calculated considering both positive and negative oxide charges. It has been shown that every known endurance characteristic can be simulated by this model. It allows a precise simulation of worst case operation of flash memories and an optimized circuit design.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132440575","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781165
Roy Kooh Jinn Chye, M. Ahmad, T. H. Ting, B.S. Suparjo, R. Wagiran
The concept, design and characterisation of thick oxide parasitic transistors is investigated in this paper. The outcome includes the design from concept of two classes of thick oxide parasitic transistors, which consist of four different test structures. Both classes were used to evaluate the possibility of parasitic FET occurrence. They are class 1 (poly/field oxide and metal 1/field oxide) and class 2 (metal 1/BPSG and metal 2/BPSG/USG). Class 1 designs involved the conventional isolation technology used in the development of MIMOS 0.8 /spl mu/m CMOS technology while class 2 were designed to imitate the condition of metal routing in circuit design. The results of some n- and p-channel thick oxide parasitic transistors are presented in this paper. All field threshold voltages obtained for the test structures are above 12 V. CADENCE Virtuoso Layout editor is used to generate the test structure layouts. The results of this study complement other test structures for MIMOS 0.8 /spl mu/m CMOS technology development.
{"title":"Design and characterisation of thick oxide parasitic transistor for MIMOS 0.8-/spl mu/m CMOS technology development","authors":"Roy Kooh Jinn Chye, M. Ahmad, T. H. Ting, B.S. Suparjo, R. Wagiran","doi":"10.1109/SMELEC.1998.781165","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781165","url":null,"abstract":"The concept, design and characterisation of thick oxide parasitic transistors is investigated in this paper. The outcome includes the design from concept of two classes of thick oxide parasitic transistors, which consist of four different test structures. Both classes were used to evaluate the possibility of parasitic FET occurrence. They are class 1 (poly/field oxide and metal 1/field oxide) and class 2 (metal 1/BPSG and metal 2/BPSG/USG). Class 1 designs involved the conventional isolation technology used in the development of MIMOS 0.8 /spl mu/m CMOS technology while class 2 were designed to imitate the condition of metal routing in circuit design. The results of some n- and p-channel thick oxide parasitic transistors are presented in this paper. All field threshold voltages obtained for the test structures are above 12 V. CADENCE Virtuoso Layout editor is used to generate the test structure layouts. The results of this study complement other test structures for MIMOS 0.8 /spl mu/m CMOS technology development.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122409334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781142
H. Younan
A few lots of wafers (FLAT ROM) were reported with low yield (5-20%) issue. RIE, SEM and EDX techniques were used to identify the root causes. Al metal filaments were found at particular locations, which had resulted in metal bridging failure. They were found to be due to the narrow space between the two polysilicon layers and insufficient metal etching. The solution to eliminate these metal filaments is to increase overetch of L90 from 100 to 135 or change the space between the two poly layers. After using a new overetch recipe [135], the wafer sort yield was greatly enhanced.
{"title":"Elimination of metal bridging failure in VLSI metallization and yield enhancement of FLAT ROM device","authors":"H. Younan","doi":"10.1109/SMELEC.1998.781142","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781142","url":null,"abstract":"A few lots of wafers (FLAT ROM) were reported with low yield (5-20%) issue. RIE, SEM and EDX techniques were used to identify the root causes. Al metal filaments were found at particular locations, which had resulted in metal bridging failure. They were found to be due to the narrow space between the two polysilicon layers and insufficient metal etching. The solution to eliminate these metal filaments is to increase overetch of L90 from 100 to 135 or change the space between the two poly layers. After using a new overetch recipe [135], the wafer sort yield was greatly enhanced.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"213 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122810544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781140
L. An, K. Lai, W. Chay, Y. Hua
A study was conducted on EKC265 cleaning bath life. The Auger analysis technique was used to evaluate the contamination levels of fluorine and carbon on the bond pad after the EKC265 process. The results showed that it is necessary and effective to perform EKC265 cleaning for L95 lots. The contamination levels of C and F on the surface (0 /spl Aring/) of bond pads were about 20 at% and 7.5 at% at the bath life of 40 lots used currently. However, they were 0 at.% at a depth of 50 /spl Aring/. The results also show that it is possible to extend EKC265 bath life from 40 lots (6 inch) to 50 lots (6 inch) for cost reduction purposes.
{"title":"A study on EKC265 bath life and fluorine and carbon contamination on bond pads","authors":"L. An, K. Lai, W. Chay, Y. Hua","doi":"10.1109/SMELEC.1998.781140","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781140","url":null,"abstract":"A study was conducted on EKC265 cleaning bath life. The Auger analysis technique was used to evaluate the contamination levels of fluorine and carbon on the bond pad after the EKC265 process. The results showed that it is necessary and effective to perform EKC265 cleaning for L95 lots. The contamination levels of C and F on the surface (0 /spl Aring/) of bond pads were about 20 at% and 7.5 at% at the bath life of 40 lots used currently. However, they were 0 at.% at a depth of 50 /spl Aring/. The results also show that it is possible to extend EKC265 bath life from 40 lots (6 inch) to 50 lots (6 inch) for cost reduction purposes.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"160 3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128982844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781182
U. Hashim, S. Shaari, B. Y. Majlis
A rapid thermal annealing treatment technique was introduced to remove a thin native oxide on silicon substrates. The native oxide was not present at the silicide/silicon interface after the wafer was thermally treated by RTA at 800/spl deg/C for 60 seconds in an N/sub 2/ ambient. This SEM cross-sectional micrograph observation was supported by X-ray diffraction analysis. XRD showed no traceable presence of an oxide peak. Therefore, RTA heat treatment is shown to be a suitable alternative method to remove the native oxide.
{"title":"Characterization of thin oxide removal by rapid thermal annealing treatment","authors":"U. Hashim, S. Shaari, B. Y. Majlis","doi":"10.1109/SMELEC.1998.781182","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781182","url":null,"abstract":"A rapid thermal annealing treatment technique was introduced to remove a thin native oxide on silicon substrates. The native oxide was not present at the silicide/silicon interface after the wafer was thermally treated by RTA at 800/spl deg/C for 60 seconds in an N/sub 2/ ambient. This SEM cross-sectional micrograph observation was supported by X-ray diffraction analysis. XRD showed no traceable presence of an oxide peak. Therefore, RTA heat treatment is shown to be a suitable alternative method to remove the native oxide.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128784383","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781190
S. Shaari, Yussa Ananda
The coupling characteristics of a silica based waveguide type directional coupler with asymmetrical structure are studied by the beam propagation method. The coupling behavior of optical power from a single mode 3 mm guide into a multi-mode guide in silica are clearly demonstrated. The coupling into a second guide of <27 /spl mu/m causes only a small loss, but the coupling into a 54 /spl mu/m guide involves a significant loss.
{"title":"Silica based optical waveguide coupler with asymmetric structure in single-mode to multi-mode coupling regime","authors":"S. Shaari, Yussa Ananda","doi":"10.1109/SMELEC.1998.781190","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781190","url":null,"abstract":"The coupling characteristics of a silica based waveguide type directional coupler with asymmetrical structure are studied by the beam propagation method. The coupling behavior of optical power from a single mode 3 mm guide into a multi-mode guide in silica are clearly demonstrated. The coupling into a second guide of <27 /spl mu/m causes only a small loss, but the coupling into a 54 /spl mu/m guide involves a significant loss.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126952863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781173
M. Din, R. D. Gould
Cadmium arsenide is a II-V semiconductor which exhibits n-type intrinsic conductivity with high mobility. Potential applications include magnetoresistors and both thermal and photodetectors, which require electrical characterisation over a wide range of deposition and measurement conditions. The films were prepared by vacuum evaporation with deposition rates of 0.5 nm s/sup -1/ and substrate temperatures maintained at constant values of 293 K-393 K. Sandwich-type samples were deposited with film thicknesses of 0.1-1.1 /spl mu/m using evaporated electrodes of Ag and occasionally Au or Al. Above a typical electric field F/sub b/ of up to 5/spl times/10/sup 7/ V m/sup -1/, all samples showed instabilities characteristic of dielectric breakdown or electroforming. Below this field, they showed a high-field conduction process with log J/spl prop/V/sup 1/2/, where J is the current density and V the applied voltage. This type of dependence is indicative of carrier excitation over a potential barrier whose effective barrier height has been lowered by the high electric field. The field-lowering coefficient /spl beta/ had a value of (1.2-5.3)/spl times/10/sup -5/ eV m/sup 1/2/ V/sup -1/2/, which is reasonably consistent with the theoretical value of /spl beta//sub PF/=2.19/spl times/10/sup -5/ eV m/sup 1/2/ V/sup -1/2/ expected when the field-lowering occurs at donor-like centres in the semiconductor (Poole-Frenkel effect). For thinner films, Schottky emission was more probable. The effects of the film thickness, electrode materials, deposition rate, and substrate temperature on the conductivity behaviour are discussed.
{"title":"High field conduction mechanism of the evaporated cadmium arsenide thin films","authors":"M. Din, R. D. Gould","doi":"10.1109/SMELEC.1998.781173","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781173","url":null,"abstract":"Cadmium arsenide is a II-V semiconductor which exhibits n-type intrinsic conductivity with high mobility. Potential applications include magnetoresistors and both thermal and photodetectors, which require electrical characterisation over a wide range of deposition and measurement conditions. The films were prepared by vacuum evaporation with deposition rates of 0.5 nm s/sup -1/ and substrate temperatures maintained at constant values of 293 K-393 K. Sandwich-type samples were deposited with film thicknesses of 0.1-1.1 /spl mu/m using evaporated electrodes of Ag and occasionally Au or Al. Above a typical electric field F/sub b/ of up to 5/spl times/10/sup 7/ V m/sup -1/, all samples showed instabilities characteristic of dielectric breakdown or electroforming. Below this field, they showed a high-field conduction process with log J/spl prop/V/sup 1/2/, where J is the current density and V the applied voltage. This type of dependence is indicative of carrier excitation over a potential barrier whose effective barrier height has been lowered by the high electric field. The field-lowering coefficient /spl beta/ had a value of (1.2-5.3)/spl times/10/sup -5/ eV m/sup 1/2/ V/sup -1/2/, which is reasonably consistent with the theoretical value of /spl beta//sub PF/=2.19/spl times/10/sup -5/ eV m/sup 1/2/ V/sup -1/2/ expected when the field-lowering occurs at donor-like centres in the semiconductor (Poole-Frenkel effect). For thinner films, Schottky emission was more probable. The effects of the film thickness, electrode materials, deposition rate, and substrate temperature on the conductivity behaviour are discussed.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"29 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120925873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781160
N. Ismail, M. Mahdi, P. Poopalan, H. Ahmad
Erbium-doped fibre amplifiers (EDFA) have been widely used for long haul transmission and are already in place for WDM applications. We characterised cascaded optical amplifiers by comparing their performance while operating with and without an interstage optical filter. It is noticeable that the 3 nm filter improved the gain (G) and output signal power (P/sub sout/) by as much as 9.72 dB and 9.75 dB respectively at a signal level of -50 dBm.
{"title":"Characterisation of cascaded EDFA with the inclusion of an interstage optical element","authors":"N. Ismail, M. Mahdi, P. Poopalan, H. Ahmad","doi":"10.1109/SMELEC.1998.781160","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781160","url":null,"abstract":"Erbium-doped fibre amplifiers (EDFA) have been widely used for long haul transmission and are already in place for WDM applications. We characterised cascaded optical amplifiers by comparing their performance while operating with and without an interstage optical filter. It is noticeable that the 3 nm filter improved the gain (G) and output signal power (P/sub sout/) by as much as 9.72 dB and 9.75 dB respectively at a signal level of -50 dBm.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"284 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132126338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781156
E.-S.A. El-Badaway, S. H. Ibrahim, H. El-Motaafy
The purpose of this paper is to shed further light on the effects of the operating conditions, such as the operating frequency and the DC-bias current, on the performance of IMPATT amplifiers. It is shown that the characteristics of the IMPATT amplifier depend strongly on the characteristics of the IMPATT diode. It is found that increasing the frequency reduces the bunching and acceleration, and the premature collection of the avalanche-generated pulse. This is attributed to the decrease of the space charge effect and the depletion layer width modulation effect with increasing frequency. It is also concluded that by increasing the DC-bias current, the bunching and acceleration of the avalanche generated pulse increases, while the premature collection of the pulse decreases. This improves the IMPATT amplifier performance. Optimization of the amplifier gain and its dependence on the operating conditions are introduced and discussed.
{"title":"Effects of the operating conditions on the performance of IMPATT amplifiers","authors":"E.-S.A. El-Badaway, S. H. Ibrahim, H. El-Motaafy","doi":"10.1109/SMELEC.1998.781156","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781156","url":null,"abstract":"The purpose of this paper is to shed further light on the effects of the operating conditions, such as the operating frequency and the DC-bias current, on the performance of IMPATT amplifiers. It is shown that the characteristics of the IMPATT amplifier depend strongly on the characteristics of the IMPATT diode. It is found that increasing the frequency reduces the bunching and acceleration, and the premature collection of the avalanche-generated pulse. This is attributed to the decrease of the space charge effect and the depletion layer width modulation effect with increasing frequency. It is also concluded that by increasing the DC-bias current, the bunching and acceleration of the avalanche generated pulse increases, while the premature collection of the pulse decreases. This improves the IMPATT amplifier performance. Optimization of the amplifier gain and its dependence on the operating conditions are introduced and discussed.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129933004","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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