Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781167
N. Mariun, Ishak Aris, W. Shepherd
The two important characteristics of an IGBT, which should be considered in device modelling, are the conduction (static) and the switching (dynamic) characteristics. The conduction characteristic parameters were discussed previously (Mariun et al, 1997) and here only the dynamic parameters are presented briefly to give background before detailed development of the model is presented. The curve-fitting optimisation method available in HSPICE is used to determine the model parameters and the results are compared with laboratory test results and are found to be in good agreement.
在器件建模中应该考虑的IGBT的两个重要特性是传导(静态)和开关(动态)特性。之前已经讨论过传导特性参数(Mariun et al, 1997)，这里只简要介绍动态参数，以便在详细介绍模型发展之前提供背景。利用HSPICE中的曲线拟合优化方法确定了模型参数，并与实验室试验结果进行了比较，结果吻合较好。
{"title":"Determination of dynamic parameters for HSPICE IGBT model using curve-fitting optimisation method","authors":"N. Mariun, Ishak Aris, W. Shepherd","doi":"10.1109/SMELEC.1998.781167","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781167","url":null,"abstract":"The two important characteristics of an IGBT, which should be considered in device modelling, are the conduction (static) and the switching (dynamic) characteristics. The conduction characteristic parameters were discussed previously (Mariun et al, 1997) and here only the dynamic parameters are presented briefly to give background before detailed development of the model is presented. The curve-fitting optimisation method available in HSPICE is used to determine the model parameters and the results are compared with laboratory test results and are found to be in good agreement.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132386659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781168
M. Ngadino, A. A. Hassan, M. K. Abdullah, H. Ahmad
We present here results on the effects of various pulling speeds (PS) and pull delays (PD) for a fixed flame profile on the performance of 1/spl times/2 50/50 or 3 dB fused biconical tapered (FBT) single mode optical fiber couplers. We study how these factors correlate with the shape of the fused tapered region and therefore influence the coupler performance. The fabrication technique, which is based on the heat fusion of the twisted section of two standard single mode fibers of the same type are elaborated. A good fiber coupler can be produced by pulling it in a speed range from 25 /spl mu/m/s to 250 /spl mu/m/s. It is also found that at a pull delay of 80 s, excess loss as low as 0.02 dB can be achieved.
{"title":"Loss dependence on pull speed and pull delay of 3 dB fused tapered single mode fiber coupler","authors":"M. Ngadino, A. A. Hassan, M. K. Abdullah, H. Ahmad","doi":"10.1109/SMELEC.1998.781168","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781168","url":null,"abstract":"We present here results on the effects of various pulling speeds (PS) and pull delays (PD) for a fixed flame profile on the performance of 1/spl times/2 50/50 or 3 dB fused biconical tapered (FBT) single mode optical fiber couplers. We study how these factors correlate with the shape of the fused tapered region and therefore influence the coupler performance. The fabrication technique, which is based on the heat fusion of the twisted section of two standard single mode fibers of the same type are elaborated. A good fiber coupler can be produced by pulling it in a speed range from 25 /spl mu/m/s to 250 /spl mu/m/s. It is also found that at a pull delay of 80 s, excess loss as low as 0.02 dB can be achieved.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125242682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781172
Md. Altaf-Ul-Amin, Z. M. Darus
This paper presents an approach to integrate logic and IDDQ testing which are crucial in verifying the functionality and improving the reliability of CMOS ICs. Work presented in this paper involves the design of an off-chip current sensor and a compatible test processor for the aforementioned purpose. The sensor is an analog circuit and the test processor is a digital ASIC. The performance of both the sensor and the test processor has been verified through computer simulation. Fault simulation results show that reasonable numbers of test vectors generated by the scheme used in this work are able to detect all detectable stuck-at faults in some ISCAS'85 benchmark circuits.
{"title":"Current sensor and test processor design for integration of logic and IDDQ testing of CMOS ICs","authors":"Md. Altaf-Ul-Amin, Z. M. Darus","doi":"10.1109/SMELEC.1998.781172","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781172","url":null,"abstract":"This paper presents an approach to integrate logic and IDDQ testing which are crucial in verifying the functionality and improving the reliability of CMOS ICs. Work presented in this paper involves the design of an off-chip current sensor and a compatible test processor for the aforementioned purpose. The sensor is an analog circuit and the test processor is a digital ASIC. The performance of both the sensor and the test processor has been verified through computer simulation. Fault simulation results show that reasonable numbers of test vectors generated by the scheme used in this work are able to detect all detectable stuck-at faults in some ISCAS'85 benchmark circuits.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116550808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781143
H. Younan
Crystalline defects on silicon substrates affect the wafer fabrication yield. Secco Etch is a chemical etching method used to delineate crystalline defects on silicon wafer substrates. When Secco Etch is used directly, crystalline defects can be revealed on silicon substrates after 2 minutes on some areas. However, it does not fully deprocess the substrate layers where severe overetching occurs, even for etch times of up to 20 minutes. After delayering by using dry and wet etches and subsequent Secco Etch, crystalline defects were revealed. However, the delayering method is both time consuming and more costly, as it requires a long time to delayer. To reduce failure analysis cycle time, a new chemical etching method, 152 Secco Etch, has been proposed in this study. In 152 Secco Etch, hydrofluoric acid (HF) is used for deprocessing prior to Secco etch for wafer fabrication failure analysis applications. Analytical results show that 152 Secco Etch is a rapid and reliable chemical method and is effective in revealing crystalline silicon defects.
{"title":"Studies of a new chemical etching method-152 Secco Etch in failure analysis of wafer fabrication","authors":"H. Younan","doi":"10.1109/SMELEC.1998.781143","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781143","url":null,"abstract":"Crystalline defects on silicon substrates affect the wafer fabrication yield. Secco Etch is a chemical etching method used to delineate crystalline defects on silicon wafer substrates. When Secco Etch is used directly, crystalline defects can be revealed on silicon substrates after 2 minutes on some areas. However, it does not fully deprocess the substrate layers where severe overetching occurs, even for etch times of up to 20 minutes. After delayering by using dry and wet etches and subsequent Secco Etch, crystalline defects were revealed. However, the delayering method is both time consuming and more costly, as it requires a long time to delayer. To reduce failure analysis cycle time, a new chemical etching method, 152 Secco Etch, has been proposed in this study. In 152 Secco Etch, hydrofluoric acid (HF) is used for deprocessing prior to Secco etch for wafer fabrication failure analysis applications. Analytical results show that 152 Secco Etch is a rapid and reliable chemical method and is effective in revealing crystalline silicon defects.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122669758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781191
M. Yahaya, M. Salleh, T. K. Hoe
The photodiode is one of the most commonly used devices for photodetectors. Light absorption in the semiconductor produces electron-hole pairs in the depletion region which are separated by the electric field, leading to the flow of current in the external circuit. This paper describes preparation and characterization of photodiodes by the screen printing technique. Screen-printing is a cost effective thick film deposition method, where a paste containing the desired materials is printed on the substrate. The substrate is then fired under a controlled environment to yield devices bonded to the substrate. In this experiment, a layer of phosphorous thick films were deposited on the Si-substrate. Then, the p-n junction was formed by the usual doping via the diffusion method. The samples were characterized for the rectifier effect, quantum efficiency, response time and rise time. In the optimization process, samples were doped at temperatures from 800-1000/spl deg/C. It was found that samples doped at 900/spl deg/C had the highest speed and response time of 0.32 s and rise time of 0.48 s. This sample also has the highest responsivity and quantum efficiency. Problems in the thermal diffusion process and electrode design are described in detail.
{"title":"Fabrication of photodiode by screen printing technique","authors":"M. Yahaya, M. Salleh, T. K. Hoe","doi":"10.1109/SMELEC.1998.781191","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781191","url":null,"abstract":"The photodiode is one of the most commonly used devices for photodetectors. Light absorption in the semiconductor produces electron-hole pairs in the depletion region which are separated by the electric field, leading to the flow of current in the external circuit. This paper describes preparation and characterization of photodiodes by the screen printing technique. Screen-printing is a cost effective thick film deposition method, where a paste containing the desired materials is printed on the substrate. The substrate is then fired under a controlled environment to yield devices bonded to the substrate. In this experiment, a layer of phosphorous thick films were deposited on the Si-substrate. Then, the p-n junction was formed by the usual doping via the diffusion method. The samples were characterized for the rectifier effect, quantum efficiency, response time and rise time. In the optimization process, samples were doped at temperatures from 800-1000/spl deg/C. It was found that samples doped at 900/spl deg/C had the highest speed and response time of 0.32 s and rise time of 0.48 s. This sample also has the highest responsivity and quantum efficiency. Problems in the thermal diffusion process and electrode design are described in detail.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114815759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781159
R. Bakar, M. Abdullah, F. Isnin, H. Ahmad, B. Ali
In this paper, a passive optical add-drop multiplexer (OADM) is developed. The employment of optical couplers as opposed to the beam splitters normally used makes it a very viable low-cost system. The tapper also provides flexibility in the design, whereby the tappers' coupling ratios can be easily changed. The effect of the tapper's coupling ratios on the system is analyzed here, with the emphasis on the insertion loss. In varying the coupling ratio, higher drop and add powers can be obtained with an equal power of add, drop and other channel's power found to be at 50-50 coupling.
{"title":"Tapper ratio dependency of a low-cost passive OADM system","authors":"R. Bakar, M. Abdullah, F. Isnin, H. Ahmad, B. Ali","doi":"10.1109/SMELEC.1998.781159","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781159","url":null,"abstract":"In this paper, a passive optical add-drop multiplexer (OADM) is developed. The employment of optical couplers as opposed to the beam splitters normally used makes it a very viable low-cost system. The tapper also provides flexibility in the design, whereby the tappers' coupling ratios can be easily changed. The effect of the tapper's coupling ratios on the system is analyzed here, with the emphasis on the insertion loss. In varying the coupling ratio, higher drop and add powers can be obtained with an equal power of add, drop and other channel's power found to be at 50-50 coupling.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128663849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781185
B. Y. Majlis, A. Ariffin, A. Mat, S. Jaafar, S. Bujang, M. Yahya
Summary form only given. A number of MMICs with operating frequencies from L to X band have been designed and fabricated using the GMMT foundry. All circuits were designed using MMIC CAD Series IV Libra on PC and workstation. The circuit functions include a range of TWAs, LNAs, wide band amplifiers, switches, mixers, oscillators, four bit attenuators, phase shifters and power amplifiers. Fabrication was conducted on 3" GaAs wafers using the GMMT PHEMT process, with 0.3 /spl mu/m gate length, via holes through the substrate, MIM nitride and polyimide capacitors and is fully protected by silicon nitride passivation. The primary applications of GaAs high electron mobility transistor (HEMT) circuits are in satellite receivers, consumer video applications, high frequency scanners, wireless LAN and other low noise front ends. Most of the operating frequencies for this application are in the range from 1 to 15 GHz.
只提供摘要形式。许多工作频率从L到X波段的mmic已经使用GMMT代工厂设计和制造。所有电路均采用MMIC CAD Series IV Libra在PC和工作站上进行设计。电路功能包括一系列twa、lna、宽带放大器、开关、混频器、振荡器、四位衰减器、移相器和功率放大器。采用GMMT PHEMT工艺在3" GaAs晶圆上进行了制造，栅极长度为0.3 /spl mu/m，通过衬底、MIM氮化和聚酰亚胺电容器的孔，并由氮化硅钝化完全保护。GaAs高电子迁移率晶体管(HEMT)电路的主要应用是卫星接收器、消费视频应用、高频扫描仪、无线局域网和其他低噪声前端。此应用的大多数工作频率在1至15 GHz的范围内。
{"title":"Design and fabrication of GaAs microwave monolithic integrated circuits using 0.2 /spl mu/m GMMT PHEMT foundry process","authors":"B. Y. Majlis, A. Ariffin, A. Mat, S. Jaafar, S. Bujang, M. Yahya","doi":"10.1109/SMELEC.1998.781185","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781185","url":null,"abstract":"Summary form only given. A number of MMICs with operating frequencies from L to X band have been designed and fabricated using the GMMT foundry. All circuits were designed using MMIC CAD Series IV Libra on PC and workstation. The circuit functions include a range of TWAs, LNAs, wide band amplifiers, switches, mixers, oscillators, four bit attenuators, phase shifters and power amplifiers. Fabrication was conducted on 3\" GaAs wafers using the GMMT PHEMT process, with 0.3 /spl mu/m gate length, via holes through the substrate, MIM nitride and polyimide capacitors and is fully protected by silicon nitride passivation. The primary applications of GaAs high electron mobility transistor (HEMT) circuits are in satellite receivers, consumer video applications, high frequency scanners, wireless LAN and other low noise front ends. Most of the operating frequencies for this application are in the range from 1 to 15 GHz.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130388361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781186
J.Y. Asous, S. Shaari
A new passive x-coupler waveguide optical device is proposed and its coupling behaviour in response to different wavelengths is studied using the beam propagation method. The coupling behaviour of 0.86 /spl mu/m, 1.3 /spl mu/m and 1.55 /spl mu/m wavelengths in this silica-based waveguide coupler is different for each wavelength. The device can behave as a WDM multiplexer, where each wavelength automatically selects its own output arm.
{"title":"BPM study of wavelength dependent of new design of variable x-coupler waveguide passive device","authors":"J.Y. Asous, S. Shaari","doi":"10.1109/SMELEC.1998.781186","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781186","url":null,"abstract":"A new passive x-coupler waveguide optical device is proposed and its coupling behaviour in response to different wavelengths is studied using the beam propagation method. The coupling behaviour of 0.86 /spl mu/m, 1.3 /spl mu/m and 1.55 /spl mu/m wavelengths in this silica-based waveguide coupler is different for each wavelength. The device can behave as a WDM multiplexer, where each wavelength automatically selects its own output arm.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117306066","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781157
E. Gondro, P. Klein, F. Schuler, O. Kowarik
A new model description for source and drain resistances of LDD devices is proposed. It includes the dependence on the gate, bulk and drain bias. Measurements on a 0.25 /spl mu/m gate length device show excellent agreement with circuit simulation.
{"title":"A non-linear description of the bias dependent parasitic resistances of quarter micron MOSFETs","authors":"E. Gondro, P. Klein, F. Schuler, O. Kowarik","doi":"10.1109/SMELEC.1998.781157","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781157","url":null,"abstract":"A new model description for source and drain resistances of LDD devices is proposed. It includes the dependence on the gate, bulk and drain bias. Measurements on a 0.25 /spl mu/m gate length device show excellent agreement with circuit simulation.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116571127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-11-24DOI: 10.1109/SMELEC.1998.781147
K. S. Lim, C. Ling
The stacked capacitor structure used in DRAM cells usually takes the form of an interpoly capacitor where the dielectric layer is sandwiched between two polycrystalline silicon plates. The charge trapping characteristics of the oxide-nitride-oxide (ONO) film in an interpoly capacitor structure has been investigated. The hole trapping characteristics are observed under constant current stress. The trapped charge centroid is found to be localised at the top oxide/nitride interface under both stress polarities. The larger hole trapping observed under negative stress correlates to a shorter electrical lifetime.
{"title":"Charge trapping in interpoly ONO film","authors":"K. S. Lim, C. Ling","doi":"10.1109/SMELEC.1998.781147","DOIUrl":"https://doi.org/10.1109/SMELEC.1998.781147","url":null,"abstract":"The stacked capacitor structure used in DRAM cells usually takes the form of an interpoly capacitor where the dielectric layer is sandwiched between two polycrystalline silicon plates. The charge trapping characteristics of the oxide-nitride-oxide (ONO) film in an interpoly capacitor structure has been investigated. The hole trapping characteristics are observed under constant current stress. The trapped charge centroid is found to be localised at the top oxide/nitride interface under both stress polarities. The larger hole trapping observed under negative stress correlates to a shorter electrical lifetime.","PeriodicalId":356206,"journal":{"name":"ICSE'98. 1998 IEEE International Conference on Semiconductor Electronics. Proceedings (Cat. No.98EX187)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125077637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：