Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838193
K. Górecki, P. Górecki
The paper presents the results of investigations illustrating the influence of the form of a compact thermal model of the IGBT module on the accuracy of computing the non-isothermal characteristics of the components of this module. The tests are carried out for a module containing 2 IGBTs, 2 diodes and a thermistor. Three degrees of complexity of the thermal model are considered. The first one takes into account only self-heating in each component of the module. The second - additionally takes into account mutual thermal couplings between the components of the module. The third - additionally takes into account the dependence of thermal parameters on the power dissipated in the components of the module. The form of the considered models as well as the results of computations and measurements of the characteristics of the module components obtained for various cooling conditions of the module and the supply conditions of these components are presented. The obtained results are discussed.
{"title":"Influence of the IGBT Module Thermal Model Form on the Accuracy of Electrothermal Computations","authors":"K. Górecki, P. Górecki","doi":"10.23919/mixdes55591.2022.9838193","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838193","url":null,"abstract":"The paper presents the results of investigations illustrating the influence of the form of a compact thermal model of the IGBT module on the accuracy of computing the non-isothermal characteristics of the components of this module. The tests are carried out for a module containing 2 IGBTs, 2 diodes and a thermistor. Three degrees of complexity of the thermal model are considered. The first one takes into account only self-heating in each component of the module. The second - additionally takes into account mutual thermal couplings between the components of the module. The third - additionally takes into account the dependence of thermal parameters on the power dissipated in the components of the module. The form of the considered models as well as the results of computations and measurements of the characteristics of the module components obtained for various cooling conditions of the module and the supply conditions of these components are presented. The obtained results are discussed.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130121486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837960
Aristeidis Nikolaou, Jakob Leise, Jakob Pruefer, U. Zschieschang, H. Klauk, G. Darbandy, B. Iñíguez, A. Kloes
In this study, the effect of bending on the electrical characteristics of organic thin-film transistors is studied, using experimental data obtained from a large number of discrete or-ganic transistors fabricated on a flexible polymeric substrates, in the coplanar device architecture. The transistors under bending-stress presented a significant drain-current degradation that can be mainly attributed to the respected reduction of the effective carrier mobility value. By correlating a power-law mobility model and the basics of percolation theory, the observed mobility degradation could be attributed to a decrease of the characteristic temperature that describes the shape of the Gaussian density of states in the utilized organic semiconductor. Overall, a maximum effective carrier mobility degradation of 45.9% due to bending, depending on the experimental conditions, can be reported.
{"title":"Impact of Mechanical Bending on the Performance of Organic Thin-Film Transistors and the Characteristic Temperature of the Density of States","authors":"Aristeidis Nikolaou, Jakob Leise, Jakob Pruefer, U. Zschieschang, H. Klauk, G. Darbandy, B. Iñíguez, A. Kloes","doi":"10.23919/mixdes55591.2022.9837960","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837960","url":null,"abstract":"In this study, the effect of bending on the electrical characteristics of organic thin-film transistors is studied, using experimental data obtained from a large number of discrete or-ganic transistors fabricated on a flexible polymeric substrates, in the coplanar device architecture. The transistors under bending-stress presented a significant drain-current degradation that can be mainly attributed to the respected reduction of the effective carrier mobility value. By correlating a power-law mobility model and the basics of percolation theory, the observed mobility degradation could be attributed to a decrease of the characteristic temperature that describes the shape of the Gaussian density of states in the utilized organic semiconductor. Overall, a maximum effective carrier mobility degradation of 45.9% due to bending, depending on the experimental conditions, can be reported.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127745015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838210
Patryk Widulinski, K. Wawryn
In this paper, a study of parameter efficiency for an intrusion detection system (IDS) inspired by the human immune system has been conducted. The IDS monitors a folder in the operating system to check for modifications or infections. The IDS is based on the negative selection algorithm to generate binary strings called receptors. The receptors are used to check for anomalies in the monitored folder. The receptors are gen-erated based on fundamental parameters of receptor size and activation threshold. This work investigates the efficiency of said parameters in a test environment. A wide range of receptor sizes and activation thresholds are tested, their efficiency factors are calculated, and the results are presented, analyzed and concluded.
{"title":"Parameter Efficiency Testing for an Intrusion Detection System Inspired by the Human Immune System","authors":"Patryk Widulinski, K. Wawryn","doi":"10.23919/mixdes55591.2022.9838210","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838210","url":null,"abstract":"In this paper, a study of parameter efficiency for an intrusion detection system (IDS) inspired by the human immune system has been conducted. The IDS monitors a folder in the operating system to check for modifications or infections. The IDS is based on the negative selection algorithm to generate binary strings called receptors. The receptors are used to check for anomalies in the monitored folder. The receptors are gen-erated based on fundamental parameters of receptor size and activation threshold. This work investigates the efficiency of said parameters in a test environment. A wide range of receptor sizes and activation thresholds are tested, their efficiency factors are calculated, and the results are presented, analyzed and concluded.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132524083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837975
Jedrzej Topilko, K. Kucharski, K. Grabowski, L. Starzak, Zbigniew Mudza
An analog quadrature modulator-demodulator for narrowband power line communication (PLC) together with an adaptive grid coupler have been developed. They have been integrated in a PLC communication device and tested both in a laboratory benchmark and in a real channel. Bit error rates low enough for transmission speeds of up to 14400 b/s were achieved. The proposed solution has the advantages of low cost, limited microcontroller load as well as high versatility with respect to the modulation used and transmission parameters.
{"title":"Analog Quadrature Modulator and Coupling Circuit for Narrowband Power Line Communication","authors":"Jedrzej Topilko, K. Kucharski, K. Grabowski, L. Starzak, Zbigniew Mudza","doi":"10.23919/mixdes55591.2022.9837975","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837975","url":null,"abstract":"An analog quadrature modulator-demodulator for narrowband power line communication (PLC) together with an adaptive grid coupler have been developed. They have been integrated in a PLC communication device and tested both in a laboratory benchmark and in a real channel. Bit error rates low enough for transmission speeds of up to 14400 b/s were achieved. The proposed solution has the advantages of low cost, limited microcontroller load as well as high versatility with respect to the modulation used and transmission parameters.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131656430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838232
Alija Dervić, H. Zimmermann
This paper presents a fully-integrated optical sensor with SPAD and mixed quenching/resetting circuit with sensing stage based on a tunable-threshold inverter optimized for the standard 0.35-µm CMOS technology. The presented quencher features a controllable detection threshold voltage and an adjustable total dead time. The quenching circuit 5QC achieves 16.5 V excess bias voltage (five times the supply voltage). The dead time ranges from 7.5 ns to 51.5 ns, which corresponds to a saturation count rate range from 19.4 Mcps to 133.3 Mcps. The quencher is optimized for SPADs with a capacitance ranging from 50 fF up to 400 fF. Using our published measured photon detection probability (PDP) results and extrapolating them, a peak PDP of 75.6% at 652 nm and a PDP of 39.2% at 854 nm is estimated for VEX = 16.5 V. To the authors' best knowledge, the presented PDP result has never been reached before for a fully-integrated SPAD sensor in standard CMOS technology.
{"title":"SPAD Mixed-Quenching Circuit in 0.35-µm CMOS for Achieving a PDP of 39.2% at 854 nm","authors":"Alija Dervić, H. Zimmermann","doi":"10.23919/mixdes55591.2022.9838232","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838232","url":null,"abstract":"This paper presents a fully-integrated optical sensor with SPAD and mixed quenching/resetting circuit with sensing stage based on a tunable-threshold inverter optimized for the standard 0.35-µm CMOS technology. The presented quencher features a controllable detection threshold voltage and an adjustable total dead time. The quenching circuit 5QC achieves 16.5 V excess bias voltage (five times the supply voltage). The dead time ranges from 7.5 ns to 51.5 ns, which corresponds to a saturation count rate range from 19.4 Mcps to 133.3 Mcps. The quencher is optimized for SPADs with a capacitance ranging from 50 fF up to 400 fF. Using our published measured photon detection probability (PDP) results and extrapolating them, a peak PDP of 75.6% at 652 nm and a PDP of 39.2% at 854 nm is estimated for VEX = 16.5 V. To the authors' best knowledge, the presented PDP result has never been reached before for a fully-integrated SPAD sensor in standard CMOS technology.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128793734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838183
Arkadiusz Krupinski, Grzegorz Swistak, P. Nowakowski, D. Makowski
Embedded systems become more and more complex, and this is also a case for their software. For this reason, there is an increased demand for software updates and data compression to decrease the application download time. The purpose of this paper is to compare the compression algorithms in terms of their use for firmware updates in the Micro Telecommunications Computing Architecture (MicroTCA) system for the Advanced Mezzanine Card (AMC) board. To reduce the firmware upload time for Module Management Controller (MMC) a literature review was conducted. Selected lossless data compression algorithms were tested. The implemented solution is compatible with Hardware Platform Management version 1 (HPM.l) standard. Initial results of firmware upgrade performance and challenges faced during the design are presented in this paper.
{"title":"Firmware Update for Improved Reliability Embedded Systems","authors":"Arkadiusz Krupinski, Grzegorz Swistak, P. Nowakowski, D. Makowski","doi":"10.23919/mixdes55591.2022.9838183","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838183","url":null,"abstract":"Embedded systems become more and more complex, and this is also a case for their software. For this reason, there is an increased demand for software updates and data compression to decrease the application download time. The purpose of this paper is to compare the compression algorithms in terms of their use for firmware updates in the Micro Telecommunications Computing Architecture (MicroTCA) system for the Advanced Mezzanine Card (AMC) board. To reduce the firmware upload time for Module Management Controller (MMC) a literature review was conducted. Selected lossless data compression algorithms were tested. The implemented solution is compatible with Hardware Platform Management version 1 (HPM.l) standard. Initial results of firmware upgrade performance and challenges faced during the design are presented in this paper.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128415930","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838167
K. Podbucki, J. Suder, T. Marciniak, A. Dabrowski
This paper presents a comparison of the performance of embedded systems processing video sequences in real time. As part of the work, practical programs for detecting lanes located on airport areas, which allow autonomous vehicles to move around the airport, were tested. The following modules were used during the tests: Raspberry Pi 4B, NVIDIA Jetson Nano, NVIDIA Jetson Xavier AGX. For modules from the NVIDIA Jetson family, the maximum performance of video stream processing depending on the resolution and the selected power mode has been checked. The results of the experiment show that NVIDIA Jetson modules have sufficient computing resources to effectively track lines based on the camera image, even in low power modes.
{"title":"Evaluation of Embedded Devices for Real- Time Video Lane Detection","authors":"K. Podbucki, J. Suder, T. Marciniak, A. Dabrowski","doi":"10.23919/mixdes55591.2022.9838167","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838167","url":null,"abstract":"This paper presents a comparison of the performance of embedded systems processing video sequences in real time. As part of the work, practical programs for detecting lanes located on airport areas, which allow autonomous vehicles to move around the airport, were tested. The following modules were used during the tests: Raspberry Pi 4B, NVIDIA Jetson Nano, NVIDIA Jetson Xavier AGX. For modules from the NVIDIA Jetson family, the maximum performance of video stream processing depending on the resolution and the selected power mode has been checked. The results of the experiment show that NVIDIA Jetson modules have sufficient computing resources to effectively track lines based on the camera image, even in low power modes.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121948417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838321
Nicolas Bogun, E. Quesada, E. Pérez, C. Wenger, A. Kloes, M. Schwarz
The impact of artificial intelligence on human life has increased significantly in recent years. However, as the complexity of problems rose aswell, increasing system features for such amount of data computation became troublesome due to the von Neumann's computer architecture. Neuromorphic computing aims to solve this problem by mimicking the parallel computation of a human brain. For this approach, memristive devices are used to emulate the synapses of a human brain. Yet, common simulations of hardware based networks require time consuming Monte-Carlo simulations to take into account the stochastic switching of memristive devices. This work presents an alternative concept making use of the convolution of the probability distribution functions (PDF) of memristor currents by its equivalent multiplication in Fourier domain. An artificial neural network is accordingly implemented to perform the inference stage with handwritten digits.
{"title":"Analytical Calculation of Inference in Memristor-based Stochastic Artificial Neural Networks","authors":"Nicolas Bogun, E. Quesada, E. Pérez, C. Wenger, A. Kloes, M. Schwarz","doi":"10.23919/mixdes55591.2022.9838321","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838321","url":null,"abstract":"The impact of artificial intelligence on human life has increased significantly in recent years. However, as the complexity of problems rose aswell, increasing system features for such amount of data computation became troublesome due to the von Neumann's computer architecture. Neuromorphic computing aims to solve this problem by mimicking the parallel computation of a human brain. For this approach, memristive devices are used to emulate the synapses of a human brain. Yet, common simulations of hardware based networks require time consuming Monte-Carlo simulations to take into account the stochastic switching of memristive devices. This work presents an alternative concept making use of the convolution of the probability distribution functions (PDF) of memristor currents by its equivalent multiplication in Fourier domain. An artificial neural network is accordingly implemented to perform the inference stage with handwritten digits.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"30 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125655290","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838055
L. Kohútka
This paper presents a new FPGA design of a task scheduler that supports not only aperiodic hard real-time tasks but periodic tasks too. Whenever a period of a periodic task is elapsed, the task is automatically restarted with no need of software intervention. The proposed scheduler is using Earliest Deadline First (EDF) algorithm. For inter-task synchronisation, the scheduler also supports temporary suspension of tasks with automatic resumption of tasks after the specified time elapsed. The proposed architecture is based on priority queues used for time management and decision-making processes. Thanks to FPGA implementation of the scheduler and its priority queues, the scheduler operations are always performed in two clock cycles regardless of the current number of tasks and regardless of the maximum possible number of tasks in the system. The paper contains results obtained by FPGA synthesis done for various parameters using Intel FPGA Cyclone V device. The proposed solution was verified using simplified version of Universal Verification Methodology (UVM) and applying millions of test instructions with randomly generated deadline and period values.
{"title":"A New FPGA - based Architecture of Task Scheduler with Support of Periodic Real-Time Tasks","authors":"L. Kohútka","doi":"10.23919/mixdes55591.2022.9838055","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838055","url":null,"abstract":"This paper presents a new FPGA design of a task scheduler that supports not only aperiodic hard real-time tasks but periodic tasks too. Whenever a period of a periodic task is elapsed, the task is automatically restarted with no need of software intervention. The proposed scheduler is using Earliest Deadline First (EDF) algorithm. For inter-task synchronisation, the scheduler also supports temporary suspension of tasks with automatic resumption of tasks after the specified time elapsed. The proposed architecture is based on priority queues used for time management and decision-making processes. Thanks to FPGA implementation of the scheduler and its priority queues, the scheduler operations are always performed in two clock cycles regardless of the current number of tasks and regardless of the maximum possible number of tasks in the system. The paper contains results obtained by FPGA synthesis done for various parameters using Intel FPGA Cyclone V device. The proposed solution was verified using simplified version of Universal Verification Methodology (UVM) and applying millions of test instructions with randomly generated deadline and period values.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130894101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838105
{"title":"Design of Integrated Circuit and Microsystems","authors":"","doi":"10.23919/mixdes55591.2022.9838105","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838105","url":null,"abstract":"","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134211134","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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