Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837972
Karwan Javanmardi, A. Amini, A. Cabrini
Shift-and-add multipliers have a simpler structure than other types of multipliers and, at the same time, have a lower operating speed. They are suitable for applications where speed is not the first design priority. In this paper, we present a low-power, low-area multiplier with a simplest possible structure based on shift-and-add which can be a good choice for portable applications and medical devices such as a pacemaker, where power reduction and chip area are core issues. The main idea of the article is to use multiplexers and appropriate timing signals. By applying these signals to the multiplexer selection lines, it is possible to achieve the correct output with an n-bit adder and input-output registers during (2n+1) clock pulse. Simulation results of proposed 16*16-bit multiplier using HSPICE in standard 0.18µm CMOS technology demonstrate that it has 129ns propagation delay while the corresponding power consumption is 467µW.
{"title":"Ultra Low-Power, Area-Efficient Multiplier Based on Shift-and-Add Architecture","authors":"Karwan Javanmardi, A. Amini, A. Cabrini","doi":"10.23919/mixdes55591.2022.9837972","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837972","url":null,"abstract":"Shift-and-add multipliers have a simpler structure than other types of multipliers and, at the same time, have a lower operating speed. They are suitable for applications where speed is not the first design priority. In this paper, we present a low-power, low-area multiplier with a simplest possible structure based on shift-and-add which can be a good choice for portable applications and medical devices such as a pacemaker, where power reduction and chip area are core issues. The main idea of the article is to use multiplexers and appropriate timing signals. By applying these signals to the multiplexer selection lines, it is possible to achieve the correct output with an n-bit adder and input-output registers during (2n+1) clock pulse. Simulation results of proposed 16*16-bit multiplier using HSPICE in standard 0.18µm CMOS technology demonstrate that it has 129ns propagation delay while the corresponding power consumption is 467µW.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130779557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837980
M. Niewczas
We review major problems and technical challenges related to mask making A.D. 2022. This overview is addressed to engineers dealing with physical design of ICs. Two significant advances have been just introduced to the volume manufacturing in transition from 7nm to 5nm process nodes: EUV lithography and multibeam mask writing. Combined, they improve accuracy, process margin and wafer throughput. However, they introduce various challenges and opportunities that we discuss here. Moreover, on the software side, two critical issues are being addressed currently, the data volume explosion and tremendous computational requirement. These are being addressed with the move to new data formats, curvilinear geometry and new algorithms utilizing supercomputing on GPU clusters.
{"title":"IC Masks - The Challenges of the Newest Technologies","authors":"M. Niewczas","doi":"10.23919/mixdes55591.2022.9837980","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837980","url":null,"abstract":"We review major problems and technical challenges related to mask making A.D. 2022. This overview is addressed to engineers dealing with physical design of ICs. Two significant advances have been just introduced to the volume manufacturing in transition from 7nm to 5nm process nodes: EUV lithography and multibeam mask writing. Combined, they improve accuracy, process margin and wafer throughput. However, they introduce various challenges and opportunities that we discuss here. Moreover, on the software side, two critical issues are being addressed currently, the data volume explosion and tremendous computational requirement. These are being addressed with the move to new data formats, curvilinear geometry and new algorithms utilizing supercomputing on GPU clusters.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114960861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837958
Andrzej A. Wojciechowski, Krzysztof Marcinek, W. Pleskacz
Phase difference of the clock signals is a critical factor in high precision synchronization of interconnected integrated circuits. In order to synchronize a daisy-chained set of individual systems, a novel concept of clock signal phase alignment circuit as well as calibration algorithm were developed. The work describes a high-level analog circuit and the calibration procedure implemented in the digital control module. The high-level implementation was tested using Verilog HDL language and conclusions are presented. Moreover, the required features and recognized restrictions are also discussed.
{"title":"Clock Signal Phase Alignment System for Daisy Chained Integrated Circuits","authors":"Andrzej A. Wojciechowski, Krzysztof Marcinek, W. Pleskacz","doi":"10.23919/mixdes55591.2022.9837958","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837958","url":null,"abstract":"Phase difference of the clock signals is a critical factor in high precision synchronization of interconnected integrated circuits. In order to synchronize a daisy-chained set of individual systems, a novel concept of clock signal phase alignment circuit as well as calibration algorithm were developed. The work describes a high-level analog circuit and the calibration procedure implemented in the digital control module. The high-level implementation was tested using Verilog HDL language and conclusions are presented. Moreover, the required features and recognized restrictions are also discussed.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126276361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838041
K. Klys, W. Cichalewski, W. Jalmuzna, A. Napieralski, P. Perek, A. Persson, Anders L. Olsson
In the European Spallation Source (ESS) accel-erator, which is currently being built in Lund, Sweden, the typical hardware platform for fast acquisition devices is Micro Telecommunications Computing Architecture.4 (MTCA.4). A major part of the LLRF control system devices are designed as MTCA.4 modules - Advanced Mezzanine Carrier (AMCs) or Rear Transition Modules (RTMs). The main feature of the mentioned standard is its high reliability and maintainability. Those aspects are crucial in terms of keeping the accelerator in its operational state. Thanks to the management layer in MTCA.4 which is based on Intelligent Platform Management Interface (IPMI) protocol it is possible to control and monitor modules' state. The paper presents the software's development process sup-porting MTCA.4 chassis management. It shows the evolution of the proposed tool (in two phases), and how it has been modified and improved thanks to users' feedback. It explains why we started our work with an EPICS application with a single Input/Output Controller (IOC) and why our final solution is composed of several separate modules. Finally, the paper describes tests and activities performed to confirm the proper functioning of the software. It also discusses areas of possible improvements and encountered issues.
{"title":"Software Solutions for Dynamic Configuration and Deployment of EPICS Application for MTCA.4 Chassis Management","authors":"K. Klys, W. Cichalewski, W. Jalmuzna, A. Napieralski, P. Perek, A. Persson, Anders L. Olsson","doi":"10.23919/mixdes55591.2022.9838041","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838041","url":null,"abstract":"In the European Spallation Source (ESS) accel-erator, which is currently being built in Lund, Sweden, the typical hardware platform for fast acquisition devices is Micro Telecommunications Computing Architecture.4 (MTCA.4). A major part of the LLRF control system devices are designed as MTCA.4 modules - Advanced Mezzanine Carrier (AMCs) or Rear Transition Modules (RTMs). The main feature of the mentioned standard is its high reliability and maintainability. Those aspects are crucial in terms of keeping the accelerator in its operational state. Thanks to the management layer in MTCA.4 which is based on Intelligent Platform Management Interface (IPMI) protocol it is possible to control and monitor modules' state. The paper presents the software's development process sup-porting MTCA.4 chassis management. It shows the evolution of the proposed tool (in two phases), and how it has been modified and improved thanks to users' feedback. It explains why we started our work with an EPICS application with a single Input/Output Controller (IOC) and why our final solution is composed of several separate modules. Finally, the paper describes tests and activities performed to confirm the proper functioning of the software. It also discusses areas of possible improvements and encountered issues.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133498909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838304
T. Przybyla, T. Pander
In this paper, we present a preliminary results on the evaluation of fluid therapy completion time. Weight of fluid container was used for this purpose. For the weight recording as well as for signal decimation, FPGA-based system was applied. The effectiveness of our proposed approach was evaluated in a laboratory conditions using a fluid tank filled with clean water.
{"title":"Fluid Therapy Completion Time Assessment","authors":"T. Przybyla, T. Pander","doi":"10.23919/mixdes55591.2022.9838304","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838304","url":null,"abstract":"In this paper, we present a preliminary results on the evaluation of fluid therapy completion time. Weight of fluid container was used for this purpose. For the weight recording as well as for signal decimation, FPGA-based system was applied. The effectiveness of our proposed approach was evaluated in a laboratory conditions using a fluid tank filled with clean water.","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134452260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9838186
{"title":"Compact Modeling of Hetergeneous Devices and Systems","authors":"","doi":"10.23919/mixdes55591.2022.9838186","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9838186","url":null,"abstract":"","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125263320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-06-23DOI: 10.23919/mixdes55591.2022.9837969
Pawel Wargacki, P. Kmon
We present a design of a low-noise chopper based amplifier for biomedical recordings. It is a part of a multi-channel integrated system fabricated in 40nm CMOS technology. It features a DC stabilizing loop for compensating electrode offset and positive feedback for input impedance boosting. The first stage uses double current reuse. Design consumes 2µA per channel under 1V supply voltage and occupies only 0.044mm2 of silicon area. A novel input stage presented in this work combines a low noise performance of a stacked input pair with the high DC gain of the folded cascode amplifier. The simulated input-referred noise is 0.96/µVrms in the 0.5-100Hz frequency band and 2.8µVrms in the 100Hz-10kHz frequency band, respectively, leading to a noise-efficiency factor of 5.29 (0.5-100Hz) and 1.55 (0.1-10kHz).
{"title":"Design of 1.55 NEF, 2µA, Chopper Based Amplifier in 40nm CMOS for Biomedical Multichannel Integrated System","authors":"Pawel Wargacki, P. Kmon","doi":"10.23919/mixdes55591.2022.9837969","DOIUrl":"https://doi.org/10.23919/mixdes55591.2022.9837969","url":null,"abstract":"We present a design of a low-noise chopper based amplifier for biomedical recordings. It is a part of a multi-channel integrated system fabricated in 40nm CMOS technology. It features a DC stabilizing loop for compensating electrode offset and positive feedback for input impedance boosting. The first stage uses double current reuse. Design consumes 2µA per channel under 1V supply voltage and occupies only 0.044mm2 of silicon area. A novel input stage presented in this work combines a low noise performance of a stacked input pair with the high DC gain of the folded cascode amplifier. The simulated input-referred noise is 0.96/µVrms in the 0.5-100Hz frequency band and 2.8µVrms in the 100Hz-10kHz frequency band, respectively, leading to a noise-efficiency factor of 5.29 (0.5-100Hz) and 1.55 (0.1-10kHz).","PeriodicalId":356244,"journal":{"name":"2022 29th International Conference on Mixed Design of Integrated Circuits and System (MIXDES)","volume":"58 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-06-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114020825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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