Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709129
E. Aguilar, V. Issakov, R. Weigel
Two low-power D-band receiver front-ends with competitive performance for radar and imaging applications are presented. The receivers include passive and active singleended-to-differential converters realized as an ultra-compact Marchand-based balun and as a differential-pair-based active balun, respectively. The receivers achieve measured conversion gains (CG) of 24.9dB at 134GHz (active balun) and 20.27dB at 124GHz (passive balun) while consuming 425mW and 330mW correspondingly. A wide bandwidth of 32GHz is achieved for the active variant in the 114-146GHz frequency range while the passive approach achieves a CG $gt 10dB$ in the 112-147GHz frequency range. The passive approach achieves a peak conversion gain of 20.$27dB at 126GHz. The presented results offer competitive performance and compare favorably to reported receiver front-ends in terms of ultra-small silicon area (0.14 and 0.$1mm^{mathbf{2}})$. The front-ends are suitable for integration in highly-integrated D-Band radar receiver arrays as well as for high-density imaging arrays.
{"title":"Highly-Integrated <0.14mm2D -Band Receiver Front-Ends for Radar and Imaging Applications in a 130 nm SiGe BiCMOS Technology","authors":"E. Aguilar, V. Issakov, R. Weigel","doi":"10.1109/SIRF.2019.8709129","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709129","url":null,"abstract":"Two low-power D-band receiver front-ends with competitive performance for radar and imaging applications are presented. The receivers include passive and active singleended-to-differential converters realized as an ultra-compact Marchand-based balun and as a differential-pair-based active balun, respectively. The receivers achieve measured conversion gains (CG) of 24.9dB at 134GHz (active balun) and 20.27dB at 124GHz (passive balun) while consuming 425mW and 330mW correspondingly. A wide bandwidth of 32GHz is achieved for the active variant in the 114-146GHz frequency range while the passive approach achieves a CG $gt 10dB$ in the 112-147GHz frequency range. The passive approach achieves a peak conversion gain of 20.$27dB at 126GHz. The presented results offer competitive performance and compare favorably to reported receiver front-ends in terms of ultra-small silicon area (0.14 and 0.$1mm^{mathbf{2}})$. The front-ends are suitable for integration in highly-integrated D-Band radar receiver arrays as well as for high-density imaging arrays.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114396220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709124
C. Baristiran-Kaynak, A. Göritz, Y. Yamamoto, M. Wietstruck, M. Stocchi, K. E. Unal, M. B. Ozdemir, Y. Ozsoy, Y. Gurbuz, M. Kaynak
This paper presents the development of process integration and mechanical modeling of a Si1-xGex/Si MQW based uncooled micro-bolometer. The recent progress on layer transfer based integration scheme of Si1-xGex/Si based micro-bolometer into a 130 nm BiCMOS process is presented. The two important parts of the process integration, namely the layer-transfer and stress compensation of the arms are studied. The initial successful results on layer transfer and the FEM modeling for the stress compensation of the thin and narrow arms of the bolometer is presented. Finally, the developed FEM model is compared with the fabricated cantilevers. The results show that the developed FEM model has a very good matching with the experimental results; thus very convenient to use for the FEM modeling of the full bolometer structure.
{"title":"Development and Mechanical Modeling of Si1-XGex/Si MQW Based Uncooled Microbolometers in a 130 nm BiCMOS","authors":"C. Baristiran-Kaynak, A. Göritz, Y. Yamamoto, M. Wietstruck, M. Stocchi, K. E. Unal, M. B. Ozdemir, Y. Ozsoy, Y. Gurbuz, M. Kaynak","doi":"10.1109/SIRF.2019.8709124","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709124","url":null,"abstract":"This paper presents the development of process integration and mechanical modeling of a Si1-xGex/Si MQW based uncooled micro-bolometer. The recent progress on layer transfer based integration scheme of Si1-xGex/Si based micro-bolometer into a 130 nm BiCMOS process is presented. The two important parts of the process integration, namely the layer-transfer and stress compensation of the arms are studied. The initial successful results on layer transfer and the FEM modeling for the stress compensation of the thin and narrow arms of the bolometer is presented. Finally, the developed FEM model is compared with the fabricated cantilevers. The results show that the developed FEM model has a very good matching with the experimental results; thus very convenient to use for the FEM modeling of the full bolometer structure.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121748399","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709136
M. Schröter, M. Krattenmacher
The presently existing approach for describing dynamic emitter current-crowding in present compact models is only applicable to small-signal operation. Therefore, different options for modeling textbf fast nonlinear large-signal switching of bipolar transistors have been investigated. Such options include multi-transistor models and different versions of a two-transistor model as well as a single transistor with lateral charge partitioning across the DC internal base resistance. Compared to the results of 2D numerical device simulation of the internal transistor region under the emitter, a multi-transistor model with at least five segments and a single transistor model with lateral charge partitioning appear to be most accurate for describing the time dependent large-signal collector current.
{"title":"Modeling distributed dynamic lateral large-signal switching effects in bipolar transistors","authors":"M. Schröter, M. Krattenmacher","doi":"10.1109/SIRF.2019.8709136","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709136","url":null,"abstract":"The presently existing approach for describing dynamic emitter current-crowding in present compact models is only applicable to small-signal operation. Therefore, different options for modeling textbf fast nonlinear large-signal switching of bipolar transistors have been investigated. Such options include multi-transistor models and different versions of a two-transistor model as well as a single transistor with lateral charge partitioning across the DC internal base resistance. Compared to the results of 2D numerical device simulation of the internal transistor region under the emitter, a multi-transistor model with at least five segments and a single transistor model with lateral charge partitioning appear to be most accurate for describing the time dependent large-signal collector current.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"136 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122583473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709098
Dennis Schuklin, Juergen Roeber, Markus Stadelmayer, T. Mai, R. Weigel, A. Hagelauer
After the successful launch of IceCube, the work is currently concentrated the next generation neutrino observatory at South Pole, IceCube Gen2. The neutrino detection and post processing accuracy mostly relies on used electronic hardware. The proposed highly integrated, low power photomultiplier readout ASIC is designed for function in low temperatures of Antarctic. The microchip comprises an input pre-amplifier, a clock generator and an ADC with encoder logic featuring sampling rate of 500MHz, 6bit output accuracy with a smart extension of input related resolution up to 8bit in the area of interest. It achieves the same accuracy like a standard 8bit ADC architecture but with significantly less hardware overhead and power dissipation.
{"title":"Highly Integrated Low Power Photomultiplier Readout ASIC comprising fast ADC to be used in the Antarctic Ice","authors":"Dennis Schuklin, Juergen Roeber, Markus Stadelmayer, T. Mai, R. Weigel, A. Hagelauer","doi":"10.1109/SIRF.2019.8709098","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709098","url":null,"abstract":"After the successful launch of IceCube, the work is currently concentrated the next generation neutrino observatory at South Pole, IceCube Gen2. The neutrino detection and post processing accuracy mostly relies on used electronic hardware. The proposed highly integrated, low power photomultiplier readout ASIC is designed for function in low temperatures of Antarctic. The microchip comprises an input pre-amplifier, a clock generator and an ADC with encoder logic featuring sampling rate of 500MHz, 6bit output accuracy with a smart extension of input related resolution up to 8bit in the area of interest. It achieves the same accuracy like a standard 8bit ADC architecture but with significantly less hardware overhead and power dissipation.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132148264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/SIRF.2019.8709089
J. Xia, Yiling Xu, Hai Huang, S. Boumaiza
This paper describes a new broadband vector modulator phase shifter (VMPS) featuring low magnitude/phase errors and enhanced linearity. It includes a novel variable gain amplifier (VGA) that is devised to mitigate two issues that are detrimental to the overall performance of the VMPS, namely, the variation of the phase with gain setting and large-signal nonlinearity. This is achieved by incorporating a modified tail current source that is carefully designed to perform a square-law function and compensate for the nonlinearity associated with the source-coupled pair of amplifiers. A proof-of-concept prototype of the proposed VGA, an input active balun stage and a post-amplifier stage were then designed using bulk 130 nm CMOS process to form an VMPS that operates in the sub-6GHz band. The fabricated VMPS chip confirmed magnitude and phase control ranges of 35 dB and 360 degrees, respectively. Without any baseband calibration, it maintained low root-mean-square (RMS) magnitude and phase errors within 0.27 dB and 1.8 degree, respectively, over the entire band of 0.1-5.7 GHz. Furthermore, a relatively high input 1-dB compression point of 4.5-6.8 dBm was achieved in the target bandwidth.
{"title":"A 0.1-5.7 GHz CMOS Phase Shifter with 0.27dB/1.8° RMS Magnitude /Phase Errors and Enhanced Linearity","authors":"J. Xia, Yiling Xu, Hai Huang, S. Boumaiza","doi":"10.1109/SIRF.2019.8709089","DOIUrl":"https://doi.org/10.1109/SIRF.2019.8709089","url":null,"abstract":"This paper describes a new broadband vector modulator phase shifter (VMPS) featuring low magnitude/phase errors and enhanced linearity. It includes a novel variable gain amplifier (VGA) that is devised to mitigate two issues that are detrimental to the overall performance of the VMPS, namely, the variation of the phase with gain setting and large-signal nonlinearity. This is achieved by incorporating a modified tail current source that is carefully designed to perform a square-law function and compensate for the nonlinearity associated with the source-coupled pair of amplifiers. A proof-of-concept prototype of the proposed VGA, an input active balun stage and a post-amplifier stage were then designed using bulk 130 nm CMOS process to form an VMPS that operates in the sub-6GHz band. The fabricated VMPS chip confirmed magnitude and phase control ranges of 35 dB and 360 degrees, respectively. Without any baseband calibration, it maintained low root-mean-square (RMS) magnitude and phase errors within 0.27 dB and 1.8 degree, respectively, over the entire band of 0.1-5.7 GHz. Furthermore, a relatively high input 1-dB compression point of 4.5-6.8 dBm was achieved in the target bandwidth.","PeriodicalId":356507,"journal":{"name":"2019 IEEE 19th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121453409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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